1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2013-7-17 Peng Fan sep6200 implementation 9 */ 10 11 #ifndef __SEP6200_H 12 #define __SEP6200_H 13 14 #include <rtthread.h> 15 16 /*Core definations*/ 17 #define PRIVMODE 0x13 18 #define Mode_USR 0x10 19 #define Mode_REAL 0x11 20 #define Mode_IRQ 0x12 21 #define Mode_PRIV 0x13 22 #define Mode_TRAP 0x17 23 #define Mode_EXT 0x1B 24 #define Mode_SUSR 0x1F 25 26 /* 27 * Address 28 */ 29 30 #define SEP6200_VIC_BASE 0xb0000000 31 #define SEP6200_PMU_BASE 0xb0001000 32 #define SEP6200_RTC_BASE 0xb0002000 33 #define SEP6200_TIMER_BASE 0xb0003000 34 #define SEP6200_PWM_BASE 0xb0004000 35 #define SEP6200_GPIO_BASE 0xb0006000 36 #define SEP6200_TOUCH_ADC 0xb0007000 37 #define SEP6200_SYSCTL_BASE 0xb0008000 38 #define SEP6200_UART0_BASE 0xb1000000 39 #define SEP6200_UART1_BASE 0xb1001000 40 #define SEP6200_UART2_BASE 0xb1002000 41 #define SEP6200_UART3_BASE 0xb1003000 42 #define SEP6200_SSI1_BASE 0xb1004000 43 #define SEP6200_SSI2_BASE 0xb1005000 44 #define SEP6200_SSI3_BASE 0xb1006000 45 #define SEP6200_I2C_BASE 0xb1007000 46 #define SEP6200_I2S_BASE 0xb1008000 47 #define SEP6200_USB_BASE 0xb1010000 48 #define SEP6200_DMAC2_BASE 0xb1011000 49 #define SEP6200_ESRAM_BASE 0xb2000000 50 #define SEP6200_NORREG_BASE0xb2020000 51 #define SEP6200_SDIO1_BASE 0xb2022000 52 #define SEP6200_SDIO2_BASE 0xb2023000 53 #define SEP6200_LCDC_BASE 0xb2025000 54 #define SEP6200_VPU_BASE 0xb2026000 55 #define SEP6200_DMAC1_BASE 0xb2027000 56 #define SEP6200_DDR2_REG 0xb3000000 57 #define SEP6200_DDR_MEM 0x40000000 58 59 #define SEP6200_UART0_DLBL (SEP6200_UART0_BASE+0x00) 60 #define SEP6200_UART0_RXFIFO (SEP6200_UART0_BASE+0x00) 61 #define SEP6200_UART0_TXFIFO (SEP6200_UART0_BASE+0x00) 62 #define SEP6200_UART0_DLBH (SEP6200_UART0_BASE+0x04) 63 #define SEP6200_UART0_IER (SEP6200_UART0_BASE+0x04) 64 #define SEP6200_UART0_IIR (SEP6200_UART0_BASE+0x08) 65 #define SEP6200_UART0_FCR (SEP6200_UART0_BASE+0x08) 66 #define SEP6200_UART0_LCR (SEP6200_UART0_BASE+0x0c) 67 #define SEP6200_UART0_MCR (SEP6200_UART0_BASE+0x10) 68 #define SEP6200_UART0_LSR (SEP6200_UART0_BASE+0x14) 69 #define SEP6200_UART0_MSR (SEP6200_UART0_BASE+0x18) 70 71 72 #define SEP6200_TIMER_T1LCR (SEP6200_TIMER_BASE + 0X000) 73 #define SEP6200_TIMER_T1CCR (SEP6200_TIMER_BASE + 0X004) 74 #define SEP6200_TIMER_T1CR (SEP6200_TIMER_BASE + 0X008) 75 #define SEP6200_TIMER_T1ISCR (SEP6200_TIMER_BASE + 0X00C) 76 #define SEP6200_TIMER_T1IMSR (SEP6200_TIMER_BASE + 0X010) 77 #define SEP6200_TIMER_T2LCR (SEP6200_TIMER_BASE + 0X020) 78 #define SEP6200_TIMER_T2CCR (SEP6200_TIMER_BASE + 0X024) 79 #define SEP6200_TIMER_T2CR (SEP6200_TIMER_BASE + 0X028) 80 #define SEP6200_TIMER_T2ISCR (SEP6200_TIMER_BASE + 0X02C) 81 #define SEP6200_TIMER_T2IMSR (SEP6200_TIMER_BASE + 0X030) 82 #define SEP6200_TIMER_T3LCR (SEP6200_TIMER_BASE + 0X040) 83 #define SEP6200_TIMER_T3CCR (SEP6200_TIMER_BASE + 0X044) 84 #define SEP6200_TIMER_T3CR (SEP6200_TIMER_BASE + 0X048) 85 #define SEP6200_TIMER_T3ISCR (SEP6200_TIMER_BASE + 0X04C) 86 #define SEP6200_TIMER_T3IMSR (SEP6200_TIMER_BASE + 0X050) 87 #define SEP6200_TIMER_T3CAPR (SEP6200_TIMER_BASE + 0X054) 88 #define SEP6200_TIMER_T4LCR (SEP6200_TIMER_BASE + 0X060) 89 #define SEP6200_TIMER_T4CCR (SEP6200_TIMER_BASE + 0X064) 90 #define SEP6200_TIMER_T4CR (SEP6200_TIMER_BASE + 0X068) 91 #define SEP6200_TIMER_T4ISCR (SEP6200_TIMER_BASE + 0X06C) 92 #define SEP6200_TIMER_T4IMSR (SEP6200_TIMER_BASE + 0X070) 93 #define SEP6200_TIMER_T4CAPR (SEP6200_TIMER_BASE + 0X074) 94 #define SEP6200_TIMER_T5LCR (SEP6200_TIMER_BASE + 0X080) 95 #define SEP6200_TIMER_T5CCR (SEP6200_TIMER_BASE + 0X084) 96 #define SEP6200_TIMER_T5CR (SEP6200_TIMER_BASE + 0X088) 97 #define SEP6200_TIMER_T5ISCR (SEP6200_TIMER_BASE + 0X08C) 98 #define SEP6200_TIMER_T5IMSR (SEP6200_TIMER_BASE + 0X090) 99 #define SEP6200_TIMER_T5CAPR (SEP6200_TIMER_BASE + 0X094) 100 #define SEP6200_TIMER_T6LCR (SEP6200_TIMER_BASE + 0X0A0) 101 #define SEP6200_TIMER_T6CCR (SEP6200_TIMER_BASE + 0X0A4) 102 #define SEP6200_TIMER_T6CR (SEP6200_TIMER_BASE + 0X0A8) 103 #define SEP6200_TIMER_T6ISCR (SEP6200_TIMER_BASE + 0X0AC) 104 #define SEP6200_TIMER_T6IMSR (SEP6200_TIMER_BASE + 0X0B0) 105 #define SEP6200_TIMER_T6CAPR (SEP6200_TIMER_BASE + 0X0B4) 106 #define SEP6200_TIMER_T7LCR (SEP6200_TIMER_BASE + 0X0C0) 107 #define SEP6200_TIMER_T7CCR (SEP6200_TIMER_BASE + 0X0C4) 108 #define SEP6200_TIMER_T7CR (SEP6200_TIMER_BASE + 0X0C8) 109 #define SEP6200_TIMER_T7ISCR (SEP6200_TIMER_BASE + 0X0CC) 110 #define SEP6200_TIMER_T7IMSR (SEP6200_TIMER_BASE + 0X0D0) 111 #define SEP6200_TIMER_T8LCR (SEP6200_TIMER_BASE + 0X0E0) 112 #define SEP6200_TIMER_T8CCR (SEP6200_TIMER_BASE + 0X0E4) 113 #define SEP6200_TIMER_T8CR (SEP6200_TIMER_BASE + 0X0E8) 114 #define SEP6200_TIMER_T8ISCR (SEP6200_TIMER_BASE + 0X0EC) 115 #define SEP6200_TIMER_T8IMSR (SEP6200_TIMER_BASE + 0X0F0) 116 #define SEP6200_TIMER_T9LCR (SEP6200_TIMER_BASE + 0X100) 117 #define SEP6200_TIMER_T9CCR (SEP6200_TIMER_BASE + 0X104) 118 #define SEP6200_TIMER_T9CR (SEP6200_TIMER_BASE + 0X108) 119 #define SEP6200_TIMER_T9ISCR (SEP6200_TIMER_BASE + 0X10C) 120 #define SEP6200_TIMER_T9IMSR (SEP6200_TIMER_BASE + 0X110) 121 #define SEP6200_TIMER_T10LCR (SEP6200_TIMER_BASE + 0X120) 122 #define SEP6200_TIMER_T10CCR (SEP6200_TIMER_BASE + 0X124) 123 #define SEP6200_TIMER_T10CR (SEP6200_TIMER_BASE + 0X128) 124 #define SEP6200_TIMER_T10ISCR (SEP6200_TIMER_BASE + 0X12C) 125 #define SEP6200_TIMER_T10IMSR (SEP6200_TIMER_BASE + 0X130) 126 #define SEP6200_TIMER_TIMSR (SEP6200_TIMER_BASE + 0X140) 127 #define SEP6200_TIMER_TISCR (SEP6200_TIMER_BASE + 0X144) 128 #define SEP6200_TIMER_TISR (SEP6200_TIMER_BASE + 0X148) 129 130 #define SEP6200_VIC_INT_SLT_L (SEP6200_VIC_BASE + 0x000) 131 #define SEP6200_VIC_INT_SLT_H (SEP6200_VIC_BASE + 0x004) 132 #define SEP6200_VIC_INT_EN_L (SEP6200_VIC_BASE + 0x008) 133 #define SEP6200_VIC_INT_EN_H (SEP6200_VIC_BASE + 0x00C) 134 #define SEP6200_VIC_INT_EN_CLR_L (SEP6200_VIC_BASE + 0x010) 135 #define SEP6200_VIC_INT_EN_CLR_H (SEP6200_VIC_BASE + 0x014) 136 #define SEP6200_VIC_SFT_INT_L (SEP6200_VIC_BASE + 0x018) 137 #define SEP6200_VIC_SFT_INT_H (SEP6200_VIC_BASE + 0x01C) 138 #define SEP6200_VIC_SFT_INT_CLR_L (SEP6200_VIC_BASE + 0x020) 139 #define SEP6200_VIC_SFT_INT_CLR_H (SEP6200_VIC_BASE + 0x024) 140 #define SEP6200_VIC_INT_MSK_ALL (SEP6200_VIC_BASE + 0x028) 141 #define SEP6200_VIC_RAW_INT_SRC_L (SEP6200_VIC_BASE + 0x030) 142 #define SEP6200_VIC_RAW_INT_SRC_H (SEP6200_VIC_BASE + 0x034) 143 #define SEP6200_VIC_RAW_IRQ_STS_L (SEP6200_VIC_BASE + 0x038) 144 #define SEP6200_VIC_RAW_IRQ_STS_H (SEP6200_VIC_BASE + 0x03C) 145 #define SEP6200_VIC_RAW_FIQ_STS_L (SEP6200_VIC_BASE + 0x040) 146 #define SEP6200_VIC_RAW_FIQ_STS_H (SEP6200_VIC_BASE + 0x044) 147 #define SEP6200_VIC_MSK_IRQ_STS_L (SEP6200_VIC_BASE + 0x048) 148 #define SEP6200_VIC_MSK_IRQ_STS_H (SEP6200_VIC_BASE + 0x04C) 149 #define SEP6200_VIC_MSK_FIQ_STS_L (SEP6200_VIC_BASE + 0x050) 150 #define SEP6200_VIC_MSK_FIQ_STS_H (SEP6200_VIC_BASE + 0x054) 151 #define SEP6200_VIC_IRQ_PENDING_L (SEP6200_VIC_BASE + 0x058) 152 #define SEP6200_VIC_IRQ_PENDING_H (SEP6200_VIC_BASE + 0x05C) 153 #define SEP6200_VIC_FIQ_PENDING_L (SEP6200_VIC_BASE + 0x060) 154 #define SEP6200_VIC_FIQ_PENDING_H (SEP6200_VIC_BASE + 0x064) 155 #define SEP6200_VIC_IRQ_VECTOR_BASE (SEP6200_VIC_BASE + 0x070) 156 #define SEP6200_VIC_FIQ_VECTOR_BASE (SEP6200_VIC_BASE + 0x074) 157 #define SEP6200_VIC_IRQ_VECTOR_NUM (SEP6200_VIC_BASE + 0x078) 158 #define SEP6200_VIC_FIQ_VECTOR_NUM (SEP6200_VIC_BASE + 0x07C) 159 #define SEP6200_VIC_IRQ_VECTOR_ADDR (SEP6200_VIC_BASE + 0x080) 160 #define SEP6200_VIC_FIQ_VECTOR_ADDR (SEP6200_VIC_BASE + 0x084) 161 #define SEP6200_VIC_PROIRTY_MASK (SEP6200_VIC_BASE + 0x090) 162 #define SEP6200_VIC_VECTOR_PROIRTY00 (SEP6200_VIC_BASE + 0x100) 163 #define SEP6200_VIC_VECTOR_PROIRTY01 (SEP6200_VIC_BASE + 0x104) 164 #define SEP6200_VIC_VECTOR_PROIRTY02 (SEP6200_VIC_BASE + 0x108) 165 #define SEP6200_VIC_VECTOR_PROIRTY03 (SEP6200_VIC_BASE + 0x10C) 166 #define SEP6200_VIC_VECTOR_PROIRTY04 (SEP6200_VIC_BASE + 0x110) 167 #define SEP6200_VIC_VECTOR_PROIRTY05 (SEP6200_VIC_BASE + 0x114) 168 #define SEP6200_VIC_VECTOR_PROIRTY06 (SEP6200_VIC_BASE + 0x118) 169 #define SEP6200_VIC_VECTOR_PROIRTY07 (SEP6200_VIC_BASE + 0x11C) 170 #define SEP6200_VIC_VECTOR_PROIRTY08 (SEP6200_VIC_BASE + 0x120) 171 #define SEP6200_VIC_VECTOR_PROIRTY09 (SEP6200_VIC_BASE + 0x124) 172 #define SEP6200_VIC_VECTOR_PROIRTY10 (SEP6200_VIC_BASE + 0x128) 173 #define SEP6200_VIC_VECTOR_PROIRTY11 (SEP6200_VIC_BASE + 0x12C) 174 #define SEP6200_VIC_VECTOR_PROIRTY12 (SEP6200_VIC_BASE + 0x130) 175 #define SEP6200_VIC_VECTOR_PROIRTY13 (SEP6200_VIC_BASE + 0x134) 176 #define SEP6200_VIC_VECTOR_PROIRTY14 (SEP6200_VIC_BASE + 0x138) 177 #define SEP6200_VIC_VECTOR_PROIRTY15 (SEP6200_VIC_BASE + 0x13C) 178 #define SEP6200_VIC_VECTOR_PROIRTY16 (SEP6200_VIC_BASE + 0x140) 179 #define SEP6200_VIC_VECTOR_PROIRTY17 (SEP6200_VIC_BASE + 0x144) 180 #define SEP6200_VIC_VECTOR_PROIRTY18 (SEP6200_VIC_BASE + 0x148) 181 #define SEP6200_VIC_VECTOR_PROIRTY19 (SEP6200_VIC_BASE + 0x14C) 182 #define SEP6200_VIC_VECTOR_PROIRTY20 (SEP6200_VIC_BASE + 0x150) 183 #define SEP6200_VIC_VECTOR_PROIRTY21 (SEP6200_VIC_BASE + 0x154) 184 #define SEP6200_VIC_VECTOR_PROIRTY22 (SEP6200_VIC_BASE + 0x158) 185 #define SEP6200_VIC_VECTOR_PROIRTY23 (SEP6200_VIC_BASE + 0x15C) 186 #define SEP6200_VIC_VECTOR_PROIRTY24 (SEP6200_VIC_BASE + 0x160) 187 #define SEP6200_VIC_VECTOR_PROIRTY25 (SEP6200_VIC_BASE + 0x164) 188 #define SEP6200_VIC_VECTOR_PROIRTY26 (SEP6200_VIC_BASE + 0x168) 189 #define SEP6200_VIC_VECTOR_PROIRTY27 (SEP6200_VIC_BASE + 0x16C) 190 #define SEP6200_VIC_VECTOR_PROIRTY28 (SEP6200_VIC_BASE + 0x170) 191 #define SEP6200_VIC_VECTOR_PROIRTY29 (SEP6200_VIC_BASE + 0x174) 192 #define SEP6200_VIC_VECTOR_PROIRTY30 (SEP6200_VIC_BASE + 0x178) 193 #define SEP6200_VIC_VECTOR_PROIRTY31 (SEP6200_VIC_BASE + 0x17C) 194 #define SEP6200_VIC_VECTOR_PROIRTY32 (SEP6200_VIC_BASE + 0x180) 195 #define SEP6200_VIC_VECTOR_PROIRTY33 (SEP6200_VIC_BASE + 0x184) 196 #define SEP6200_VIC_VECTOR_PROIRTY34 (SEP6200_VIC_BASE + 0x188) 197 #define SEP6200_VIC_VECTOR_PROIRTY35 (SEP6200_VIC_BASE + 0x18C) 198 #define SEP6200_VIC_VECTOR_PROIRTY36 (SEP6200_VIC_BASE + 0x190) 199 #define SEP6200_VIC_VECTOR_PROIRTY37 (SEP6200_VIC_BASE + 0x194) 200 #define SEP6200_VIC_VECTOR_PROIRTY38 (SEP6200_VIC_BASE + 0x198) 201 #define SEP6200_VIC_VECTOR_PROIRTY39 (SEP6200_VIC_BASE + 0x19C) 202 #define SEP6200_VIC_VECTOR_PROIRTY40 (SEP6200_VIC_BASE + 0x1A0) 203 #define SEP6200_VIC_VECTOR_PROIRTY41 (SEP6200_VIC_BASE + 0x1A4) 204 #define SEP6200_VIC_VECTOR_PROIRTY42 (SEP6200_VIC_BASE + 0x1A8) 205 #define SEP6200_VIC_VECTOR_PROIRTY43 (SEP6200_VIC_BASE + 0x1AC) 206 #define SEP6200_VIC_VECTOR_PROIRTY44 (SEP6200_VIC_BASE + 0x1B0) 207 #define SEP6200_VIC_VECTOR_PROIRTY45 (SEP6200_VIC_BASE + 0x1B4) 208 #define SEP6200_VIC_VECTOR_PROIRTY46 (SEP6200_VIC_BASE + 0x1B8) 209 #define SEP6200_VIC_VECTOR_PROIRTY47 (SEP6200_VIC_BASE + 0x1BC) 210 #define SEP6200_VIC_VECTOR_PROIRTY48 (SEP6200_VIC_BASE + 0x1C0) 211 #define SEP6200_VIC_VECTOR_PROIRTY49 (SEP6200_VIC_BASE + 0x1C4) 212 #define SEP6200_VIC_VECTOR_PROIRTY50 (SEP6200_VIC_BASE + 0x1C8) 213 #define SEP6200_VIC_VECTOR_PROIRTY51 (SEP6200_VIC_BASE + 0x1CC) 214 #define SEP6200_VIC_VECTOR_PROIRTY52 (SEP6200_VIC_BASE + 0x1D0) 215 #define SEP6200_VIC_VECTOR_PROIRTY53 (SEP6200_VIC_BASE + 0x1D4) 216 #define SEP6200_VIC_VECTOR_PROIRTY54 (SEP6200_VIC_BASE + 0x1D8) 217 #define SEP6200_VIC_VECTOR_PROIRTY55 (SEP6200_VIC_BASE + 0x1DC) 218 #define SEP6200_VIC_VECTOR_PROIRTY56 (SEP6200_VIC_BASE + 0x1E0) 219 #define SEP6200_VIC_VECTOR_PROIRTY57 (SEP6200_VIC_BASE + 0x1E4) 220 #define SEP6200_VIC_VECTOR_PROIRTY58 (SEP6200_VIC_BASE + 0x1E8) 221 #define SEP6200_VIC_VECTOR_PROIRTY59 (SEP6200_VIC_BASE + 0x1EC) 222 #define SEP6200_VIC_VECTOR_PROIRTY60 (SEP6200_VIC_BASE + 0x1F0) 223 #define SEP6200_VIC_VECTOR_PROIRTY61 (SEP6200_VIC_BASE + 0x1F4) 224 #define SEP6200_VIC_VECTOR_PROIRTY62 (SEP6200_VIC_BASE + 0x1F8) 225 #define SEP6200_VIC_VECTOR_PROIRTY63 (SEP6200_VIC_BASE + 0x1FC) 226 227 #define SEP6200_PMU_PLL_SET (SEP6200_PMU_BASE + 0x000) 228 #define SEP6200_PMU_APLL_CFG (SEP6200_PMU_BASE + 0x004) 229 #define SEP6200_PMU_MPLL_GFG (SEP6200_PMU_BASE + 0x008) 230 #define SEP6200_PMU_DPLL_CFG (SEP6200_PMU_BASE + 0x00C) 231 #define SEP6200_PMU_PMDR (SEP6200_PMU_BASE + 0x010) 232 #define SEP6200_PMU_CLK_GT_CFG1 (SEP6200_PMU_BASE + 0x014) 233 #define SEP6200_PMU_CLK_GT_CFG2 (SEP6200_PMU_BASE + 0x018) 234 #define SEP6200_PMU_PWR_GT_CFG (SEP6200_PMU_BASE + 0x01C) 235 #define SEP6200_PMU_AHB_CLK_CFG (SEP6200_PMU_BASE + 0x020) 236 #define SEP6200_PMU_ARM_CLK_CFG (SEP6200_PMU_BASE + 0x024) 237 #define SEP6200_PMU_DDR_CLK_CFG (SEP6200_PMU_BASE + 0x028) 238 #define SEP6200_PMU_PIX_CLK_CFG (SEP6200_PMU_BASE + 0x02C) 239 #define SEP6200_PMU_GPU_CLK2X_CFG (SEP6200_PMU_BASE + 0x030) 240 #define SEP6200_PMU_DIV_SET (SEP6200_PMU_BASE + 0x034) 241 #define SEP6200_PMU_CRYSTAL_CFG (SEP6200_PMU_BASE + 0x038) 242 #define SEP6200_PMU_MSK_WAKEUP (SEP6200_PMU_BASE + 0x03C) 243 #define SEP6200_PMU_RTCR (SEP6200_PMU_BASE + 0x040) 244 #define SEP6200_PMU_CLR_WAKEUP (SEP6200_PMU_BASE + 0x044) 245 #define SEP6200_PMU_WAKEUP_TIME (SEP6200_PMU_BASE + 0x048) 246 #define SEP6200_PMU_SLEEP_FLAG (SEP6200_PMU_BASE + 0x04C) 247 #define SEP6200_PMU_WAIT_PWR_SWITCH (SEP6200_PMU_BASE + 0x050) 248 #define SEP6200_PMU_PWR_STATE (SEP6200_PMU_BASE + 0x054) 249 #define SEP6200_PMU_INT_POL_SEL (SEP6200_PMU_BASE + 0x058) 250 #define SEP6200_PMU_PLLLD (SEP6200_PMU_BASE + 0x05C) 251 #define SEP6200_PMU_IC_ENABLE (SEP6200_PMU_BASE + 0x060) 252 #define SEP6200_PMU_IC_TAR (SEP6200_PMU_BASE + 0x064) 253 #define SEP6200_PMU_IC_SCL_LCNT (SEP6200_PMU_BASE + 0x068) 254 #define SEP6200_PMU_IC_SCL_HCNT (SEP6200_PMU_BASE + 0x06C) 255 #define SEP6200_PMU_IC_DATA_CMD (SEP6200_PMU_BASE + 0x070) 256 #define SEP6200_PMU_IC_STATE (SEP6200_PMU_BASE + 0x074) 257 #define SEP6200_PMU_IC_SET (SEP6200_PMU_BASE + 0x078) 258 #define SEP6200_PMU_HA_PWR_OFF_DAT (SEP6200_PMU_BASE + 0x07C) 259 #define SEP6200_PMU_HA_PWR_ON_DAT (SEP6200_PMU_BASE + 0x080) 260 #define SEP6200_PMU_HA_PWR_OFF_DAT_CNT (SEP6200_PMU_BASE + 0x084) 261 #define SEP6200_PMU_HA_PWR_ON_DAT_CNT (SEP6200_PMU_BASE + 0x088) 262 #define SEP6200_PMU_PWR_OFF_TIME (SEP6200_PMU_BASE + 0x08C) 263 #define SEP6200_PMU_PWR_ON_TIME (SEP6200_PMU_BASE + 0x090) 264 #define SEP6200_PMU_PWR_ON_POL_SEL (SEP6200_PMU_BASE + 0x094) 265 #define SEP6200_PMU_RETURN_ADDR (SEP6200_PMU_BASE + 0x098) 266 #define SEP6200_PMU_INT (SEP6200_PMU_BASE + 0x09C) 267 268 /* define the interrupt source number */ 269 #define INTSRC_RESERVE2 63 270 #define INTSRC_RESERVE1 62 271 #define INTSRC_LCDC 61 272 #define INTSRC_GPU 60 273 #define INTSRC_VPU 59 274 #define INTSRC_TIMER3 58 275 #define INTSRC_TIMER2 57 276 #define INTSRC_TIMER1 56 277 #define INTSRC_NAND 55 278 #define INTSRC_I2S 54 279 #define INTSRC_I2C3 53 280 #define INTSRC_I2C2 52 281 #define INTSRC_I2C1 51 282 #define INTSRC_SSI3 50 283 #define INTSRC_SSI2 49 284 #define INTSRC_SSI1 48 285 #define INTSRC_SDIO2 47 286 #define INTSRC_SDIO1 46 287 #define INTSRC_UART3 45 288 #define INTSRC_UART2 44 289 #define INTSRC_UART1 43 290 #define INTSRC_UART0 42 291 #define INTSRC_PWM 41 292 #define INTSRC_USB 40 293 #define INTSRC_USBDMA 39 294 #define INTSRC_DMAC2 38 295 #define INTSRC_DMAC1 37 296 #define INTSRC_PMUIRQ_A11 36 297 #define INTSRC_DMAIRQ_A11 35 298 #define INTSRC_GPS 34 299 #define INTSRC_RTC 33 300 #define INTSRC_RESERVED16 32 301 #define INTSRC_PORTE12 31 302 #define INTSRC_PORTE11 30 303 #define INTSRC_PORTE10 29 304 #define INTSRC_PORTE9 28 305 #define INTSRC_PORTE5 27 306 #define INTSRC_PORTE4 26 307 #define INTSRC_PORTD9 25 308 #define INTSRC_PORTD8 24 309 #define INTSRC_PORTD3 23 310 #define INTSRC_PORTD2 22 311 #define INTSRC_PORTD1 21 312 #define INTSRC_PORTD0 20 313 #define INTSRC_PORTC3 19 314 #define INTSRC_PORTC2 18 315 #define INTSRC_PORTC1 17 316 #define INTSRC_PORTC0 16 317 #define INTSRC_EXT15 15 318 #define INTSRC_EXT14 14 319 #define INTSRC_EXT13 13 320 #define INTSRC_EXT12 12 321 #define INTSRC_EXT11 11 322 #define INTSRC_EXT10 10 323 #define INTSRC_EXT9 9 324 #define INTSRC_EXT8 8 325 #define INTSRC_EXT7 7 326 #define INTSRC_EXT6 6 327 #define INTSRC_EXT5 5 328 #define INTSRC_EXT4 4 329 #define INTSRC_AO_EXT3 3 330 #define INTSRC_AO_EXT2 2 331 #define INTSRC_AO_EXT1 1 332 #define INTSRC_AO_EXT0 0 333 334 335 typedef char S8; /* signed 8-bit integer */ 336 typedef short S16; /* signed 16-bit integer */ 337 typedef long S32; /* signed 32-bit integer */ 338 typedef unsigned char U8; /* unsigned 8-bit integer */ 339 typedef unsigned short U16; /* unsigned 16-bit integer */ 340 typedef unsigned long U32; /* unsigned 32-bit integer */ 341 342 typedef volatile U32 * RP; 343 typedef volatile U16 * RP16; 344 typedef volatile U8 * RP8; 345 346 typedef void *VP; /* pointer to an unpredictable data type */ 347 typedef void (*FP)(); /* program start address */ 348 349 #ifndef _BOOL_TYPE_ 350 #define _BOOL_TYPE_ 351 typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ 352 #endif 353 354 typedef int ER; /* Error code. A signed integer. */ 355 356 /** 357 * IO definitions 358 * 359 * define access restrictions to peripheral registers 360 */ 361 362 #define __I volatile const /*!< defines 'read only' permissions */ 363 #define __O volatile /*!< defines 'write only' permissions */ 364 #define __IO volatile /*!< defines 'read / write' permissions */ 365 #define __iomem volatile 366 367 368 /*Macros for debug*/ 369 370 #define EOUT(fmt,...) \ 371 do \ 372 { \ 373 rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ 374 rt_kprintf(fmt,##__VA_ARGS__); \ 375 }while(0) 376 377 #define RT_USING_DEBUG 378 #ifdef RT_USING_DEBUG 379 #define DBOUT(fmt,...) \ 380 do \ 381 { \ 382 rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ 383 rt_kprintf(fmt,##__VA_ARGS__); \ 384 }while(0) 385 #else 386 #define DBOUT(fmt,...) \ 387 do{}while(0) 388 #endif 389 390 #ifdef RT_USING_DEBUG 391 #define ASSERT(arg) \ 392 if((arg) == 0) \ 393 { \ 394 while(1) \ 395 { \ 396 rt_kprintf("have a assert failure\n"); \ 397 } \ 398 } 399 #else 400 #define ASSERT(arg) \ 401 do \ 402 { \ 403 }while(0) 404 #endif 405 406 407 #define write_reg(reg,value) \ 408 do \ 409 { \ 410 *(RP)(reg) = value; \ 411 }while(0) 412 413 #define read_reg(reg) (*(RP)reg) 414 415 416 struct rt_hw_register 417 { 418 rt_uint32_t r0; 419 rt_uint32_t r1; 420 rt_uint32_t r2; 421 rt_uint32_t r3; 422 rt_uint32_t r4; 423 rt_uint32_t r5; 424 rt_uint32_t r6; 425 rt_uint32_t r7; 426 rt_uint32_t r8; 427 rt_uint32_t r9; 428 rt_uint32_t r10; 429 rt_uint32_t r11; 430 rt_uint32_t r12; 431 rt_uint32_t r13; 432 rt_uint32_t r14; 433 rt_uint32_t r15; 434 rt_uint32_t r16; 435 rt_uint32_t r17; 436 rt_uint32_t r18; 437 rt_uint32_t r19; 438 rt_uint32_t r20; 439 rt_uint32_t r21; 440 rt_uint32_t r22; 441 rt_uint32_t r23; 442 rt_uint32_t r24; 443 rt_uint32_t sb; 444 rt_uint32_t sl; 445 rt_uint32_t fp; 446 rt_uint32_t ip; 447 rt_uint32_t sp; 448 rt_uint32_t lr; 449 rt_uint32_t pc; 450 rt_uint32_t asr; 451 rt_uint32_t bsr; 452 rt_uint32_t ORIG_r0; 453 }; 454 455 /*@}*/ 456 457 #endif 458