| /libcpu/risc-v/common/ |
| A D | riscv-ops.h | 16 #define read_csr(reg) ({ unsigned long __tmp; \ argument
20 #define write_csr(reg, val) ({ \ argument
26 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
33 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
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| /libcpu/arm/zynqmp-r5/ |
| A D | xpseudo_asm_gcc.h | 211 #define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) argument
212 #define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) argument
214 #define mtcpicall(reg) __asm__ __volatile__("ic " #reg) argument
215 #define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) argument
216 #define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) argument
218 #define mfcp(reg) ({u64 rval = 0U;\ argument
223 #define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) argument
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| A D | gic.c | 197 unsigned int reg; in arm_gic_trigger() local
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| /libcpu/arm/s3c44b0/ |
| A D | cpu.c | 25 rt_base_t reg; in rt_hw_cpu_icache_enable() local
56 rt_base_t reg; in rt_hw_cpu_icache_disable() local
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| /libcpu/ppc/ppc405/include/asm/ |
| A D | ppc4xx.h | 78 #define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) argument
79 #define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) argument
81 #define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) argument
82 #define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) argument
84 #define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) argument
85 #define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) argument
87 #define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) argument
88 #define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) argument
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| /libcpu/arm/cortex-a/ |
| A D | pmu.h | 71 unsigned long reg; in rt_hw_pmu_get_ceid() local
132 unsigned long reg; in rt_hw_pmu_read_counter() local
142 unsigned long reg; in rt_hw_pmu_get_ovsr() local
148 rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) in rt_hw_pmu_clear_ovsr()
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| A D | pmu.c | 18 unsigned long reg; in rt_hw_pmu_dump_feature() local
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| A D | backtrace.c | 211 unsigned long **vsp, unsigned int reg) in unwind_pop_register()
226 int load_sp, reg = 4; in unwind_exec_pop_subset_r4_to_r13() local
247 int reg; in unwind_exec_pop_r4_to_rN() local
267 int reg = 0; in unwind_exec_pop_subset_r0_to_r3() local
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| /libcpu/arm/realview-a8-vmm/ |
| A D | pmu.h | 71 unsigned long reg; in rt_hw_pmu_get_ceid() local
132 unsigned long reg; in rt_hw_pmu_read_counter() local
142 unsigned long reg; in rt_hw_pmu_get_ovsr() local
148 rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) in rt_hw_pmu_clear_ovsr()
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| A D | pmu.c | 14 unsigned long reg; in rt_hw_pmu_dump_feature() local
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| A D | gic.c | 291 unsigned int reg; in arm_gic_trigger() local
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| /libcpu/arm/cortex-r52/ |
| A D | backtrace.c | 212 unsigned long **vsp, unsigned int reg) in unwind_pop_register()
227 int load_sp, reg = 4; in unwind_exec_pop_subset_r4_to_r13() local
248 int reg; in unwind_exec_pop_r4_to_rN() local
268 int reg = 0; in unwind_exec_pop_subset_r0_to_r3() local
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| /libcpu/xilinx/microblaze/ |
| A D | trap.c | 137 volatile u32 reg; /* used as bit bucket */ in rt_hw_trap_irq() local
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| /libcpu/mips/common/ |
| A D | exception.c | 105 int reg = 4 * i + j; in mips_dump_regs() local
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| A D | mips_regs.h | 750 #define __read_ulong_c0_register(reg, sel) \ argument
755 #define __write_ulong_c0_register(reg, sel, val) \ argument
1136 #define readb(reg) (*((volatile unsigned char *) (reg))) argument
1137 #define readw(reg) (*((volatile unsigned short *) (reg))) argument
1138 #define readl(reg) (*((volatile unsigned int *) (reg))) argument
1140 #define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data)) argument
1141 #define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) argument
1142 #define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data)) argument
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| /libcpu/risc-v/t-head/c906/ |
| A D | plic.c | 143 … uint32_t *reg = (uint32_t *)((rt_size_t)handler->enable_base + (hwirq / 32) * sizeof(uint32_t)); in plic_toggle() local
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| /libcpu/risc-v/t-head/c908/ |
| A D | plic.c | 143 … uint32_t *reg = (uint32_t *)((rt_size_t)handler->enable_base + (hwirq / 32) * sizeof(uint32_t)); in plic_toggle() local
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| /libcpu/aarch64/common/include/ |
| A D | gicv3.h | 28 #define GET_GICV3_REG(reg, out) __asm__ volatile ("mrs %0, " reg:"=r"(out)::"memory"); argument
29 #define SET_GICV3_REG(reg, in) __asm__ volatile ("msr " reg ", %0"::"r"(in):"memory"); argument
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| /libcpu/risc-v/common64/ |
| A D | encoding.h | 203 #define read_csr(reg) ({ unsigned long __tmp; \ argument
207 #define write_csr(reg, val) ({ \ argument
213 #define swap_csr(reg, val) ({ unsigned long __tmp; \ argument
220 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
227 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
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| /libcpu/risc-v/rv64/ |
| A D | encoding.h | 186 #define read_csr(reg) ({ unsigned long __tmp; \ argument
190 #define write_csr(reg, val) ({ \ argument
196 #define swap_csr(reg, val) ({ unsigned long __tmp; \ argument
203 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
210 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
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| /libcpu/unicore32/sep6200/ |
| A D | sep6200.h | 407 #define write_reg(reg,value) \ argument
413 #define read_reg(reg) (*(RP)reg) argument
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| /libcpu/arm/sep4020/ |
| A D | sep4020.h | 841 #define write_reg(reg,value) \ argument
847 #define read_reg(reg) (*(RP)reg) argument
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