1 /** 2 ****************************************************************************** 3 * @file bl628_sflah.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL628_SFLAH_H__ 37 #define __BL628_SFLAH_H__ 38 39 #include "bflb_sf_ctrl.h" 40 41 /** @addtogroup BL628_Peripheral_Driver 42 * @{ 43 */ 44 45 /** @addtogroup SFLAH 46 * @{ 47 */ 48 49 /** @defgroup SFLAH_Public_Types 50 * @{ 51 */ 52 53 /** 54 * @brief Serial flash configuration structure type definition 55 */ 56 typedef struct 57 { 58 uint8_t io_mode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */ 59 uint8_t c_read_support; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ 60 uint8_t clk_delay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ 61 uint8_t clk_invert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ 62 uint8_t reset_en_cmd; /*!< Flash enable reset command */ 63 uint8_t reset_cmd; /*!< Flash reset command */ 64 uint8_t reset_c_read_cmd; /*!< Flash reset continuous read command */ 65 uint8_t reset_c_read_cmd_size; /*!< Flash reset continuous read command size */ 66 uint8_t jedec_id_cmd; /*!< JEDEC ID command */ 67 uint8_t jedec_id_cmd_dmy_clk; /*!< JEDEC ID command dummy clock */ 68 #if defined(BL702L) || defined(BL702) || defined(BL602) 69 uint8_t qpi_jedec_id_cmd; /*!< QPI JEDEC ID comamnd */ 70 uint8_t qpi_jedec_id_cmd_dmy_clk; /*!< QPI JEDEC ID command dummy clock */ 71 #else 72 uint8_t enter_32bits_addr_cmd; /*!< Enter 32-bits addr command */ 73 uint8_t exit_32bits_addr_cmd; /*!< Exit 32-bits addr command */ 74 #endif 75 uint8_t sector_size; /*!< *1024bytes */ 76 uint8_t mid; /*!< Manufacturer ID */ 77 uint16_t page_size; /*!< Page size */ 78 uint8_t chip_erase_cmd; /*!< Chip erase cmd */ 79 uint8_t sector_erase_cmd; /*!< Sector erase command */ 80 uint8_t blk32_erase_cmd; /*!< Block 32K erase command,some Micron not support */ 81 uint8_t blk64_erase_cmd; /*!< Block 64K erase command */ 82 uint8_t write_enable_cmd; /*!< Need before every erase or program */ 83 uint8_t page_program_cmd; /*!< Page program cmd */ 84 uint8_t qpage_program_cmd; /*!< QIO page program cmd */ 85 uint8_t qpp_addr_mode; /*!< QIO page program address mode */ 86 uint8_t fast_read_cmd; /*!< Fast read command */ 87 uint8_t fr_dmy_clk; /*!< Fast read command dummy clock */ 88 uint8_t qpi_fast_read_cmd; /*!< QPI fast read command */ 89 uint8_t qpi_fr_dmy_clk; /*!< QPI fast read command dummy clock */ 90 uint8_t fast_read_do_cmd; /*!< Fast read dual output command */ 91 uint8_t fr_do_dmy_clk; /*!< Fast read dual output command dummy clock */ 92 uint8_t fast_read_dio_cmd; /*!< Fast read dual io comamnd */ 93 uint8_t fr_dio_dmy_clk; /*!< Fast read dual io command dummy clock */ 94 uint8_t fast_read_qo_cmd; /*!< Fast read quad output comamnd */ 95 uint8_t fr_qo_dmy_clk; /*!< Fast read quad output comamnd dummy clock */ 96 uint8_t fast_read_qio_cmd; /*!< Fast read quad io comamnd */ 97 uint8_t fr_qio_dmy_clk; /*!< Fast read quad io comamnd dummy clock */ 98 uint8_t qpi_fast_read_qio_cmd; /*!< QPI fast read quad io comamnd */ 99 uint8_t qpi_fr_qio_dmy_clk; /*!< QPI fast read QIO dummy clock */ 100 uint8_t qpi_page_program_cmd; /*!< QPI program command */ 101 uint8_t write_vreg_enable_cmd; /*!< Enable write reg */ 102 uint8_t wr_enable_index; /*!< Write enable register index */ 103 uint8_t qe_index; /*!< Quad mode enable register index */ 104 uint8_t busy_index; /*!< Busy status register index */ 105 uint8_t wr_enable_bit; /*!< Write enable bit pos */ 106 uint8_t qe_bit; /*!< Quad enable bit pos */ 107 uint8_t busy_bit; /*!< Busy status bit pos */ 108 uint8_t wr_enable_write_reg_len; /*!< Register length of write enable */ 109 uint8_t wr_enable_read_reg_len; /*!< Register length of write enable status */ 110 uint8_t qe_write_reg_len; /*!< Register length of contain quad enable */ 111 uint8_t qe_read_reg_len; /*!< Register length of contain quad enable status */ 112 uint8_t release_powerdown; /*!< Release power down command */ 113 uint8_t busy_read_reg_len; /*!< Register length of contain busy status */ 114 uint8_t read_reg_cmd[4]; /*!< Read register command buffer */ 115 uint8_t write_reg_cmd[4]; /*!< Write register command buffer */ 116 uint8_t enter_qpi; /*!< Enter qpi command */ 117 uint8_t exit_qpi; /*!< Exit qpi command */ 118 uint8_t c_read_mode; /*!< Config data for continuous read mode */ 119 uint8_t c_rexit; /*!< Config data for exit continuous read mode */ 120 uint8_t burst_wrap_cmd; /*!< Enable burst wrap command */ 121 uint8_t burst_wrap_cmd_dmy_clk; /*!< Enable burst wrap command dummy clock */ 122 uint8_t burst_wrap_data_mode; /*!< Data and address mode for this command */ 123 uint8_t burst_wrap_data; /*!< Data to enable burst wrap */ 124 uint8_t de_burst_wrap_cmd; /*!< Disable burst wrap command */ 125 uint8_t de_burst_wrap_cmd_dmy_clk; /*!< Disable burst wrap command dummy clock */ 126 uint8_t de_burst_wrap_data_mode; /*!< Data and address mode for this command */ 127 uint8_t de_burst_wrap_data; /*!< Data to disable burst wrap */ 128 uint16_t time_e_sector; /*!< 4K erase time */ 129 uint16_t time_e_32k; /*!< 32K erase time */ 130 uint16_t time_e_64k; /*!< 64K erase time */ 131 uint16_t time_page_pgm; /*!< Page program time */ 132 uint16_t time_ce; /*!< Chip erase time in ms */ 133 uint8_t pd_delay; /*!< Release power down command delay time for wake up */ 134 uint8_t qe_data; /*!< QE set data */ 135 } __attribute__((packed)) spi_flash_cfg_type; 136 137 /** 138 * @brief Serial flash security register configuration 139 */ 140 struct sflash_sec_reg_cfg 141 { 142 uint8_t erase_cmd; /*!< Erase security register command */ 143 uint8_t program_cmd; /*!< Program security register command */ 144 uint8_t read_cmd; /*!< Read security register command */ 145 uint8_t enter_sec_opt_cmd; /*!< Enter security register option mode command */ 146 uint8_t exit_sec_opt_cmd; /*!< Exit security register option mode command */ 147 uint8_t block_num; /*!< Security register block number */ 148 uint8_t *data; /*!< Data pointer to be program/read */ 149 uint32_t addr; /*!< Start address to be program/read */ 150 uint32_t len; /*!< Data length to be program/read */ 151 }; 152 /*@} end of group SFLAH_Public_Types */ 153 154 /** @defgroup SFLAH_Public_Constants 155 * @{ 156 */ 157 158 /*@} end of group SFLAH_Public_Constants */ 159 160 /** @defgroup SFLAH_Public_Macros 161 * @{ 162 */ 163 #define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) 164 #define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) 165 #define BFLB_SPIFLASH_CMD_INVALID 0xff 166 167 /*@} end of group SFLAH_Public_Macros */ 168 169 /** @defgroup SFLAH_Public_Functions 170 * @{ 171 */ 172 #ifdef BFLB_SF_CTRL_SBUS2_ENABLE 173 void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg); 174 #else 175 void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg); 176 #endif 177 int bflb_sflash_set_spi_mode(uint8_t mode); 178 int bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len); 179 int bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len); 180 int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, 181 uint8_t reg_len); 182 int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value, 183 uint8_t reg_len); 184 int bflb_sflash_busy(spi_flash_cfg_type *flash_cfg); 185 int bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg); 186 int bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg); 187 int bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg); 188 void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg); 189 int bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg); 190 int bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sector_num); 191 int bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num); 192 int bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num); 193 int bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr); 194 void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len); 195 void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data); 196 void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr); 197 void bflb_sflash_powerdown(void); 198 void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg); 199 int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg, uint8_t flash_cont_read, uint8_t bank); 200 void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg); 201 void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg); 202 #ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE 203 int bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg, uint8_t en_32bits_addr); 204 #endif 205 int bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg); 206 void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg); 207 int bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, 208 uint32_t len, uint8_t bank); 209 int bflb_sflash_xip_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank); 210 void bflb_sflash_xip_read_disable(void); 211 int bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos); 212 int bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg); 213 int bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg); 214 int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg); 215 int bflb_sflash_clear_status_register(spi_flash_cfg_type *flash_cfg); 216 int bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data, 217 uint32_t len); 218 int bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len); 219 220 /*@} end of group SFLAH_Public_Functions */ 221 222 /*@} end of group SFLAH */ 223 224 /*@} end of group BL628_Peripheral_Driver */ 225 226 #endif /* __BL628_SFLAH_H__ */ 227