1 /** 2 ****************************************************************************** 3 * @file bflb_spi_psram.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BFLB_SPI_PSRAM_H__ 37 #define __BFLB_SPI_PSRAM_H__ 38 39 #include "sf_ctrl_reg.h" 40 #include "bflb_common.h" 41 #include "bflb_sf_ctrl.h" 42 43 /** @addtogroup BFLB_Peripheral_Driver 44 * @{ 45 */ 46 47 /** @addtogroup PSRAM 48 * @{ 49 */ 50 51 /** @defgroup PSRAM_Public_Types 52 * @{ 53 */ 54 55 /** 56 * @brief Psram drive strength type definition 57 */ 58 59 #define PSRAM_DRIVE_STRENGTH_50_OHMS 0 /*!< Drive strength 50 ohms(default) */ 60 #define PSRAM_DRIVE_STRENGTH_100_OHMS 1 /*!< Drive strength 100 ohms */ 61 #define PSRAM_DRIVE_STRENGTH_200_OHMS 2 /*!< Drive strength 200 ohms */ 62 63 /** 64 * @brief Psram burst length size type definition 65 */ 66 #define PSRAM_BURST_LENGTH_16_BYTES 0 /*!< Burst Length 16 bytes */ 67 #define PSRAM_BURST_LENGTH_32_BYTES 1 /*!< Burst Length 32 bytes */ 68 #define PSRAM_BURST_LENGTH_64_BYTES 2 /*!< Burst Length 64 bytes */ 69 #define PSRAM_BURST_LENGTH_512_BYTES 3 /*!< Burst Length 512 bytes(default) */ 70 71 /** 72 * @brief Psram ctrl mode type definition 73 */ 74 #define PSRAM_SPI_CTRL_MODE 0 /*!< Psram SPI ctrl mode */ 75 #define PSRAM_QPI_CTRL_MODE 1 /*!< Psram QPI ctrl mode */ 76 77 /** 78 * @brief Psram ctrl configuration structure type definition 79 */ 80 struct spi_psram_cfg_type { 81 uint8_t read_id_cmd; /*!< Read ID command */ 82 uint8_t read_id_dmy_clk; /*!< Read ID command dummy clock */ 83 uint8_t burst_toggle_cmd; /*!< Burst toggle length command */ 84 uint8_t reset_enable_cmd; /*!< Psram reset enable command */ 85 uint8_t reset_cmd; /*!< Psram reset command */ 86 uint8_t enter_quad_mode_cmd; /*!< Psram enter quad mode command */ 87 uint8_t exit_quad_mode_cmd; /*!< Psram exit quad mode command */ 88 uint8_t read_reg_cmd; /*!< Read register command */ 89 uint8_t read_reg_dmy_clk; /*!< Read register command dummy clock */ 90 uint8_t write_reg_cmd; /*!< Write register command */ 91 uint8_t read_cmd; /*!< Psram read command */ 92 uint8_t read_dmy_clk; /*!< Psram read command dummy clock */ 93 uint8_t f_read_cmd; /*!< Psram fast read command */ 94 uint8_t f_read_dmy_clk; /*!< Psram fast read command dummy clock */ 95 uint8_t f_read_quad_cmd; /*!< Psram fast read quad command */ 96 uint8_t f_read_quad_dmy_clk; /*!< Psram fast read quad command dummy clock */ 97 uint8_t write_cmd; /*!< Psram write command */ 98 uint8_t quad_write_cmd; /*!< Psram quad write command */ 99 uint16_t page_size; /*!< Psram page size */ 100 #if defined(BL702L) 101 uint8_t burst_toggle_en; /*!< Psram burst toggle mode enable */ 102 #endif 103 uint8_t ctrl_mode; /*!< Psram ctrl mode */ 104 uint8_t drive_strength; /*!< Psram drive strength */ 105 uint8_t burst_length; /*!< Psram burst length size */ 106 }; 107 108 /*@} end of group PSRAM_Public_Types */ 109 110 /** @defgroup PSRAM_Public_Constants 111 * @{ 112 */ 113 114 /*@} end of group PSRAM_Public_Constants */ 115 116 /** @defgroup PSRAM_Public_Macros 117 * @{ 118 */ 119 120 /*@} end of group PSRAM_Public_Macros */ 121 122 /** @defgroup PSRAM_Public_Functions 123 * @{ 124 */ 125 126 /** 127 * @brief PSRAM Functions 128 */ 129 void bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg, 130 struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg); 131 void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value); 132 void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value); 133 int bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg); 134 int bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg); 135 void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data); 136 int bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg); 137 int bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg); 138 int bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode); 139 int bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode); 140 int bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint32_t len); 141 int bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint8_t wt_en, 142 uint8_t wb_en, uint8_t wa_en); 143 int bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len); 144 int bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len); 145 146 /*@} end of group PSRAM_Public_Functions */ 147 148 /*@} end of group PSRAM */ 149 150 /*@} end of group BFLB_Peripheral_Driver */ 151 152 #endif /* __BFLB_SPI_PSRAM_H__ */ 153