1 /*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-10-24 GuEe-GUI first version
9 */
10
11 #include <drivers/pci.h>
12
rt_pci_msi_init(struct rt_pci_device * pdev)13 void rt_pci_msi_init(struct rt_pci_device *pdev)
14 {
15 if (pdev && (pdev->msi_cap = rt_pci_find_capability(pdev, PCIY_MSI)))
16 {
17 rt_uint16_t ctrl;
18
19 rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &ctrl);
20
21 if (ctrl & PCIM_MSICTRL_MSI_ENABLE)
22 {
23 rt_pci_write_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, ctrl & ~PCIM_MSICTRL_MSI_ENABLE);
24 }
25
26 if (!(ctrl & PCIM_MSICTRL_64BIT))
27 {
28 pdev->no_64bit_msi = RT_TRUE;
29 }
30 }
31 }
32
rt_pci_msix_init(struct rt_pci_device * pdev)33 void rt_pci_msix_init(struct rt_pci_device *pdev)
34 {
35 if (pdev && (pdev->msix_cap = rt_pci_find_capability(pdev, PCIY_MSIX)))
36 {
37 rt_uint16_t ctrl;
38
39 rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &ctrl);
40
41 if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE)
42 {
43 rt_pci_write_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE);
44 }
45 }
46 }
47