1 /*
2 * Copyright (c) 2006-2024 RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-11-16 GuEe-GUI first version
9 */
10
11 #include "8250.h"
12
serial8250_config(struct serial8250 * serial,const char * options)13 rt_err_t serial8250_config(struct serial8250 *serial, const char *options)
14 {
15 rt_err_t ret = -RT_EINVAL;
16
17 if (serial)
18 {
19 char *arg;
20 rt_bool_t has_iotype = RT_FALSE;
21
22 /*
23 * uart8250,io,<addr>[,options]
24 * uart8250,mmio,<addr>[,options]
25 * uart8250,mmio16,<addr>[,options]
26 * uart8250,mmio32,<addr>[,options]
27 * uart8250,mmio32be,<addr>[,options]
28 * uart8250,0x<addr>[,options]
29 */
30 serial_for_each_args(arg, options)
31 {
32 if (!rt_strcmp(arg, "uart8250"))
33 {
34 ret = RT_EOK;
35 continue;
36 }
37 /* user call error */
38 if (ret)
39 {
40 break;
41 }
42 if (!rt_strncmp(arg, "0x", 2))
43 {
44 serial->base = serial_base_from_args(arg);
45 continue;
46 }
47 if (!has_iotype)
48 {
49 const struct
50 {
51 char *param;
52 int type;
53 } iotype_table[] =
54 {
55 { "io", PORT_IO },
56 { "mmio", PORT_MMIO },
57 { "mmio16", PORT_MMIO16 },
58 { "mmio32", PORT_MMIO32 },
59 { "mmio32be", PORT_MMIO32BE },
60 };
61
62 serial->iotype = PORT_MMIO32;
63
64 for (int i = 0; i < RT_ARRAY_SIZE(iotype_table); ++i)
65 {
66 if (!rt_strcmp(arg, iotype_table[i].param))
67 {
68 serial->iotype = iotype_table[i].type;
69 break;
70 }
71 }
72
73 has_iotype = RT_TRUE;
74 continue;
75 }
76
77 serial->parent.config = serial_cfg_from_args(arg);
78 }
79
80 if (!serial->size)
81 {
82 serial->size = 0x1000;
83 }
84 }
85
86 return ret;
87 }
88
serial8250_isr(int irqno,void * param)89 static void serial8250_isr(int irqno, void *param)
90 {
91 struct serial8250 *serial = (struct serial8250 *)param;
92
93 if (serial->handle_irq)
94 {
95 serial->handle_irq(serial, irqno);
96 }
97 else
98 {
99 rt_hw_serial_isr(&serial->parent, RT_SERIAL_EVENT_RX_IND);
100 }
101 }
102
serial8250_setup(struct serial8250 * serial)103 rt_err_t serial8250_setup(struct serial8250 *serial)
104 {
105 rt_err_t ret = RT_EOK;
106 const char *uart_name;
107 char dev_name[RT_NAME_MAX];
108
109 if (serial)
110 {
111 rt_spin_lock_init(&serial->spinlock);
112
113 serial->serial_in = serial->serial_in ? : &serial8250_in;
114 serial->serial_out = serial->serial_out ? : &serial8250_out;
115
116 serial_dev_set_name(&serial->parent);
117 uart_name = rt_dm_dev_get_name(&serial->parent.parent);
118
119 rt_hw_serial_register(&serial->parent, uart_name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, serial->data);
120
121 rt_snprintf(dev_name, sizeof(dev_name), "%s-8250", uart_name);
122 rt_pic_attach_irq(serial->irq, serial8250_isr, serial, dev_name, RT_IRQ_F_NONE);
123 }
124 else
125 {
126 ret = -RT_EINVAL;
127 }
128
129 return ret;
130 }
131
serial8250_remove(struct serial8250 * serial)132 rt_err_t serial8250_remove(struct serial8250 *serial)
133 {
134 rt_err_t err;
135
136 rt_iounmap((void *)serial->base);
137 serial->base = RT_NULL;
138
139 rt_pic_irq_mask(serial->irq);
140 rt_pic_detach_irq(serial->irq, serial);
141
142 err = rt_device_unregister(&serial->parent.parent);
143
144 if (!err && serial->remove)
145 {
146 serial->remove(serial);
147 }
148
149 return err;
150 }
151
serial8250_in(struct serial8250 * serial,int offset)152 rt_uint32_t serial8250_in(struct serial8250 *serial, int offset)
153 {
154 rt_uint32_t ret = 0;
155 offset <<= serial->regshift;
156
157 switch (serial->iotype)
158 {
159 case PORT_MMIO:
160 ret = HWREG8(serial->base + offset);
161 break;
162 case PORT_MMIO16:
163 ret = HWREG16(serial->base + offset);
164 break;
165 case PORT_MMIO32:
166 ret = HWREG32(serial->base + offset);
167 break;
168 case PORT_MMIO32BE:
169 ret = rt_cpu_to_be32(HWREG32(serial->base + offset));
170 break;
171 #ifdef ARCH_SUPPORT_PIO
172 case PORT_IO:
173 ret = inb(serial->base + offset, value);
174 break;
175 #endif
176 default:
177 break;
178 }
179
180 return ret;
181 }
182
serial8250_out(struct serial8250 * serial,int offset,int value)183 void serial8250_out(struct serial8250 *serial, int offset, int value)
184 {
185 offset <<= serial->regshift;
186
187 switch (serial->iotype)
188 {
189 case PORT_MMIO:
190 HWREG8(serial->base + offset) = value;
191 break;
192 case PORT_MMIO16:
193 HWREG16(serial->base + offset) = value;
194 break;
195 case PORT_MMIO32:
196 HWREG32(serial->base + offset) = value;
197 break;
198 case PORT_MMIO32BE:
199 HWREG32(serial->base + offset) = rt_cpu_to_be32(value);
200 break;
201 #ifdef ARCH_SUPPORT_PIO
202 case PORT_IO:
203 outb(serial->base + offset, value);
204 break;
205 #endif
206 default:
207 break;
208 }
209 }
210
serial8250_uart_configure(struct rt_serial_device * raw_serial,struct serial_configure * cfg)211 rt_err_t serial8250_uart_configure(struct rt_serial_device *raw_serial, struct serial_configure *cfg)
212 {
213 rt_err_t err = RT_EOK;
214 struct serial8250 *serial = raw_to_serial8250(raw_serial);
215
216 /* Disable interrupt */
217 serial->serial_out(serial, UART_IER, !UART_IER_RDI);
218
219 /* Enable FIFO, Clear FIFO*/
220 serial->serial_out(serial, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
221
222 /* DTR + RTS */
223 serial->serial_out(serial, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
224
225 if (serial->freq)
226 {
227 rt_uint32_t wlen = cfg->data_bits - DATA_BITS_5 + UART_LCR_WLEN5;
228 rt_uint32_t divisor = serial->freq / 16 / cfg->baud_rate;
229
230 /* Enable access DLL & DLH */
231 serial->serial_out(serial, UART_LCR, serial->serial_in(serial, UART_LCR) | UART_LCR_DLAB);
232 serial->serial_out(serial, UART_DLL, (divisor & 0xff));
233 serial->serial_out(serial, UART_DLM, (divisor >> 8) & 0xff);
234 /* Clear DLAB bit */
235 serial->serial_out(serial, UART_LCR, serial->serial_in(serial, UART_LCR) & (~UART_LCR_DLAB));
236
237 serial->serial_out(serial, UART_LCR, (serial->serial_in(serial, UART_LCR) & (~wlen)) | wlen);
238 serial->serial_out(serial, UART_LCR, serial->serial_in(serial, UART_LCR) & (~UART_LCR_STOP));
239 serial->serial_out(serial, UART_LCR, serial->serial_in(serial, UART_LCR) & (~UART_LCR_PARITY));
240 }
241
242 serial->serial_out(serial, UART_IER, UART_IER_RDI);
243
244 return err;
245 }
246
serial8250_uart_control(struct rt_serial_device * raw_serial,int cmd,void * arg)247 rt_err_t serial8250_uart_control(struct rt_serial_device *raw_serial, int cmd, void *arg)
248 {
249 rt_err_t err = RT_EOK;
250 struct serial8250 *serial = raw_to_serial8250(raw_serial);
251
252 switch (cmd)
253 {
254 case RT_DEVICE_CTRL_CLR_INT:
255 /* disable rx irq */
256 serial->serial_out(serial, UART_IER, !UART_IER_RDI);
257 rt_pic_irq_mask(serial->irq);
258 break;
259
260 case RT_DEVICE_CTRL_SET_INT:
261 /* enable rx irq */
262 serial->serial_out(serial, UART_IER, UART_IER_RDI);
263 rt_pic_irq_unmask(serial->irq);
264 break;
265 }
266
267 return err;
268 }
269
serial8250_uart_putc(struct rt_serial_device * raw_serial,char c)270 int serial8250_uart_putc(struct rt_serial_device *raw_serial, char c)
271 {
272 struct serial8250 *serial = raw_to_serial8250(raw_serial);
273
274 while (!(serial->serial_in(serial, UART_LSR) & 0x20))
275 {
276 rt_hw_cpu_relax();
277 }
278
279 serial->serial_out(serial, UART_TX, c);
280
281 return 1;
282 }
283
serial8250_uart_getc(struct rt_serial_device * raw_serial)284 int serial8250_uart_getc(struct rt_serial_device *raw_serial)
285 {
286 int ch = -1;
287 struct serial8250 *serial = raw_to_serial8250(raw_serial);
288
289 if ((serial->serial_in(serial, UART_LSR) & 0x1))
290 {
291 ch = serial->serial_in(serial, UART_RX) & 0xff;
292 }
293
294 return ch;
295 }
296
297 const struct rt_uart_ops serial8250_uart_ops =
298 {
299 .configure = serial8250_uart_configure,
300 .control = serial8250_uart_control,
301 .putc = serial8250_uart_putc,
302 .getc = serial8250_uart_getc,
303 };
304