1 /*
2 * Copyright (c) 2006-2024 RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2024-08-16 zhujiale first version
9 */
10 #ifndef __RT_SDHCI_HW_H
11 #define __RT_SDHCI_HW_H
12
13 #include "sdhci_host.h"
14 #include "sdhci_misc.h"
15 #include "sdhci-platform.h"
16 #include <drivers/mmcsd_cmd.h>
17 #include <drivers/dev_mmcsd_core.h>
18 #include <drivers/mmcsd_host.h>
19 #include <rtdevice.h>
20
21 #define lower_32_bits(n) ((rt_uint32_t)((n) & 0xffffffff))
22 #define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16))
23
24 #define MAX_TUNING_LOOP 40
25 /*
26 * Controller registers
27 */
28 #define RT_SDHCI_DMA_ADDRESS 0x00
29 #define RT_SDHCI_ARGUMENT2 RT_SDHCI_DMA_ADDRESS
30 #define RT_SDHCI_32BIT_BLK_CNT RT_SDHCI_DMA_ADDRESS
31
32 #define RT_SDHCI_BLOCK_SIZE 0x04
33 #define RT_SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
34
35 #define RT_SDHCI_BLOCK_COUNT 0x06
36
37 #define RT_SDHCI_ARGUMENT 0x08
38
39 #define RT_SDHCI_TRANSFER_MODE 0x0C
40 #define RT_SDHCI_TRNS_DMA 0x01
41 #define RT_SDHCI_TRNS_BLK_CNT_EN 0x02
42 #define RT_SDHCI_TRNS_AUTO_CMD12 0x04
43 #define RT_SDHCI_TRNS_AUTO_CMD23 0x08
44 #define RT_SDHCI_TRNS_AUTO_SEL 0x0C
45 #define RT_SDHCI_TRNS_READ 0x10
46 #define RT_SDHCI_TRNS_MULTI 0x20
47
48 #define RT_SDHCI_COMMAND 0x0E
49 #define RT_SDHCI_CMD_RESP_MASK 0x03
50 #define RT_SDHCI_CMD_CRC 0x08
51 #define RT_SDHCI_CMD_INDEX 0x10
52 #define RT_SDHCI_CMD_DATA 0x20
53 #define RT_SDHCI_CMD_ABORTCMD 0xC0
54
55 #define RT_SDHCI_CMD_RESP_NONE 0x00
56 #define RT_SDHCI_CMD_RESP_LONG 0x01
57 #define RT_SDHCI_CMD_RESP_SHORT 0x02
58 #define RT_SDHCI_CMD_RESP_SHORT_BUSY 0x03
59
60 #define RT_SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
61 #define RT_SDHCI_GET_CMD(c) ((c >> 8) & 0x3f)
62
63 #define RT_SDHCI_RESPONSE 0x10
64
65 #define RT_SDHCI_BUFFER 0x20
66
67 #define RT_SDHCI_PRESENT_STATE 0x24
68 #define RT_SDHCI_CMD_INHIBIT 0x00000001
69 #define RT_SDHCI_DATA_INHIBIT 0x00000002
70 #define RT_SDHCI_DOING_WRITE 0x00000100
71 #define RT_SDHCI_DOING_READ 0x00000200
72 #define RT_SDHCI_SPACE_AVAILABLE 0x00000400
73 #define RT_SDHCI_DATA_AVAILABLE 0x00000800
74 #define RT_SDHCI_CARD_PRESENT 0x00010000
75 #define RT_SDHCI_CARD_PRES_SHIFT 16
76 #define RT_SDHCI_CD_STABLE 0x00020000
77 #define RT_SDHCI_CD_LVL 0x00040000
78 #define RT_SDHCI_CD_LVL_SHIFT 18
79 #define RT_SDHCI_WRITE_PROTECT 0x00080000
80 #define RT_SDHCI_DATA_LVL_MASK 0x00F00000
81 #define RT_SDHCI_DATA_LVL_SHIFT 20
82 #define RT_SDHCI_DATA_0_LVL_MASK 0x00100000
83 #define RT_SDHCI_CMD_LVL 0x01000000
84
85 #define RT_SDHCI_HOST_CONTROL 0x28
86 #define RT_SDHCI_CTRL_LED 0x01
87 #define RT_SDHCI_CTRL_4BITBUS 0x02
88 #define RT_SDHCI_CTRL_HISPD 0x04
89 #define RT_SDHCI_CTRL_DMA_MASK 0x18
90 #define RT_SDHCI_CTRL_SDMA 0x00
91 #define RT_SDHCI_CTRL_ADMA1 0x08
92 #define RT_SDHCI_CTRL_ADMA32 0x10
93 #define RT_SDHCI_CTRL_ADMA64 0x18
94 #define RT_SDHCI_CTRL_ADMA3 0x18
95 #define RT_SDHCI_CTRL_8BITBUS 0x20
96 #define RT_SDHCI_CTRL_CDTEST_INS 0x40
97 #define RT_SDHCI_CTRL_CDTEST_EN 0x80
98
99 #define RT_SDHCI_POWER_CONTROL 0x29
100 #define RT_SDHCI_POWER_ON 0x01
101 #define RT_SDHCI_POWER_180 0x0A
102 #define RT_SDHCI_POWER_300 0x0C
103 #define RT_SDHCI_POWER_330 0x0E
104 /*
105 * VDD2 - UHS2 or PCIe/NVMe
106 * VDD2 power on/off and voltage select
107 */
108 #define RT_SDHCI_VDD2_POWER_ON 0x10
109 #define RT_SDHCI_VDD2_POWER_120 0x80
110 #define RT_SDHCI_VDD2_POWER_180 0xA0
111
112 #define RT_SDHCI_BLOCK_GAP_CONTROL 0x2A
113
114 #define RT_SDHCI_WAKE_UP_CONTROL 0x2B
115 #define RT_SDHCI_WAKE_ON_INT 0x01
116 #define RT_SDHCI_WAKE_ON_INSERT 0x02
117 #define RT_SDHCI_WAKE_ON_REMOVE 0x04
118
119 #define RT_SDHCI_CLOCK_CONTROL 0x2C
120 #define RT_SDHCI_DIVIDER_SHIFT 8
121 #define RT_SDHCI_DIVIDER_HI_SHIFT 6
122 #define RT_SDHCI_DIV_MASK 0xFF
123 #define RT_SDHCI_DIV_MASK_LEN 8
124 #define RT_SDHCI_DIV_HI_MASK 0x300
125 #define RT_SDHCI_PROG_CLOCK_MODE 0x0020
126 #define RT_SDHCI_CLOCK_CARD_EN 0x0004
127 #define RT_SDHCI_CLOCK_PLL_EN 0x0008
128 #define RT_SDHCI_CLOCK_INT_STABLE 0x0002
129 #define RT_SDHCI_CLOCK_INT_EN 0x0001
130
131 #define RT_SDHCI_TIMEOUT_CONTROL 0x2E
132
133 #define RT_SDHCI_SOFTWARE_RESET 0x2F
134 #define RT_SDHCI_RESET_ALL 0x01
135 #define RT_SDHCI_RESET_CMD 0x02
136 #define RT_SDHCI_RESET_DATA 0x04
137
138 #define RT_SDHCI_INT_STATUS 0x30
139 #define RT_SDHCI_INT_ENABLE 0x34
140 #define RT_SDHCI_SIGNAL_ENABLE 0x38
141 #define RT_SDHCI_INT_RESPONSE 0x00000001
142 #define RT_SDHCI_INT_DATA_END 0x00000002
143 #define RT_SDHCI_INT_BLK_GAP 0x00000004
144 #define RT_SDHCI_INT_DMA_END 0x00000008
145 #define RT_SDHCI_INT_SPACE_AVAIL 0x00000010
146 #define RT_SDHCI_INT_DATA_AVAIL 0x00000020
147 #define RT_SDHCI_INT_CARD_INSERT 0x00000040
148 #define RT_SDHCI_INT_CARD_REMOVE 0x00000080
149 #define RT_SDHCI_INT_CARD_INT 0x00000100
150 #define RT_SDHCI_INT_RETUNE 0x00001000
151 #define RT_SDHCI_INT_CQE 0x00004000
152 #define RT_SDHCI_INT_ERROR 0x00008000
153 #define RT_SDHCI_INT_TIMEOUT 0x00010000
154 #define RT_SDHCI_INT_CRC 0x00020000
155 #define RT_SDHCI_INT_END_BIT 0x00040000
156 #define RT_SDHCI_INT_INDEX 0x00080000
157 #define RT_SDHCI_INT_DATA_TIMEOUT 0x00100000
158 #define RT_SDHCI_INT_DATA_CRC 0x00200000
159 #define RT_SDHCI_INT_DATA_END_BIT 0x00400000
160 #define RT_SDHCI_INT_BUS_POWER 0x00800000
161 #define RT_SDHCI_INT_AUTO_CMD_ERR 0x01000000
162 #define RT_SDHCI_INT_ADMA_ERROR 0x02000000
163
164 #define RT_SDHCI_INT_NORMAL_MASK 0x00007FFF
165 #define RT_SDHCI_INT_ERROR_MASK 0xFFFF8000
166
167 #define RT_SDHCI_INT_CMD_MASK (RT_SDHCI_INT_RESPONSE | RT_SDHCI_INT_TIMEOUT | RT_SDHCI_INT_CRC | RT_SDHCI_INT_END_BIT | RT_SDHCI_INT_INDEX | RT_SDHCI_INT_AUTO_CMD_ERR)
168 #define RT_SDHCI_INT_DATA_MASK (RT_SDHCI_INT_DATA_END | RT_SDHCI_INT_DMA_END | RT_SDHCI_INT_DATA_AVAIL | RT_SDHCI_INT_SPACE_AVAIL | RT_SDHCI_INT_DATA_TIMEOUT | RT_SDHCI_INT_DATA_CRC | RT_SDHCI_INT_DATA_END_BIT | RT_SDHCI_INT_ADMA_ERROR | RT_SDHCI_INT_BLK_GAP)
169 #define RT_SDHCI_INT_ALL_MASK ((unsigned int)-1)
170
171 #define RT_SDHCI_CQE_INT_ERR_MASK ( \
172 RT_SDHCI_INT_ADMA_ERROR | RT_SDHCI_INT_BUS_POWER | RT_SDHCI_INT_DATA_END_BIT | RT_SDHCI_INT_DATA_CRC | RT_SDHCI_INT_DATA_TIMEOUT | RT_SDHCI_INT_INDEX | RT_SDHCI_INT_END_BIT | RT_SDHCI_INT_CRC | RT_SDHCI_INT_TIMEOUT)
173
174 #define RT_SDHCI_CQE_INT_MASK (RT_SDHCI_CQE_INT_ERR_MASK | RT_SDHCI_INT_CQE)
175
176 #define RT_SDHCI_AUTO_CMD_STATUS 0x3C
177 #define RT_SDHCI_AUTO_CMD_TIMEOUT 0x00000002
178 #define RT_SDHCI_AUTO_CMD_CRC 0x00000004
179 #define RT_SDHCI_AUTO_CMD_END_BIT 0x00000008
180 #define RT_SDHCI_AUTO_CMD_INDEX 0x00000010
181
182 #define RT_SDHCI_HOST_CONTROL2 0x3E
183 #define RT_SDHCI_CTRL_UHS_MASK 0x0007
184 #define RT_SDHCI_CTRL_UHS_SDR12 0x0000
185 #define RT_SDHCI_CTRL_UHS_SDR25 0x0001
186 #define RT_SDHCI_CTRL_UHS_SDR50 0x0002
187 #define RT_SDHCI_CTRL_UHS_SDR104 0x0003
188 #define RT_SDHCI_CTRL_UHS_DDR50 0x0004
189 #define RT_SDHCI_CTRL_HS400 0x0005 /* Non-standard */
190 #define RT_SDHCI_CTRL_VDD_180 0x0008
191 #define RT_SDHCI_CTRL_DRV_TYPE_MASK 0x0030
192 #define RT_SDHCI_CTRL_DRV_TYPE_B 0x0000
193 #define RT_SDHCI_CTRL_DRV_TYPE_A 0x0010
194 #define RT_SDHCI_CTRL_DRV_TYPE_C 0x0020
195 #define RT_SDHCI_CTRL_DRV_TYPE_D 0x0030
196 #define RT_SDHCI_CTRL_EXEC_TUNING 0x0040
197 #define RT_SDHCI_CTRL_TUNED_CLK 0x0080
198 #define RT_SDHCI_CMD23_ENABLE 0x0800
199 #define RT_SDHCI_CTRL_V4_MODE 0x1000
200 #define RT_SDHCI_CTRL_64BIT_ADDR 0x2000
201 #define RT_SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
202
203 #define RT_SDHCI_CAPABILITIES 0x40
204 #define RT_SDHCI_TIMEOUT_CLK_MASK RT_GENMASK(5, 0)
205 #define RT_SDHCI_TIMEOUT_CLK_SHIFT 0
206 #define RT_SDHCI_TIMEOUT_CLK_UNIT 0x00000080
207 #define RT_SDHCI_CLOCK_BASE_MASK RT_GENMASK(13, 8)
208 #define RT_SDHCI_CLOCK_BASE_SHIFT 8
209 #define RT_SDHCI_CLOCK_V3_BASE_MASK RT_GENMASK(15, 8)
210 #define RT_SDHCI_MAX_BLOCK_MASK 0x00030000
211 #define RT_SDHCI_MAX_BLOCK_SHIFT 16
212 #define RT_SDHCI_CAN_DO_8BIT 0x00040000
213 #define RT_SDHCI_CAN_DO_ADMA2 0x00080000
214 #define RT_SDHCI_CAN_DO_ADMA1 0x00100000
215 #define RT_SDHCI_CAN_DO_HISPD 0x00200000
216 #define RT_SDHCI_CAN_DO_SDMA 0x00400000
217 #define RT_SDHCI_CAN_DO_SUSPEND 0x00800000
218 #define RT_SDHCI_CAN_VDD_330 0x01000000
219 #define RT_SDHCI_CAN_VDD_300 0x02000000
220 #define RT_SDHCI_CAN_VDD_180 0x04000000
221 #define RT_SDHCI_CAN_64BIT_V4 0x08000000
222 #define RT_SDHCI_CAN_64BIT 0x10000000
223
224 #define RT_SDHCI_CAPABILITIES_1 0x44
225 #define RT_SDHCI_SUPPORT_SDR50 0x00000001
226 #define RT_SDHCI_SUPPORT_SDR104 0x00000002
227 #define RT_SDHCI_SUPPORT_DDR50 0x00000004
228 #define RT_SDHCI_DRIVER_TYPE_A 0x00000010
229 #define RT_SDHCI_DRIVER_TYPE_C 0x00000020
230 #define RT_SDHCI_DRIVER_TYPE_D 0x00000040
231 #define RT_SDHCI_RETUNING_TIMER_COUNT_MASK RT_GENMASK(11, 8)
232 #define RT_SDHCI_USE_SDR50_TUNING 0x00002000
233 #define RT_SDHCI_RETUNING_MODE_MASK RT_GENMASK(15, 14)
234 #define RT_SDHCI_CLOCK_MUL_MASK RT_GENMASK(23, 16)
235 #define RT_SDHCI_CAN_DO_ADMA3 0x08000000
236 #define RT_SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
237
238 #define RT_SDHCI_MAX_CURRENT 0x48
239 #define RT_SDHCI_MAX_CURRENT_LIMIT RT_GENMASK(7, 0)
240 #define RT_SDHCI_MAX_CURRENT_330_MASK RT_GENMASK(7, 0)
241 #define RT_SDHCI_MAX_CURRENT_300_MASK RT_GENMASK(15, 8)
242 #define RT_SDHCI_MAX_CURRENT_180_MASK RT_GENMASK(23, 16)
243 #define RT_SDHCI_MAX_CURRENT_MULTIPLIER 4
244
245 /* 4C-4F reserved for more max current */
246
247 #define RT_SDHCI_SET_ACMD12_ERROR 0x50
248 #define RT_SDHCI_SET_INT_ERROR 0x52
249
250 #define RT_SDHCI_ADMA_ERROR 0x54
251
252 /* 55-57 reserved */
253
254 #define RT_SDHCI_ADMA_ADDRESS 0x58
255 #define RT_SDHCI_ADMA_ADDRESS_HI 0x5C
256
257 /* 60-FB reserved */
258
259 #define RT_SDHCI_PRESET_FOR_HIGH_SPEED 0x64
260 #define RT_SDHCI_PRESET_FOR_SDR12 0x66
261 #define RT_SDHCI_PRESET_FOR_SDR25 0x68
262 #define RT_SDHCI_PRESET_FOR_SDR50 0x6A
263 #define RT_SDHCI_PRESET_FOR_SDR104 0x6C
264 #define RT_SDHCI_PRESET_FOR_DDR50 0x6E
265 #define RT_SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
266 #define RT_SDHCI_PRESET_DRV_MASK RT_GENMASK(15, 14)
267 #define BIT(nr) ((1) << (nr))
268
269 #define RT_SDHCI_PRESET_CLKGEN_SEL BIT(10)
270 #define RT_SDHCI_PRESET_SDCLK_FREQ_MASK RT_GENMASK(9, 0)
271
272 #define RT_SDHCI_SLOT_INT_STATUS 0xFC
273
274 #define RT_SDHCI_HOST_VERSION 0xFE
275 #define RT_SDHCI_VENDOR_VER_MASK 0xFF00
276 #define RT_SDHCI_VENDOR_VER_SHIFT 8
277 #define RT_SDHCI_SPEC_VER_MASK 0x00FF
278 #define RT_SDHCI_SPEC_VER_SHIFT 0
279 #define RT_SDHCI_SPEC_100 0
280 #define RT_SDHCI_SPEC_200 1
281 #define RT_SDHCI_SPEC_300 2
282 #define RT_SDHCI_SPEC_400 3
283 #define RT_SDHCI_SPEC_410 4
284 #define RT_SDHCI_SPEC_420 5
285
286 /*
287 * End of controller registers.
288 */
289
290 #define RT_SDHCI_MAX_DIV_SPEC_200 256
291 #define RT_SDHCI_MAX_DIV_SPEC_300 2046
292
293 /*
294 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
295 */
296 #define RT_SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
297 #define ilog2(v) __rt_ffs(v)
298 #define RT_SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(RT_SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
299 #define RT_SDHCI_MAX_SEGS 128
300
301 /* Allow for a command request and a data request at the same time */
302 #define RT_SDHCI_MAX_MRQS 2
303 #define MMC_CMD_TRANSFER_TIME (10 * 1000000L) /* max 10 ms */
304
305
306 enum rt_sdhci_cookie
307 {
308 COOKIE_UNMAPPED,
309 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
310 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */
311 };
312
313 struct rt_sdhci_host
314 {
315 const char *hw_name; /* Hardware bus name */
316
317 unsigned int quirks; /* Deviations from spec. */
318
319 void *data_buf;
320 /* Controller doesn't honor resets unless we touch the clock register */
321 #define RT_SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0)
322 /* Controller has bad caps bits, but really supports DMA */
323 #define RT_SDHCI_QUIRK_FORCE_DMA (1 << 1)
324 /* Controller doesn't like to be reset when there is no card inserted. */
325 #define RT_SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 2)
326 /* Controller doesn't like clearing the power reg before a change */
327 #define RT_SDHCI_QUIRK_SINGLE_POWER_WRITE (1 << 3)
328 /* Controller has an unusable DMA engine */
329 #define RT_SDHCI_QUIRK_BROKEN_DMA (1 << 5)
330 /* Controller has an unusable ADMA engine */
331 #define RT_SDHCI_QUIRK_BROKEN_ADMA (1 << 6)
332 /* Controller can only DMA from 32-bit aligned addresses */
333 #define RT_SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 7)
334 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
335 #define RT_SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 8)
336 /* Controller can only ADMA chunks that are a multiple of 32 bits */
337 #define RT_SDHCI_QUIRK_32BIT_ADMA_SIZE (1 << 9)
338 /* Controller needs to be reset after each request to stay stable */
339 #define RT_SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 10)
340 /* Controller needs voltage and power writes to happen separately */
341 #define RT_SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 11)
342 /* Controller provides an incorrect timeout value for transfers */
343 #define RT_SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 12)
344 /* Controller has an issue with buffer bits for small transfers */
345 #define RT_SDHCI_QUIRK_BROKEN_SMALL_PIO (1 << 13)
346 /* Controller does not provide transfer-complete interrupt when not busy */
347 #define RT_SDHCI_QUIRK_NO_BUSY_IRQ (1 << 14)
348 /* Controller has unreliable card detection */
349 #define RT_SDHCI_QUIRK_BROKEN_CARD_DETECTION (1 << 15)
350 /* Controller reports inverted write-protect state */
351 #define RT_SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1 << 16)
352 /* Controller has unusable command queue engine */
353 #define RT_SDHCI_QUIRK_BROKEN_CQE (1 << 17)
354 /* Controller does not like fast PIO transfers */
355 #define RT_SDHCI_QUIRK_PIO_NEEDS_DELAY (1 << 18)
356 /* Controller does not have a LED */
357 #define RT_SDHCI_QUIRK_NO_LED (1 << 19)
358 /* Controller has to be forced to use block size of 2048 bytes */
359 #define RT_SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1 << 20)
360 /* Controller cannot do multi-block transfers */
361 #define RT_SDHCI_QUIRK_NO_MULTIBLOCK (1 << 21)
362 /* Controller can only handle 1-bit data transfers */
363 #define RT_SDHCI_QUIRK_FORCE_1_BIT_DATA (1 << 22)
364 /* Controller needs 10ms delay between applying power and clock */
365 #define RT_SDHCI_QUIRK_DELAY_AFTER_POWER (1 << 23)
366 /* Controller uses SDCLK instead of TMCLK for data timeouts */
367 #define RT_SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24)
368 /* Controller reports wrong base clock capability */
369 #define RT_SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1 << 25)
370 /* Controller cannot support End Attribute in NOP ADMA descriptor */
371 #define RT_SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1 << 26)
372 /* Controller uses Auto CMD12 command to stop the transfer */
373 #define RT_SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1 << 28)
374 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
375 #define RT_SDHCI_QUIRK_NO_HISPD_BIT (1 << 29)
376 /* Controller treats ADMA descriptors with length 0000h incorrectly */
377 #define RT_SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1 << 30)
378 /* The read-only detection via RT_SDHCI_PRESENT_STATE register is unstable */
379 #define RT_SDHCI_QUIRK_UNSTABLE_RO_DETECT (1 << 31)
380
381 unsigned int quirks2; /* More deviations from spec. */
382
383 #define RT_SDHCI_QUIRK2_HOST_OFF_CARD_ON (1 << 0)
384 #define RT_SDHCI_QUIRK2_HOST_NO_CMD23 (1 << 1)
385 /* The system physically doesn't support 1.8v, even if the host does */
386 #define RT_SDHCI_QUIRK2_NO_1_8_V (1 << 2)
387 #define RT_SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1 << 3)
388 #define RT_SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1 << 4)
389 /* Controller has a non-standard host control register */
390 #define RT_SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1 << 5)
391 /* Controller does not support HS200 */
392 #define RT_SDHCI_QUIRK2_BROKEN_HS200 (1 << 6)
393 /* Controller does not support DDR50 */
394 #define RT_SDHCI_QUIRK2_BROKEN_DDR50 (1 << 7)
395 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
396 #define RT_SDHCI_QUIRK2_STOP_WITH_TC (1 << 8)
397 /* Controller does not support 64-bit DMA */
398 #define RT_SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1 << 9)
399 /* need clear transfer mode register before send cmd */
400 #define RT_SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1 << 10)
401 /* Capability register bit-63 indicates HS400 support */
402 #define RT_SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1 << 11)
403 /* forced tuned clock */
404 #define RT_SDHCI_QUIRK2_TUNING_WORK_AROUND (1 << 12)
405 /* disable the block count for single block transactions */
406 #define RT_SDHCI_QUIRK2_SUPPORT_SINGLE (1 << 13)
407 /* Controller broken with using ACMD23 */
408 #define RT_SDHCI_QUIRK2_ACMD23_BROKEN (1 << 14)
409 /* Broken Clock divider zero in controller */
410 #define RT_SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1 << 15)
411 /* Controller has CRC in 136 bit Command Response */
412 #define RT_SDHCI_QUIRK2_RSP_136_HAS_CRC (1 << 16)
413
414 #define RT_SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1 << 17)
415
416 #define RT_SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1 << 18)
417 /* Issue CMD and DATA reset together */
418 #define RT_SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1 << 19)
419
420 int irq; /* Device IRQ */
421 void *ioaddr; /* Mapped address */
422 char *bounce_buffer; /* For packing SDMA reads/writes */
423 rt_uint64_t bounce_addr;
424 unsigned int bounce_buffer_size;
425
426 const struct rt_sdhci_ops *ops; /* Low level hw interface */
427
428 /* Internal data */
429 struct rt_mmc_host *mmc; /* MMC structure */
430 struct mmc_host_ops mmc_host_ops; /* MMC host ops */
431 rt_uint64_t dma_mask; /* custom DMA mask */
432
433 rt_spinlock_t lock;
434 int flags; /* Host attributes */
435 #define RT_SDHCI_USE_SDMA (1 << 0) /* Host is SDMA capable */
436 #define RT_SDHCI_USE_ADMA (1 << 1) /* Host is ADMA capable */
437 #define RT_SDHCI_REQ_USE_DMA (1 << 2) /* Use DMA for this req. */
438 #define RT_SDHCI_DEVICE_DEAD (1 << 3) /* Device unresponsive */
439 #define RT_SDHCI_SDR50_NEEDS_TUNING (1 << 4) /* SDR50 needs tuning */
440 #define RT_SDHCI_AUTO_CMD12 (1 << 6) /* Auto CMD12 support */
441 #define RT_SDHCI_AUTO_CMD23 (1 << 7) /* Auto CMD23 support */
442 #define RT_SDHCI_PV_ENABLED (1 << 8) /* Preset value enabled */
443 #define RT_SDHCI_USE_64_BIT_DMA (1 << 12) /* Use 64-bit DMA */
444 #define RT_SDHCI_HS400_TUNING (1 << 13) /* Tuning for HS400 */
445 #define RT_SDHCI_SIGNALING_330 (1 << 14) /* Host is capable of 3.3V signaling */
446 #define RT_SDHCI_SIGNALING_180 (1 << 15) /* Host is capable of 1.8V signaling */
447 #define RT_SDHCI_SIGNALING_120 (1 << 16) /* Host is capable of 1.2V signaling */
448
449 unsigned int version; /* RT_SDHCI spec. version */
450
451 unsigned int max_clk; /* Max possible freq (MHz) */
452 unsigned int timeout_clk; /* Timeout freq (KHz) */
453 rt_uint8_t max_timeout_count; /* Vendor specific max timeout count */
454 unsigned int clk_mul; /* Clock Muliplier value */
455
456 unsigned int clock; /* Current clock (MHz) */
457 rt_uint8_t pwr; /* Current voltage */
458 rt_uint8_t drv_type; /* Current UHS-I driver type */
459 rt_bool_t reinit_uhs; /* Force UHS-related re-initialization */
460
461 rt_bool_t runtime_suspended; /* Host is runtime suspended */
462 rt_bool_t bus_on; /* Bus power prevents runtime suspend */
463 rt_bool_t preset_enabled; /* Preset is enabled */
464 rt_bool_t pending_reset; /* Cmd/data reset is pending */
465 rt_bool_t irq_wake_enabled; /* IRQ wakeup is enabled */
466 rt_bool_t v4_mode; /* Host Version 4 Enable */
467 rt_bool_t always_defer_done; /* Always defer to complete requests */
468
469 struct rt_mmcsd_req *mrqs_done[RT_SDHCI_MAX_MRQS]; /* Requests done */
470 struct rt_mmcsd_cmd *cmd; /* Current command */
471 struct rt_mmcsd_cmd *data_cmd; /* Current data command */
472 struct rt_mmcsd_cmd *deferred_cmd; /* Deferred command */
473 struct rt_mmcsd_data *data; /* Current data request */
474 unsigned int data_early : 1; /* Data finished before cmd */
475
476 unsigned int blocks; /* remaining PIO blocks */
477 size_t align_buffer_sz; /* Bounce buffer size */
478 rt_uint64_t align_addr; /* Mapped bounce buffer */
479
480 struct rt_workqueue *complete_wq; /* Request completion wq */
481 struct rt_work complete_work; /* Request completion work */
482
483 struct rt_workqueue *irq_wq;
484 struct rt_work irq_work;
485
486 struct rt_timer timer; /* Timer for timeouts */
487 struct rt_timer data_timer; /* Timer for data timeouts */
488
489 rt_uint32_t caps; /* CAPABILITY_0 */
490 rt_uint32_t caps1; /* CAPABILITY_1 */
491 rt_bool_t read_caps; /* Capability flags have been read */
492
493 rt_bool_t sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */
494 unsigned int ocr_avail_sdio; /* OCR bit masks */
495 unsigned int ocr_avail_sd;
496 unsigned int ocr_avail_mmc;
497 rt_uint32_t ocr_mask; /* available voltages */
498
499 unsigned timing; /* Current timing */
500
501 rt_uint32_t thread_isr;
502
503 /* cached registers */
504 rt_uint32_t ier;
505
506 rt_bool_t cqe_on; /* CQE is operating */
507 rt_uint32_t cqe_ier; /* CQE interrupt mask */
508 rt_uint32_t cqe_err_ier; /* CQE error interrupt mask */
509
510 rt_wqueue_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
511 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
512
513 unsigned int tuning_count; /* Timer count for re-tuning */
514 unsigned int tuning_mode; /* Re-tuning mode supported by host */
515 unsigned int tuning_err; /* Error code for re-tuning */
516 #define RT_SDHCI_TUNING_MODE_1 0
517 #define RT_SDHCI_TUNING_MODE_2 1
518 #define RT_SDHCI_TUNING_MODE_3 2
519 /* Delay (ms) between tuning commands */
520 int tuning_delay;
521 int tuning_loop_count;
522
523 /* Host SDMA buffer boundary. */
524 rt_uint32_t sdma_boundary;
525 rt_uint64_t data_timeout;
526
527 unsigned long private[];
528 };
529
u8_read(const volatile void * addr)530 static inline rt_uint8_t u8_read(const volatile void *addr)
531 {
532 return *(const volatile rt_uint8_t *)addr;
533 }
534
u16_read(const volatile void * addr)535 static inline rt_uint16_t u16_read(const volatile void *addr)
536 {
537 return *(const volatile rt_uint16_t *)addr;
538 }
539
u32_read(const volatile void * addr)540 static inline rt_uint32_t u32_read(const volatile void *addr)
541 {
542 return *(const volatile rt_uint32_t *)addr;
543 }
544
u8_write(rt_uint8_t value,volatile void * addr)545 static inline void u8_write(rt_uint8_t value, volatile void *addr)
546 {
547 *(volatile rt_uint8_t *)addr = value;
548 }
549
u16_write(rt_uint16_t value,volatile void * addr)550 static inline void u16_write(rt_uint16_t value, volatile void *addr)
551 {
552 *(volatile rt_uint16_t *)addr = value;
553 }
554
u32_write(rt_uint32_t value,volatile void * addr)555 static inline void u32_write(rt_uint32_t value, volatile void *addr)
556 {
557 *(volatile rt_uint32_t *)addr = value;
558 }
559
560 #define readb(c) u8_read(c)
561 #define readw(c) u16_read(c)
562 #define readl(c) u32_read(c)
563 #define readsb(p, d, l) ({ __raw_readsb(p,d,l); __iormb(); })
564 #define readsw(p, d, l) ({ __raw_readsw(p,d,l); __iormb(); })
565 #define readsl(p, d, l) ({ __raw_readsl(p,d,l); __iormb(); })
566
567 #define writeb(v, c) u8_write(v, c)
568 #define writew(v, c) u16_write(v, c)
569 #define writel(v, c) u32_write(v, c)
570 #define writesb(p, d, l) ({ __iowmb(); __raw_writesb(p,d,l); })
571 #define writesw(p, d, l) ({ __iowmb(); __raw_writesw(p,d,l); })
572 #define writesl(p, d, l) ({ __iowmb(); __raw_writesl(p,d,l); })
573
rt_sdhci_writel(struct rt_sdhci_host * host,rt_uint32_t val,int reg)574 static inline void rt_sdhci_writel(struct rt_sdhci_host *host, rt_uint32_t val, int reg)
575 {
576 writel(val, host->ioaddr + reg);
577 }
578
rt_sdhci_writew(struct rt_sdhci_host * host,rt_uint16_t val,int reg)579 static inline void rt_sdhci_writew(struct rt_sdhci_host *host, rt_uint16_t val, int reg)
580 {
581 writew(val, host->ioaddr + reg);
582 }
583
rt_sdhci_writeb(struct rt_sdhci_host * host,rt_uint8_t val,int reg)584 static inline void rt_sdhci_writeb(struct rt_sdhci_host *host, rt_uint8_t val, int reg)
585 {
586 writeb(val, host->ioaddr + reg);
587 }
588
rt_sdhci_readl(struct rt_sdhci_host * host,int reg)589 static inline rt_uint32_t rt_sdhci_readl(struct rt_sdhci_host *host, int reg)
590 {
591 return readl(host->ioaddr + reg);
592 }
593
rt_sdhci_readw(struct rt_sdhci_host * host,int reg)594 static inline rt_uint16_t rt_sdhci_readw(struct rt_sdhci_host *host, int reg)
595 {
596 return readw(host->ioaddr + reg);
597 }
598
rt_sdhci_readb(struct rt_sdhci_host * host,int reg)599 static inline rt_uint8_t rt_sdhci_readb(struct rt_sdhci_host *host, int reg)
600 {
601 return readb(host->ioaddr + reg);
602 }
603
604
605 struct rt_sdhci_ops
606 {
607 void (*set_clock)(struct rt_sdhci_host *host, unsigned int clock);
608 void (*set_power)(struct rt_sdhci_host *host, unsigned char mode,
609 unsigned short vdd);
610 rt_uint32_t (*irq)(struct rt_sdhci_host *host, rt_uint32_t intmask);
611 int (*set_dma_mask)(struct rt_sdhci_host *host);
612 int (*enable_dma)(struct rt_sdhci_host *host);
613 unsigned int (*get_max_clock)(struct rt_sdhci_host *host);
614 unsigned int (*get_min_clock)(struct rt_sdhci_host *host);
615 unsigned int (*get_timeout_clock)(struct rt_sdhci_host *host);
616 unsigned int (*get_max_timeout_count)(struct rt_sdhci_host *host);
617 void (*set_timeout)(struct rt_sdhci_host *host,
618 struct rt_mmcsd_cmd *cmd);
619 void (*set_bus_width)(struct rt_sdhci_host *host, int width);
620 unsigned int (*get_ro)(struct rt_sdhci_host *host);
621 void (*reset)(struct rt_sdhci_host *host, rt_uint8_t mask);
622 int (*platform_execute_tuning)(struct rt_sdhci_host *host, rt_uint32_t opcode);
623 void (*set_uhs_signaling)(struct rt_sdhci_host *host, unsigned int uhs);
624 void (*hw_reset)(struct rt_sdhci_host *host);
625 void (*card_event)(struct rt_sdhci_host *host);
626 void (*voltage_switch)(struct rt_sdhci_host *host);
627 void (*request_done)(struct rt_sdhci_host *host,
628 struct rt_mmcsd_req *mrq);
629 };
630
631
632 struct rt_sdhci_host *rt_sdhci_alloc_host(struct rt_device *dev, size_t priv_size);
633 void rt_sdhci_free_host(struct rt_sdhci_host *host);
634
sdhci_priv(struct rt_sdhci_host * host)635 static inline void *sdhci_priv(struct rt_sdhci_host *host)
636 {
637 return host->private;
638 }
639
640 void rt_sdhci_read_caps(struct rt_sdhci_host *host, const rt_uint16_t *ver,
641 const rt_uint32_t *caps, const rt_uint32_t *caps1);
642 int rt_sdhci_setup_host(struct rt_sdhci_host *host);
643 void rt_sdhci_cleanup_host(struct rt_sdhci_host *host);
644 int rt_sdhci_set_and_add_host(struct rt_sdhci_host *host);
645 int rt_sdhci_init_host(struct rt_sdhci_host *host);
646 void rt_sdhci_uninit_host(struct rt_sdhci_host *host, int dead);
647
648 rt_uint16_t rt_sdhci_clk_set(struct rt_sdhci_host *host, unsigned int clock,
649 unsigned int *actual_clock);
650 void rt_sdhci_set_clock(struct rt_sdhci_host *host, unsigned int clock);
651 void rt_sdhci_clk_enable(struct rt_sdhci_host *host, rt_uint16_t clk);
652 void rt_sdhci_set_power(struct rt_sdhci_host *host, unsigned char mode,unsigned short vdd);
653 void rt_read_reg(struct rt_sdhci_host* host);
654
655 void rt_sdhci_set_power_with_noreg(struct rt_sdhci_host *host, unsigned char mode,
656 unsigned short vdd);
657 void rt_sdhci_start_request(struct rt_mmc_host *mmc, struct rt_mmcsd_req *mrq);
658 int rt_sdhci_start_request_atomic(struct rt_mmc_host *mmc, struct rt_mmcsd_req *mrq);
659 void rt_sdhci_set_bus_width(struct rt_sdhci_host *host, int width);
660 void rt_sdhci_reset(struct rt_sdhci_host *host, rt_uint8_t mask);
661 void rt_sdhci_set_uhs(struct rt_sdhci_host *host, unsigned timing);
662 int rt_sdhci_execute_tuning(struct rt_mmc_host *mmc, rt_uint32_t opcode);
663 int __sdhci_execute_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode);
664 void rt_sdhci_ios_set(struct rt_mmc_host *mmc, struct rt_mmcsd_io_cfg *ios);
665 int rt_sdhci_start_signal_voltage_switch(struct rt_mmc_host *mmc,
666 struct rt_mmcsd_io_cfg *ios);
667 void rt_sdhci_enable_io_irq(struct rt_mmc_host *mmc, int enable);
668 void rt_sdhci_start_tuning(struct rt_sdhci_host *host);
669 void rt_sdhci_end_tuning(struct rt_sdhci_host *host);
670 void rt_sdhci_reset_tuning(struct rt_sdhci_host *host);
671 void rt_sdhci_send_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode);
672 void rt_sdhci_abort_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode);
673 void rt_sdhci_data_irq_timeout(struct rt_sdhci_host *host, rt_bool_t enable);
674 void rt_sdhci_timeout_set(struct rt_sdhci_host *host, struct rt_mmcsd_cmd *cmd);
675 void rt_read_reg_debug(struct rt_sdhci_host* host);
676
677 #endif /* __RT_SDHCI_HW_H */
678