1/*
2 * Copyright (c) 2006-2019, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date           Author       Notes
8 * 2013-07-05     Bernard      the first version
9 */
10
11.globl rt_cpu_get_smp_id
12rt_cpu_get_smp_id:
13    mrc     p15, #0, r0, c0, c0, #5
14    bx      lr
15
16.globl rt_cpu_vector_set_base
17rt_cpu_vector_set_base:
18    /* clear SCTRL.V to customize the vector address */
19    mrc     p15, #0, r1, c1, c0, #0
20    bic     r1, #(1 << 13)
21    mcr     p15, #0, r1, c1, c0, #0
22    /* set up the vector address */
23    mcr     p15, #0, r0, c12, c0, #0
24    dsb
25    bx      lr
26
27.globl rt_hw_cpu_dcache_enable
28rt_hw_cpu_dcache_enable:
29    mrc     p15, #0, r0, c1, c0, #0
30    orr     r0,  r0, #0x00000004
31    mcr     p15, #0, r0, c1, c0, #0
32    bx      lr
33
34.globl rt_hw_cpu_icache_enable
35rt_hw_cpu_icache_enable:
36    mrc     p15, #0, r0, c1, c0, #0
37    orr     r0,  r0, #0x00001000
38    mcr     p15, #0, r0, c1, c0, #0
39    bx      lr
40
41_FLD_MAX_WAY:
42   .word  0x3ff
43_FLD_MAX_IDX:
44   .word  0x7ff
45
46.globl set_timer_counter
47set_timer_counter:
48    mcr     p15, #0, r0, c14, c3, #0  @ write virtual timer timerval register
49    bx      lr
50.globl set_timer_control
51set_timer_control:
52    mcr     p15, #0, r0, c14, c3, #1  @ write virtual timer control register
53    bx      lr
54
55.globl rt_cpu_dcache_clean_flush
56rt_cpu_dcache_clean_flush:
57    push    {r4-r11}
58    dmb
59    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
60    ands    r3, r0, #0x7000000       @ get level of coherency
61    mov     r3, r3, lsr #23
62    beq     finished
63    mov     r10, #0
64loop1:
65    add     r2, r10, r10, lsr #1
66    mov     r1, r0, lsr r2
67    and     r1, r1, #7
68    cmp     r1, #2
69    blt     skip
70    mcr     p15, #2, r10, c0, c0, #0
71    isb
72    mrc     p15, #1, r1, c0, c0, #0
73    and     r2, r1, #7
74    add     r2, r2, #4
75    ldr     r4, _FLD_MAX_WAY
76    ands    r4, r4, r1, lsr #3
77    clz     r5, r4
78    ldr     r7, _FLD_MAX_IDX
79    ands    r7, r7, r1, lsr #13
80loop2:
81    mov     r9, r4
82loop3:
83    orr     r11, r10, r9, lsl r5
84    orr     r11, r11, r7, lsl r2
85    mcr     p15, #0, r11, c7, c14, #2
86    subs    r9, r9, #1
87    bge     loop3
88    subs    r7, r7, #1
89    bge     loop2
90skip:
91    add     r10, r10, #2
92    cmp     r3, r10
93    bgt     loop1
94
95finished:
96    dsb
97    isb
98    pop     {r4-r11}
99    bx      lr
100
101.globl rt_cpu_icache_flush
102rt_cpu_icache_flush:
103    mov r0, #0
104    mcr p15, 0, r0, c7, c5, 0       @ I+BTB cache invalidate
105    dsb
106    isb
107    bx      lr
108
109.globl rt_hw_cpu_dcache_disable
110rt_hw_cpu_dcache_disable:
111    push    {r4-r11, lr}
112    bl      rt_cpu_dcache_clean_flush
113    mrc     p15, #0, r0, c1, c0, #0
114    bic     r0,  r0, #0x00000004
115    mcr     p15, #0, r0, c1, c0, #0
116    pop     {r4-r11, lr}
117    bx      lr
118
119.globl rt_hw_cpu_icache_disable
120rt_hw_cpu_icache_disable:
121    mrc     p15, #0, r0, c1, c0, #0
122    bic     r0,  r0, #0x00001000
123    mcr     p15, #0, r0, c1, c0, #0
124    bx      lr
125
126.globl rt_cpu_mmu_disable
127rt_cpu_mmu_disable:
128    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
129    mrc     p15, #0, r0, c1, c0, #0
130    bic     r0, r0, #1
131    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
132    dsb
133    bx      lr
134
135.globl rt_cpu_mmu_enable
136rt_cpu_mmu_enable:
137    mrc     p15, #0, r0, c1, c0, #0
138    orr     r0, r0, #0x001
139    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
140    dsb
141    bx      lr
142
143.globl rt_cpu_tlb_set
144rt_cpu_tlb_set:
145    mcr     p15, #0, r0, c2, c0, #0
146    dmb
147    bx      lr
148