1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 #include "hal_conf.h" 7 8 #ifdef HAL_UART_MODULE_ENABLED 9 10 /** @addtogroup RK_HAL_Driver 11 * @{ 12 */ 13 14 /** @addtogroup UART 15 * @{ 16 */ 17 18 #ifndef _HAL_UART_H_ 19 #define _HAL_UART_H_ 20 21 #include "hal_def.h" 22 #include "hal_base.h" 23 24 /***************************** MACRO Definition ******************************/ 25 /** @defgroup UART_Exported_Definition_Group1 Basic Definition 26 * @{ 27 */ 28 29 /* Out: Interrupt Enable Register */ 30 #define UART_IER_PTIME 0x80 /**< Enable Programmable THRE Interrupt Mode */ 31 #define UART_IER_MSI 0x08 /**< Enable Modem status interrupt */ 32 #define UART_IER_RLSI 0x04 /**< Enable receiver line status interrupt */ 33 #define UART_IER_THRI 0x02 /**< Enable Transmitter holding register int. */ 34 #define UART_IER_RDI 0x01 /**< Enable receiver data interrupt */ 35 36 /* In: Interrupt ID Register */ 37 #define UART_IIR_MASK 0x0f /**< Interrupt ID Mask */ 38 #define UART_IIR_NO_INT 0x01 /**< No interrupts pending */ 39 #define UART_IIR_ID 0x0e /**< Mask for the interrupt ID */ 40 #define UART_IIR_MSI 0x00 /**< Modem status interrupt */ 41 #define UART_IIR_THRI 0x02 /**< Transmitter holding register empty */ 42 #define UART_IIR_RDI 0x04 /**< Receiver data interrupt */ 43 #define UART_IIR_RLSI 0x06 /**< Receiver line status interrupt */ 44 #define UART_IIR_BUSY 0x07 /**< DesignWare APB Busy Detect */ 45 #define UART_IIR_RX_TIMEOUT 0x0c /**< RX Timeout interrupt */ 46 47 /* Out: FIFO Control Register */ 48 #define UART_FCR_ENABLE_FIFO 0x01 /**< Enable the FIFO */ 49 #define UART_FCR_CLEAR_RCVR 0x02 /**< Clear the RCVR FIFO */ 50 #define UART_FCR_CLEAR_XMIT 0x04 /**< Clear the XMIT FIFO */ 51 #define UART_FCR_DMA_SELECT 0x08 /**< For DMA applications */ 52 53 #define UART_FCR_R_TRIG_00 0x00 54 #define UART_FCR_R_TRIG_01 0x40 55 #define UART_FCR_R_TRIG_10 0x80 56 #define UART_FCR_R_TRIG_11 0xc0 57 #define UART_FCR_T_TRIG_00 0x00 58 #define UART_FCR_T_TRIG_01 0x10 59 #define UART_FCR_T_TRIG_10 0x20 60 #define UART_FCR_T_TRIG_11 0x30 61 62 #define UART_FCR_TRIGGER_MASK 0xC0 /**< Mask for the FIFO trigger range */ 63 #define UART_FCR_TRIGGER_1 0x00 /**< Mask for trigger set at 1 */ 64 #define UART_FCR_TRIGGER_4 0x40 /**< Mask for trigger set at 4 */ 65 #define UART_FCR_TRIGGER_8 0x80 /**< Mask for trigger set at 8 */ 66 #define UART_FCR_TRIGGER_14 0xC0 /**< Mask for trigger set at 14 */ 67 /* 16650 definitions */ 68 #define UART_FCR6_R_TRIGGER_8 0x00 /**< Mask for receive trigger set at 1 */ 69 #define UART_FCR6_R_TRIGGER_16 0x40 /**< Mask for receive trigger set at 4 */ 70 #define UART_FCR6_R_TRIGGER_24 0x80 /**< Mask for receive trigger set at 8 */ 71 #define UART_FCR6_R_TRIGGER_28 0xC0 /**< Mask for receive trigger set at 14 */ 72 #define UART_FCR6_T_TRIGGER_16 0x00 /**< Mask for transmit trigger set at 16 */ 73 #define UART_FCR6_T_TRIGGER_8 0x10 /**< Mask for transmit trigger set at 8 */ 74 #define UART_FCR6_T_TRIGGER_24 0x20 /**< Mask for transmit trigger set at 24 */ 75 #define UART_FCR6_T_TRIGGER_30 0x30 /**< Mask for transmit trigger set at 30 */ 76 #define UART_FCR7_64BYTE 0x20 77 /* Go into 64 byte mode (TI16C750 and some Freescale UARTs) */ 78 79 #define UART_FCR_R_TRIG_SHIFT 6 80 #define UART_FCR_R_TRIG_BITS(x) (((x)&UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT) 81 #define UART_FCR_R_TRIG_MAX_STATE 4 82 83 /* Out: Line Control Register */ 84 /* 85 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 86 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 87 */ 88 #define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */ 89 #define UART_LCR_SBC 0x40 /**< Set break control */ 90 #define UART_LCR_SPAR 0x20 /**< Stick parity (?) */ 91 #define UART_LCR_EPAR 0x10 /**< Even parity select */ 92 #define UART_LCR_PARITY 0x08 /**< Parity Enable */ 93 #define UART_LCR_STOP 0x04 /**< Stop bits: 0=1 bit, 1=2 bits */ 94 #define UART_LCR_WLEN5 0x00 /**< Wordlength: 5 bits */ 95 #define UART_LCR_WLEN6 0x01 /**< Wordlength: 6 bits */ 96 #define UART_LCR_WLEN7 0x02 /**< Wordlength: 7 bits */ 97 #define UART_LCR_WLEN8 0x03 /**< Wordlength: 8 bits */ 98 99 /* Out: Modem Control Register */ 100 #define UART_MCR_CLKSEL 0x80 /**< Divide clock by 4 (TI16C752, EFR[4]=1) */ 101 #define UART_MCR_TCRTLR 0x40 /**< Access TCR/TLR (TI16C752, EFR[4]=1) */ 102 #define UART_MCR_XONANY 0x20 /**< Enable Xon Any (TI16C752, EFR[4]=1) */ 103 #define UART_MCR_AFE 0x20 /**< Enable auto-RTS/CTS (TI16C550C/TI16C750) */ 104 #define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */ 105 #define UART_MCR_OUT2 0x08 /**< Out2 complement */ 106 #define UART_MCR_OUT1 0x04 /**< Out1 complement */ 107 #define UART_MCR_RTS 0x02 /**< RTS complement */ 108 #define UART_MCR_DTR 0x01 /**< DTR complement */ 109 110 /* In: Line Status Register */ 111 #define UART_LSR_FIFOE 0x80 /**< Fifo error */ 112 #define UART_LSR_TEMT 0x40 /**< Transmitter empty */ 113 #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */ 114 #define UART_LSR_BI 0x10 /**< Break interrupt indicator */ 115 #define UART_LSR_FE 0x08 /**< Frame error indicator */ 116 #define UART_LSR_PE 0x04 /**< Parity error indicator */ 117 #define UART_LSR_OE 0x02 /**< Overrun error indicator */ 118 #define UART_LSR_DR 0x01 /**< Receiver data ready */ 119 #define UART_LSR_BRK_ERROR_BITS 0x1E /**< BI, FE, PE, OE bits */ 120 121 /* In: Modem Status Register */ 122 #define UART_MSR_DCD 0x80 /**< Data Carrier Detect */ 123 #define UART_MSR_RI 0x40 /**< Ring Indicator */ 124 #define UART_MSR_DSR 0x20 /**< Data Set Ready */ 125 #define UART_MSR_CTS 0x10 /**< Clear to Send */ 126 #define UART_MSR_DDCD 0x08 /**< Delta DCD */ 127 #define UART_MSR_TERI 0x04 /**< Trailing edge ring indicator */ 128 #define UART_MSR_DDSR 0x02 /**< Delta DSR */ 129 #define UART_MSR_DCTS 0x01 /**< Delta CTS */ 130 #define UART_MSR_ANY_DELTA 0x0F /**< Any of the delta bits! */ 131 132 #define UART_USR_RX_FIFO_FULL 0x10 /**< Receive FIFO full */ 133 #define UART_USR_RX_FIFO_NOT_EMPTY 0x08 /**< Receive FIFO not empty */ 134 #define UART_USR_TX_FIFO_EMPTY 0x04 /**< Transmit FIFO empty */ 135 #define UART_USR_TX_FIFO_NOT_FULL 0x02 /**< Transmit FIFO not full */ 136 #define UART_USR_BUSY 0x01 /**< UART busy indicator */ 137 138 #define UART_SRR_UR 0x1 /**< UART Reset */ 139 #define UART_SRR_RFR 0X2 /**< RCVR FIFO Reset */ 140 #define UART_SRR_XFR 0x4 /**< XMIT FIFO Reset */ 141 142 #define MODE_X_DIV 16 /**< baud = f / 16 / div */ 143 144 /***************************** Structure Definition **************************/ 145 146 /** 147 * @brief UART baud rate definition 148 */ 149 typedef enum { 150 UART_BR_110 = 110, 151 UART_BR_300 = 300, 152 UART_BR_600 = 600, 153 UART_BR_1200 = 1200, 154 UART_BR_2400 = 2400, 155 UART_BR_4800 = 4800, 156 UART_BR_9600 = 9600, 157 UART_BR_14400 = 14400, 158 UART_BR_19200 = 19200, 159 UART_BR_38400 = 38400, 160 UART_BR_57600 = 57600, 161 UART_BR_115200 = 115200, 162 UART_BR_230400 = 230400, 163 UART_BR_380400 = 380400, 164 UART_BR_460800 = 460800, 165 UART_BR_921600 = 921600, 166 UART_BR_1000000 = 1000000, 167 UART_BR_1500000 = 1500000, 168 UART_BR_2000000 = 2000000, 169 UART_BR_3000000 = 3000000, 170 UART_BR_4000000 = 4000000, 171 } eUART_baudRate; 172 173 /** 174 * @brief UART data bit definition 175 */ 176 typedef enum { 177 UART_DATA_5B = 5, 178 UART_DATA_6B, 179 UART_DATA_7B, 180 UART_DATA_8B 181 } eUART_dataLen; 182 183 /** 184 * @brief UART stop bit definition 185 */ 186 typedef enum { 187 UART_ONE_STOPBIT, 188 UART_ONE_AND_HALF_OR_TWO_STOPBIT 189 } eUART_stopBit; 190 191 /** 192 * @brief UART parity definition 193 */ 194 typedef enum { 195 UART_ODD_PARITY, 196 UART_EVEN_PARITY, 197 UART_PARITY_DISABLE 198 } eUART_parityEn; 199 200 /** 201 * @brief UART config definition 202 */ 203 struct HAL_UART_CONFIG { 204 eUART_baudRate baudRate; 205 eUART_dataLen dataBit; 206 eUART_stopBit stopBit; 207 eUART_parityEn parity; 208 }; 209 210 /** 211 * @brief UART HW information definition on a soc 212 */ 213 struct HAL_UART_DEV { 214 struct UART_REG *pReg; /**< registers base address */ 215 216 /* sclk is for uart logic, pclk is for register access */ 217 eCLOCK_Name sclkID; 218 uint32_t sclkGateID; 219 uint32_t pclkGateID; 220 221 IRQn_Type irqNum; 222 bool isAutoFlow; 223 ePM_RUNTIME_ID runtimeID; 224 DMA_REQ_Type dmaTxReqNum; /**< peri dma tx request num */ 225 DMA_REQ_Type dmaRxReqNum; /**< peri dma rx request num */ 226 struct DMA_REG *dmac; /**< dmac reg base ptr */ 227 }; 228 229 /** 230 * @brief Save UART regist 231 */ 232 struct UART_SAVE_CONFIG { 233 uint32_t DLL; 234 uint32_t DLH; 235 uint32_t IER; 236 uint32_t LCR; 237 uint32_t MCR; 238 uint32_t SRT; 239 uint32_t STET; 240 }; 241 242 /** @} */ 243 244 /***************************** Function Declare ******************************/ 245 /** @defgroup UART_Public_Function_Declare Public Function Declare 246 * @{ 247 */ 248 void HAL_UART_EnableIrq(struct UART_REG *pReg, uint32_t uartIntNumb); 249 void HAL_UART_DisableIrq(struct UART_REG *pReg, uint32_t uartIntNumb); 250 void HAL_UART_EnableLoopback(struct UART_REG *pReg); 251 void HAL_UART_DisableLoopback(struct UART_REG *pReg); 252 void HAL_UART_EnableAutoFlowControl(struct UART_REG *pReg); 253 void HAL_UART_DisableAutoFlowControl(struct UART_REG *pReg); 254 uint32_t HAL_UART_GetIrqID(struct UART_REG *pReg); 255 uint32_t HAL_UART_GetLsr(struct UART_REG *pReg); 256 uint32_t HAL_UART_GetUsr(struct UART_REG *pReg); 257 uint32_t HAL_UART_GetMsr(struct UART_REG *pReg); 258 void HAL_UART_SerialOutChar(struct UART_REG *pReg, char c); 259 int HAL_UART_SerialOut(struct UART_REG *pReg, const uint8_t *pdata, uint32_t cnt); 260 int HAL_UART_SerialIn(struct UART_REG *pReg, uint8_t *pdata, uint32_t cnt); 261 HAL_Status HAL_UART_HandleIrq(struct UART_REG *pReg); 262 void HAL_UART_Reset(struct UART_REG *pReg); 263 HAL_Status HAL_UART_Init(const struct HAL_UART_DEV *dev, const struct HAL_UART_CONFIG *config); 264 HAL_Status HAL_UART_DeInit(struct UART_REG *pReg); 265 HAL_Status HAL_UART_Suspend(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave); 266 HAL_Status HAL_UART_Resume(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave); 267 268 /** @} */ 269 270 #endif 271 272 /** @} */ 273 274 /** @} */ 275 276 #endif /* HAL_UART_MODULE_ENABLED */ 277