1 /**
2 * \file
3 *
4 * \brief SAM System related functionality
5 *
6 * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43 /*
44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
45 */
46
47 #include "system_sam_b.h"
48
49 uint32_t system_clock_value;
50
51 /**
52 * \brief System clock config
53 *
54 * Use this function to config system clock.
55 *
56 * \param[in] resoure Selection system clock resource
57 * \param[in] freq Selection clock frequency
58 *
59 * \return Status of operation.
60 * \retval STATUS_OK Clock config correctly
61 * \retval STATUS_ERR_INVALID_ARG If data is invalid
62 */
system_clock_config(enum system_clock_resource resoure,enum system_clock_freq freq)63 enum status_code system_clock_config(enum system_clock_resource resoure, \
64 enum system_clock_freq freq)
65 {
66 switch (resoure) {
67 case CLOCK_RESOURCE_XO_26_MHZ:
68 LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
69 LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK | \
70 LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK;
71 system_clock_value = 26000000;
72 break;
73
74 case CLOCK_RESOURCE_LP_2_MHZ:
75 LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
76 LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK;
77 LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
78 ~LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK;
79 AON_GP_REGS0->AON_PMU_CTRL.reg |= \
80 AON_GP_REGS_AON_PMU_CTRL_PMU_2MHZ_CLK_EN;
81 system_clock_value = 2000000;
82 break;
83
84 case CLOCK_RESOURCE_RC_26_MHZ:
85 LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
86 ~(LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK | \
87 LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK);
88 system_clock_value = 26000000;
89 break;
90
91 default:
92 return STATUS_ERR_INVALID_ARG;
93 }
94
95 LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
96 ~LPMCU_MISC_REGS_LPMCU_CTRL_LPMCU_CLK_SEL_Msk;
97 LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
98 LPMCU_MISC_REGS_LPMCU_CTRL_LPMCU_CLK_SEL(freq);
99
100 return STATUS_OK;
101 }
102
103 /**
104 * \brief Get the system clock value
105 *
106 * Use this function to get system clock value.
107 *
108 * \return system clock value.
109 */
system_clock_get_value(void)110 uint32_t system_clock_get_value(void)
111 {
112 return system_clock_value;
113 }
114
115 /**
116 * \brief System clock peripheral enable
117 *
118 * Use this function to enable system clock peripheral.
119 *
120 * \param[in] peripheral Selection peripheral
121 *
122 * \return Status of operation.
123 * \retval STATUS_OK Clock config correctly
124 * \retval STATUS_ERR_INVALID_ARG If data is invalid
125 */
system_clock_peripheral_enable(enum system_peripheral peripheral)126 enum status_code system_clock_peripheral_enable(enum system_peripheral peripheral)
127 {
128 switch (peripheral) {
129 case PERIPHERAL_SPI_FLASH:
130 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
131 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI_FLASH0_CLK_EN;
132 break;
133
134 case PERIPHERAL_SPI0_CORE:
135 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
136 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI0_CORE_CLK_EN;
137 break;
138
139 case PERIPHERAL_SPI1_CORE:
140 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
141 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI1_CORE_CLK_EN;
142 break;
143
144 case PERIPHERAL_I2C0_CORE:
145 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
146 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C0_CORE_CLK_EN;
147 break;
148
149 case PERIPHERAL_DUALT_TIMER:
150 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
151 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
152 break;
153
154 case PERIPHERAL_GPIO_CLK:
155 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
156 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_GPIO_CLK_EN;
157 break;
158
159 case PERIPHERAL_TIMER:
160 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
161 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_TIMER0_CLK_EN;
162 break;
163
164 case PERIPHERAL_WDT0:
165 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
166 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT0_CLK_EN;
167 break;
168
169 case PERIPHERAL_WDT1:
170 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
171 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT1_CLK_EN;
172 break;
173
174 case PERIPHERAL_UART0_CORE:
175 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
176 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_CORE_CLK_EN;
177 break;
178
179 case PERIPHERAL_UART0_IF:
180 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
181 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_IF_CLK_EN;
182 break;
183
184 case PERIPHERAL_UART1_CORE:
185 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
186 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_CORE_CLK_EN;
187 break;
188
189 case PERIPHERAL_UART1_IF:
190 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
191 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_IF_CLK_EN;
192 break;
193
194 case PERIPHERAL_NVIC:
195 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
196 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IRQ_CTRLR_CORE_CLK_EN;
197 break;
198
199 case PERIPHERAL_IDRAM1:
200 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
201 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_1_GL_MEM_CLK_EN;
202 break;
203
204 case PERIPHERAL_IDRAM2:
205 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
206 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_2_GL_MEM_CLK_EN;
207 break;
208
209 case PERIPHERAL_ROM:
210 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
211 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ROM_MEM_CLK_EN;
212 break;
213
214 case PERIPHERAL_LOW_POWER_IF:
215 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
216 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_XBAR_IF_CLK_EN;
217 break;
218
219 case PERIPHERAL_AON_WRAPPER:
220 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
221 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_AON_WRAPPER_CLK_EN;
222 break;
223
224 case PERIPHERAL_ARM_PCLK:
225 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
226 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLK_EN;
227 break;
228
229 case PERIPHERAL_ARM_GATED_PCLK:
230 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
231 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLKG_EN;
232 break;
233
234 case PERIPHERAL_ARM_BLE:
235 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
236 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_BLE_MEM_CLK_EN;
237 break;
238
239 case PERIPHERAL_QDEC0:
240 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
241 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
242 break;
243
244 case PERIPHERAL_QDEC1:
245 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
246 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
247 break;
248
249 case PERIPHERAL_QDEC2:
250 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
251 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
252 break;
253
254 case PERIPHERAL_I2C1_CORE:
255 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
256 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C1_CORE_CLK_EN;
257 break;
258
259 case PERIPHERAL_LOW_POWER_CORE:
260 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
261 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_CLK_EN;
262 break;
263
264 case PERIPHERAL_EFUSE1:
265 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
266 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE0_CLK_EN;
267 break;
268
269 case PERIPHERAL_EFUSE2:
270 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
271 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE1_CLK_EN;
272 break;
273
274 case PERIPHERAL_EFUSE3:
275 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
276 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE2_CLK_EN;
277 break;
278
279 case PERIPHERAL_EFUSE4:
280 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
281 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE3_CLK_EN;
282 break;
283
284 case PERIPHERAL_EFUSE5:
285 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
286 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE4_CLK_EN;
287 break;
288
289 case PERIPHERAL_EFUSE6:
290 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
291 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE5_CLK_EN;
292 break;
293
294 case PERIPHERAL_PWM0:
295 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
296 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM0_CLK_EN;
297 break;
298
299 case PERIPHERAL_PWM1:
300 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
301 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM1_CLK_EN;
302 break;
303
304 case PERIPHERAL_PWM2:
305 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
306 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM2_CLK_EN;
307 break;
308
309 case PERIPHERAL_PWM3:
310 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
311 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM3_CLK_EN;
312 break;
313
314 case PERIPHERAL_ADC:
315 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
316 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SENS_ADC_CLK_EN;
317 break;
318
319 case PERIPHERAL_SPI0_SCK_PHASE:
320 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
321 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI0_SCK_PHASE_INT_CLK_EN;
322 break;
323
324 case PERIPHERAL_SPI1_SCK_PHASE:
325 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
326 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI1_SCK_PHASE_INT_CLK_EN;
327 break;
328
329 case PERIPHERAL_GPIO_GCLK:
330 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
331 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_GPIO_GCLK_EN;
332 break;
333
334 case PERIPHERAL_TIMER0_GATE:
335 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
336 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_TIMER0_PGCLK_EN;
337 break;
338
339 case PERIPHERAL_SHA_CORE:
340 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
341 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_CORE_CLK_EN;
342 break;
343
344 case PERIPHERAL_SHA_AHB:
345 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
346 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_AHB_CLK_EN;
347 break;
348
349 case PERIPHERAL_AES_CORE:
350 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
351 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_CORE_CLK_EN;
352 break;
353
354 case PERIPHERAL_AES_AHB:
355 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
356 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_AHB_CLK_EN;
357 break;
358
359 case PERIPHERAL_IDRAM1_0:
360 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
361 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_0_MEM_CLK_EN;
362 break;
363
364 case PERIPHERAL_IDRAM1_1:
365 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
366 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_1_MEM_CLK_EN;
367 break;
368
369 case PERIPHERAL_IDRAM1_2:
370 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
371 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_2_MEM_CLK_EN;
372 break;
373
374 case PERIPHERAL_IDRAM2_0:
375 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
376 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_0_MEM_CLK_EN;
377 break;
378
379 case PERIPHERAL_IDRAM2_1:
380 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
381 LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_1_MEM_CLK_EN;
382 break;
383
384 case PERIPHERAL_BLE_RXTX:
385 LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
386 LPMCU_MISC_REGS_BTMCU_CTRL_RXTX_SEQ_CLK_EN;
387 break;
388
389 case PERIPHERAL_BLE_AHB:
390 LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
391 LPMCU_MISC_REGS_BTMCU_CTRL_AHB_CLK_EN;
392 break;
393
394 case PERIPHERAL_BLE_PERIPH_REGS:
395 LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
396 LPMCU_MISC_REGS_BTMCU_CTRL_PERIPH_REGS_CLK_EN;
397 break;
398
399 default:
400 return STATUS_ERR_INVALID_ARG;
401 }
402
403 return STATUS_OK;
404 }
405
406 /**
407 * \brief System clock peripheral disable
408 *
409 * Use this function to disable system clock peripheral.
410 *
411 * \param[in] peripheral Selection peripheral
412 *
413 * \return Status of operation.
414 * \retval STATUS_OK Clock config correctly
415 * \retval STATUS_ERR_INVALID_ARG If data is invalid
416 */
system_clock_peripheral_disable(enum system_peripheral peripheral)417 enum status_code system_clock_peripheral_disable(enum system_peripheral peripheral)
418 {
419 switch (peripheral) {
420 case PERIPHERAL_SPI_FLASH:
421 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
422 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI_FLASH0_CLK_EN;
423 break;
424
425 case PERIPHERAL_SPI0_CORE:
426 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
427 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI0_CORE_CLK_EN;
428 break;
429
430 case PERIPHERAL_SPI1_CORE:
431 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
432 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI1_CORE_CLK_EN;
433 break;
434
435 case PERIPHERAL_I2C0_CORE:
436 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
437 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C0_CORE_CLK_EN;
438 break;
439
440 case PERIPHERAL_DUALT_TIMER:
441 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
442 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
443 break;
444
445 case PERIPHERAL_GPIO_CLK:
446 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
447 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_GPIO_CLK_EN;
448 break;
449
450 case PERIPHERAL_TIMER:
451 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
452 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_TIMER0_CLK_EN;
453 break;
454
455 case PERIPHERAL_WDT0:
456 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
457 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT0_CLK_EN;
458 break;
459
460 case PERIPHERAL_WDT1:
461 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
462 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT1_CLK_EN;
463 break;
464
465 case PERIPHERAL_UART0_CORE:
466 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
467 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_CORE_CLK_EN;
468 break;
469
470 case PERIPHERAL_UART0_IF:
471 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
472 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_IF_CLK_EN;
473 break;
474
475 case PERIPHERAL_UART1_CORE:
476 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
477 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_CORE_CLK_EN;
478 break;
479
480 case PERIPHERAL_UART1_IF:
481 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
482 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_IF_CLK_EN;
483 break;
484
485 case PERIPHERAL_NVIC:
486 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
487 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IRQ_CTRLR_CORE_CLK_EN;
488 break;
489
490 case PERIPHERAL_IDRAM1:
491 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
492 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_1_GL_MEM_CLK_EN;
493 break;
494
495 case PERIPHERAL_IDRAM2:
496 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
497 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_2_GL_MEM_CLK_EN;
498 break;
499
500 case PERIPHERAL_ROM:
501 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
502 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ROM_MEM_CLK_EN;
503 break;
504
505 case PERIPHERAL_LOW_POWER_IF:
506 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
507 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_XBAR_IF_CLK_EN;
508 break;
509
510 case PERIPHERAL_AON_WRAPPER:
511 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
512 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_AON_WRAPPER_CLK_EN;
513 break;
514
515 case PERIPHERAL_ARM_PCLK:
516 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
517 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLK_EN;
518 break;
519
520 case PERIPHERAL_ARM_GATED_PCLK:
521 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
522 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLKG_EN;
523 break;
524
525 case PERIPHERAL_ARM_BLE:
526 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
527 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_BLE_MEM_CLK_EN;
528 break;
529
530 case PERIPHERAL_QDEC0:
531 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
532 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
533 break;
534
535 case PERIPHERAL_QDEC1:
536 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
537 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
538 break;
539
540 case PERIPHERAL_QDEC2:
541 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
542 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
543 break;
544
545 case PERIPHERAL_I2C1_CORE:
546 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
547 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C1_CORE_CLK_EN;
548 break;
549
550 case PERIPHERAL_LOW_POWER_CORE:
551 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
552 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_CLK_EN;
553 break;
554
555 case PERIPHERAL_EFUSE1:
556 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
557 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE0_CLK_EN;
558 break;
559
560 case PERIPHERAL_EFUSE2:
561 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
562 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE1_CLK_EN;
563 break;
564
565 case PERIPHERAL_EFUSE3:
566 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
567 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE2_CLK_EN;
568 break;
569
570 case PERIPHERAL_EFUSE4:
571 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
572 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE3_CLK_EN;
573 break;
574
575 case PERIPHERAL_EFUSE5:
576 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
577 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE4_CLK_EN;
578 break;
579
580 case PERIPHERAL_EFUSE6:
581 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
582 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE5_CLK_EN;
583 break;
584
585 case PERIPHERAL_PWM0:
586 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
587 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM0_CLK_EN;
588 break;
589
590 case PERIPHERAL_PWM1:
591 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
592 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM1_CLK_EN;
593 break;
594
595 case PERIPHERAL_PWM2:
596 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
597 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM2_CLK_EN;
598 break;
599
600 case PERIPHERAL_PWM3:
601 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
602 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM3_CLK_EN;
603 break;
604
605 case PERIPHERAL_ADC:
606 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
607 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SENS_ADC_CLK_EN;
608 break;
609
610 case PERIPHERAL_SPI0_SCK_PHASE:
611 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
612 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI0_SCK_PHASE_INT_CLK_EN;
613 break;
614
615 case PERIPHERAL_SPI1_SCK_PHASE:
616 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
617 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI1_SCK_PHASE_INT_CLK_EN;
618 break;
619
620 case PERIPHERAL_GPIO_GCLK:
621 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
622 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_GPIO_GCLK_EN;
623 break;
624
625 case PERIPHERAL_TIMER0_GATE:
626 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
627 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_TIMER0_PGCLK_EN;
628 break;
629
630 case PERIPHERAL_SHA_CORE:
631 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
632 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_CORE_CLK_EN;
633 break;
634
635 case PERIPHERAL_SHA_AHB:
636 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
637 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_AHB_CLK_EN;
638 break;
639
640 case PERIPHERAL_AES_CORE:
641 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
642 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_CORE_CLK_EN;
643 break;
644
645 case PERIPHERAL_AES_AHB:
646 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
647 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_AHB_CLK_EN;
648 break;
649
650 case PERIPHERAL_IDRAM1_0:
651 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
652 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_0_MEM_CLK_EN;
653 break;
654
655 case PERIPHERAL_IDRAM1_1:
656 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
657 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_1_MEM_CLK_EN;
658 break;
659
660 case PERIPHERAL_IDRAM1_2:
661 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
662 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_2_MEM_CLK_EN;
663 break;
664
665 case PERIPHERAL_IDRAM2_0:
666 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
667 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_0_MEM_CLK_EN;
668 break;
669
670 case PERIPHERAL_IDRAM2_1:
671 LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
672 ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_1_MEM_CLK_EN;
673 break;
674
675 case PERIPHERAL_BLE_RXTX:
676 LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
677 ~LPMCU_MISC_REGS_BTMCU_CTRL_RXTX_SEQ_CLK_EN;
678 break;
679
680 case PERIPHERAL_BLE_AHB:
681 LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
682 ~LPMCU_MISC_REGS_BTMCU_CTRL_AHB_CLK_EN;
683 break;
684
685 case PERIPHERAL_BLE_PERIPH_REGS:
686 LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
687 ~LPMCU_MISC_REGS_BTMCU_CTRL_PERIPH_REGS_CLK_EN;
688 break;
689
690 default:
691 return STATUS_ERR_INVALID_ARG;
692 }
693
694 return STATUS_OK;
695 }
696
697 /**
698 * \brief System clock peripheral frequency config
699 *
700 * Use this function to config system clock peripheral frequency.
701 *
702 * \param[in] peripheral Selection peripheral
703 * \param[in] freq Selection clock frequency
704 *
705 * \return Status of operation.
706 * \retval STATUS_OK Clock config correctly
707 * \retval STATUS_ERR_INVALID_ARG If data is invalid
708 */
system_clock_peripheral_freq_config(enum system_peripheral peripheral,enum system_clock_freq freq)709 enum status_code system_clock_peripheral_freq_config( \
710 enum system_peripheral peripheral, \
711 enum system_clock_freq freq)
712 {
713 switch (peripheral) {
714 case PERIPHERAL_SPI_FLASH:
715 LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
716 ~LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_Msk;
717 switch (freq) {
718 case CLOCK_FREQ_26_MHZ:
719 LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
720 LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_3;
721 break;
722 case CLOCK_FREQ_13_MHZ:
723 LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
724 LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_2;
725 break;
726 case CLOCK_FREQ_6_5_MHZ:
727 LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
728 LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_1;
729 break;
730 case CLOCK_FREQ_3_25_MHZ:
731 LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
732 LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_0;
733 break;
734 }
735 break;
736
737 case PERIPHERAL_DUALT_TIMER:
738 LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
739 ~LPMCU_MISC_REGS_LPMCU_CTRL_DUALTIMER0_CLK_SEL_Msk;
740 LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
741 LPMCU_MISC_REGS_LPMCU_CTRL_DUALTIMER0_CLK_SEL(freq);
742 break;
743
744 case PERIPHERAL_PWM0:
745 LPMCU_MISC_REGS0->PWM0_CTRL.reg &= \
746 ~LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL_Msk;
747 LPMCU_MISC_REGS0->PWM0_CTRL.reg |= \
748 LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL(freq);
749 break;
750
751 case PERIPHERAL_PWM1:
752 LPMCU_MISC_REGS0->PWM1_CTRL.reg &= \
753 ~LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL_Msk;
754 LPMCU_MISC_REGS0->PWM1_CTRL.reg |= \
755 LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL(freq);
756 break;
757
758 case PERIPHERAL_PWM2:
759 LPMCU_MISC_REGS0->PWM2_CTRL.reg &= \
760 ~LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL_Msk;
761 LPMCU_MISC_REGS0->PWM2_CTRL.reg |= \
762 LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL(freq);
763 break;
764
765 case PERIPHERAL_PWM3:
766 LPMCU_MISC_REGS0->PWM3_CTRL.reg &= \
767 ~LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL_Msk;
768 LPMCU_MISC_REGS0->PWM3_CTRL.reg |= \
769 LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL(freq);
770 break;
771
772 case PERIPHERAL_QDEC0:
773 LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg &= \
774 ~LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLOCK_SEL_Msk;
775 LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |= \
776 LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLOCK_SEL(freq);
777 break;
778
779 case PERIPHERAL_QDEC1:
780 LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg &= \
781 ~LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLOCK_SEL_Msk;
782 LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |= \
783 LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLOCK_SEL(freq);
784 break;
785
786 case PERIPHERAL_QDEC2:
787 LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg &= \
788 ~LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLOCK_SEL_Msk;
789 LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |= \
790 LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLOCK_SEL(freq);
791 break;
792
793 default:
794 return STATUS_ERR_INVALID_ARG;
795 }
796
797 return STATUS_OK;
798 }
799
800 /**
801 * \brief System global reset
802 *
803 * Use this function to reset system global.
804 *
805 */
system_global_reset(void)806 void system_global_reset(void)
807 {
808 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
809 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GLOBAL_RSTN;
810 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
811 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GLOBAL_RSTN;
812 };
813
814 /**
815 * \brief System peripheral reset
816 *
817 * Use this function to reset system peripheral.
818 *
819 * \param[in] peripheral Selection peripheral
820 *
821 * \return Status of operation.
822 * \retval STATUS_OK Clock config correctly
823 * \retval STATUS_ERR_INVALID_ARG If data is invalid
824 */
system_peripheral_reset(enum system_peripheral peripheral)825 enum status_code system_peripheral_reset(enum system_peripheral peripheral)
826 {
827 switch (peripheral) {
828 case PERIPHERAL_LPMCU_CPU:
829 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
830 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CPU_RSTN;
831 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
832 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CPU_RSTN;
833 break;
834
835 case PERIPHERAL_SPI_FLASH:
836 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
837 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_SYS_RSTN;
838 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
839 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_SYS_RSTN;
840 break;
841
842 case PERIPHERAL_SPI_FLASH_IF:
843 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
844 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_RSTN;
845 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
846 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_RSTN;
847 break;
848
849 case PERIPHERAL_SPI0_CORE:
850 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
851 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_CORE_RSTN;
852 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
853 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_CORE_RSTN;
854 break;
855
856 case PERIPHERAL_SPI0_IF:
857 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
858 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_IF_RSTN;
859 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
860 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_IF_RSTN;
861 break;
862
863 case PERIPHERAL_SPI1_CORE:
864 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
865 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_CORE_RESETN;
866 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
867 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_CORE_RESETN;
868 break;
869
870 case PERIPHERAL_SPI1_IF:
871 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
872 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_IF_RSTN;
873 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
874 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_IF_RSTN;
875 break;
876
877 case PERIPHERAL_I2C0_CORE:
878 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
879 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_CORE_RSTN;
880 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
881 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_CORE_RSTN;
882 break;
883
884 case PERIPHERAL_I2C0_IF:
885 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
886 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_IF_RSTN;
887 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
888 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_IF_RSTN;
889 break;
890
891 case PERIPHERAL_GPIO_CLK:
892 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
893 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GPIO_RSTN;
894 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
895 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GPIO_RSTN;
896 break;
897
898 case PERIPHERAL_TIMER:
899 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
900 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_TIMER0_RSTN;
901 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
902 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_TIMER0_RSTN;
903 break;
904
905 case PERIPHERAL_UART0_CORE:
906 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
907 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_CORE_RSTN;
908 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
909 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_CORE_RSTN;
910 break;
911
912 case PERIPHERAL_UART0_IF:
913 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
914 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_IF_RSTN;
915 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
916 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_IF_RSTN;
917 break;
918
919 case PERIPHERAL_UART1_CORE:
920 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
921 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_CORE_RSTN;
922 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
923 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_CORE_RSTN;
924 break;
925
926 case PERIPHERAL_UART1_IF:
927 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
928 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_IF_RSTN;
929 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
930 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_IF_RSTN;
931 break;
932
933 case PERIPHERAL_WDT0:
934 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
935 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT0_RSTN;
936 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
937 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT0_RSTN;
938 break;
939
940 case PERIPHERAL_WDT1:
941 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
942 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT1_RSTN;
943 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
944 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT1_RSTN;
945 break;
946
947 case PERIPHERAL_NVIC:
948 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
949 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_IRQ_CTRLR_CORE_RSTN;
950 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
951 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_IRQ_CTRLR_CORE_RSTN;
952 break;
953
954 case PERIPHERAL_MBIST:
955 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
956 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_MBIST_RSTN;
957 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
958 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_MBIST_RSTN;
959 break;
960
961 case PERIPHERAL_LOW_POWER_CORE:
962 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
963 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_RSTN;
964 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
965 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_RSTN;
966 break;
967
968 case PERIPHERAL_LOW_POWER_APB:
969 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
970 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_XBAR_IF_RSTN;
971 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
972 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_XBAR_IF_RSTN;
973 break;
974
975 case PERIPHERAL_LPMCU_DEBUG:
976 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
977 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_DBUG_RSTN;
978 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
979 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_DBUG_RSTN;
980 break;
981
982 case PERIPHERAL_ARM_FREE_CLK:
983 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
984 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_FREE_CLK_RSTN;
985 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
986 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_FREE_CLK_RSTN;
987 break;
988
989 case PERIPHERAL_ARM_APB:
990 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
991 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_PRESETN_RSTN;
992 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
993 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_PRESETN_RSTN;
994 break;
995
996 case PERIPHERAL_QDEC0:
997 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
998 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC0_RSTN;
999 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
1000 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC0_RSTN;
1001 break;
1002
1003 case PERIPHERAL_QDEC1:
1004 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
1005 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC1_RSTN;
1006 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
1007 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC1_RSTN;
1008 break;
1009
1010 case PERIPHERAL_QDEC2:
1011 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
1012 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC2_RSTN;
1013 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
1014 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC2_RSTN;
1015 break;
1016
1017 case PERIPHERAL_PWM0:
1018 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
1019 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM0_RSTN;
1020 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
1021 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM0_RSTN;
1022 break;
1023
1024 case PERIPHERAL_PWM1:
1025 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
1026 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM1_RSTN;
1027 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
1028 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM1_RSTN;
1029 break;
1030
1031 case PERIPHERAL_PWM2:
1032 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
1033 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM2_RSTN;
1034 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
1035 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM2_RSTN;
1036 break;
1037
1038 case PERIPHERAL_PWM3:
1039 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
1040 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM3_RSTN;
1041 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
1042 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM3_RSTN;
1043 break;
1044
1045 case PERIPHERAL_DUALT_TIMER:
1046 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1047 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_DUALTIMER0_RSTN;
1048 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1049 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_DUALTIMER0_RSTN;
1050 break;
1051
1052 case PERIPHERAL_I2C1_CORE:
1053 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1054 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_CORE_RSTN;
1055 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1056 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_CORE_RSTN;
1057 break;
1058
1059 case PERIPHERAL_I2C1_IF:
1060 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1061 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_IF_RSTN;
1062 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1063 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_IF_RSTN;
1064 break;
1065
1066 case PERIPHERAL_SHA_CORE:
1067 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1068 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_CORE_RSTN;
1069 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1070 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_CORE_RSTN;
1071 break;
1072
1073 case PERIPHERAL_SHA_AHB:
1074 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1075 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_AHB_RSTN;
1076 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1077 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_AHB_RSTN;
1078 break;
1079
1080 case PERIPHERAL_AES_CORE:
1081 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1082 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_CORE_RSTN;
1083 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1084 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_CORE_RSTN;
1085 break;
1086
1087 case PERIPHERAL_AES_AHB:
1088 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1089 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_AHB_RSTN;
1090 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1091 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_AHB_RSTN;
1092 break;
1093
1094 case PERIPHERAL_SPI0_SCK_CLK:
1095 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1096 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_CLK_RSTN;
1097 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1098 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_CLK_RSTN;
1099 break;
1100
1101 case PERIPHERAL_SPI1_SCK_CLK:
1102 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1103 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_CLK_RSTN;
1104 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1105 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_CLK_RSTN;
1106 break;
1107
1108 case PERIPHERAL_SPI0_SCK_PHASE:
1109 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1110 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_PHASE_INT_CLK_RSTN;
1111 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1112 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_PHASE_INT_CLK_RSTN;
1113 break;
1114
1115 case PERIPHERAL_SPI1_SCK_PHASE:
1116 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1117 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_PHASE_INT_CLK_RSTN;
1118 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1119 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_PHASE_INT_CLK_RSTN;
1120 break;
1121
1122 case PERIPHERAL_DMA:
1123 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
1124 ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_PROV_DMA_CTRL0_RSTN;
1125 LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
1126 LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_PROV_DMA_CTRL0_RSTN;
1127 break;
1128
1129 default:
1130 return STATUS_ERR_INVALID_ARG;
1131 }
1132
1133 return STATUS_OK;
1134 }
1135
1136 /**
1137 * \brief Register the ISR
1138 *
1139 * Use this function to register a ISR to the RAM table.
1140 *
1141 * \param[in] isr_index Index of the ISR
1142 * \param[in] isr_address Address of the ISR
1143 *
1144 */
system_register_isr(enum ram_isr_table_index isr_index,uint32_t isr_address)1145 void system_register_isr(enum ram_isr_table_index isr_index,
1146 uint32_t isr_address)
1147 {
1148 uint32_t *temp;
1149 temp = (uint32_t *)(isr_index * 4 + ISR_RAM_MAP_START_ADDRESS);
1150 *temp = isr_address;
1151 }
1152
1153 /**
1154 * \brief Unregister the ISR
1155 *
1156 * Use this function to unregister a ISR to the RAM table.
1157 *
1158 * \param[in] isr_index Index of the ISR
1159 *
1160 */
system_unregister_isr(enum ram_isr_table_index isr_index)1161 void system_unregister_isr(enum ram_isr_table_index isr_index)
1162 {
1163 uint32_t *temp;
1164 temp = (uint32_t *)(isr_index * 4 + ISR_RAM_MAP_START_ADDRESS);
1165 *temp = 0;
1166 }
1167
1168 /**
1169 * \brief Initializes an system calibration configuration structure to default values
1170 *
1171 * This function will initialize a given system calibration configuration
1172 * structure to a set of known default values. This function should be called
1173 * on any new instance of the configuration structures before being modified by
1174 * the user application.
1175 *
1176 * \param[out] config Configuration structure to initialize to default values
1177 */
system_calibration_get_config_defaults(struct system_calibration_config * config)1178 void system_calibration_get_config_defaults(struct system_calibration_config *config)
1179 {
1180 config->clk_num = CALIBRATION_CLK_NUM_1024;
1181 config->interrupt_control = CALIBRATION_INTERRUPT_OSC_DONE;
1182 config->osc_fractional_part = 0;
1183 config->osc_integer_part = 0;
1184 config->rtc_fractional_part = 0;
1185 config->rtc_integer_part = 0;
1186 }
1187
1188 /**
1189 * \brief System calibration set configuration
1190 *
1191 * Use this function to set system calibration configuration.
1192 *
1193 * \param[in] config Point to struct system_calibration_config
1194 *
1195 */
system_calibration_set_config(struct system_calibration_config * config)1196 void system_calibration_set_config(struct system_calibration_config *config)
1197 {
1198 Assert(config);
1199
1200 LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
1201 ~(LP_CLK_CAL_REGS_CONFIG_REG_NUMBER_CALIB_CLKS_Msk | \
1202 LP_CLK_CAL_REGS_CONFIG_REG_IRQ_CONTROL_Msk);
1203 LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
1204 LP_CLK_CAL_REGS_CONFIG_REG_NUMBER_CALIB_CLKS(config->clk_num) | \
1205 LP_CLK_CAL_REGS_CONFIG_REG_IRQ_CONTROL(config->interrupt_control);
1206 }
1207
1208 /**
1209 * \brief System calibration get interrupt status
1210 *
1211 * Use this function to get system calibration interrupt status.
1212 *
1213 * \param[in] config Point to struct system_calibration_config
1214 *
1215 * \return Status of operation.
1216 * \retval CALBRATION_NO_IN_PROGRESS No calibration in progress
1217 * \retval CALBRATION_IN_PROGRESS Calibration in progress
1218 * \retval CALBRATION_DONE Calibration done
1219 */
system_calibration_get_interrupt_status(struct system_calibration_config * config)1220 enum system_calibration_status system_calibration_get_interrupt_status( \
1221 struct system_calibration_config *config)
1222 {
1223 switch (config->interrupt_control) {
1224 case CALIBRATION_INTERRUPT_OSC_DONE:
1225 if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING) {
1226 return CALBRATION_IN_PROGRESS;
1227 } else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE) {
1228 return CALBRATION_DONE;
1229 }
1230 break;
1231 case CALIBRATION_INTERRUPT_RTC_DONE:
1232 if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING) {
1233 return CALBRATION_IN_PROGRESS;
1234 } else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
1235 return CALBRATION_DONE;
1236 }
1237 break;
1238 case CALIBRATION_INTERRUPT_OSC_OR_RTC_DONE:
1239 if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE || \
1240 LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
1241 return CALBRATION_DONE;
1242 } else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING || \
1243 LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING){
1244 return CALBRATION_IN_PROGRESS;
1245 }
1246 break;
1247 case CALIBRATION_INTERRUPT_OSC_AND_RTC_DONE:
1248 if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE && \
1249 LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
1250 return CALBRATION_DONE;
1251 } else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING || \
1252 LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING){
1253 return CALBRATION_IN_PROGRESS;
1254 }
1255 break;
1256
1257 default:
1258 return CALBRATION_NO_IN_PROGRESS;
1259 }
1260
1261 return CALBRATION_NO_IN_PROGRESS;
1262 }
1263
1264 /**
1265 * \brief System calibration osc enable
1266 *
1267 * Use this function to able system calibration osc.
1268 */
system_osc_calibration_enable(void)1269 void system_osc_calibration_enable(void)
1270 {
1271 LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
1272 LP_CLK_CAL_REGS_CONFIG_REG_START_OSC_CALIB;
1273 }
1274
1275 /**
1276 * \brief System calibration osc disable
1277 *
1278 * Use this function to disable system calibration osc.
1279 */
system_osc_calibration_disable(void)1280 void system_osc_calibration_disable(void)
1281 {
1282 LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
1283 ~LP_CLK_CAL_REGS_CONFIG_REG_START_OSC_CALIB;
1284 }
1285
1286 /**
1287 * \brief System calibration osc get status
1288 *
1289 * Use this function to get system calibration osc status.
1290 *
1291 * \param[in] config Point to struct system_calibration_config
1292 *
1293 * \return Status of operation.
1294 * \retval CALBRATION_NO_IN_PROGRESS No calibration in progress
1295 * \retval CALBRATION_IN_PROGRESS Calibration in progress
1296 * \retval CALBRATION_DONE Calibration done
1297 */
system_osc_calibration_get_status(void)1298 enum system_calibration_status system_osc_calibration_get_status(void)
1299 {
1300 if (LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.NO_CAL_IN_PROGRESS) {
1301 return CALBRATION_NO_IN_PROGRESS;
1302 } else if (LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_DONE) {
1303 return CALBRATION_DONE;
1304 } else {
1305 return CALBRATION_IN_PROGRESS;
1306 }
1307 }
1308
1309 /**
1310 * \brief System calibration osc clear status
1311 *
1312 * Use this function to clear system calibration osc status.
1313 */
system_osc_calibration_clear_status(void)1314 void system_osc_calibration_clear_status(void)
1315 {
1316 //LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.reg = 0x01;
1317 }
1318
1319 /**
1320 * \brief System calibration osc get results
1321 *
1322 * Use this function to get system calibration osc results.
1323 *
1324 * \param[in,out] config Point to struct system_calibration_config
1325 */
system_osc_calibration_result(struct system_calibration_config * config)1326 void system_osc_calibration_result(struct system_calibration_config *config)
1327 {
1328 config->osc_fractional_part = LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_FRAC_COUNT;
1329 config->osc_integer_part = LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_INT_COUNT;
1330 }
1331
1332 /**
1333 * \brief System calibration rtc enable
1334 *
1335 * Use this function to able system calibration rtc.
1336 */
system_rtc_calibration_enable(void)1337 void system_rtc_calibration_enable(void)
1338 {
1339 LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
1340 LP_CLK_CAL_REGS_CONFIG_REG_START_RTC_CALIB;
1341 }
1342
1343 /**
1344 * \brief System calibration rtc disable
1345 *
1346 * Use this function to disable system calibration rtc.
1347 */
system_rtc_calibration_disable(void)1348 void system_rtc_calibration_disable(void)
1349 {
1350 LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
1351 ~LP_CLK_CAL_REGS_CONFIG_REG_START_RTC_CALIB;
1352 }
1353
1354 /**
1355 * \brief System calibration rtc get status
1356 *
1357 * Use this function to get system calibration rtc status.
1358 *
1359 * \param[in] config Point to struct system_calibration_config
1360 *
1361 * \return Status of operation.
1362 * \retval CALBRATION_NO_IN_PROGRESS No calibration in progress
1363 * \retval CALBRATION_IN_PROGRESS Calibration in progress
1364 * \retval CALBRATION_DONE Calibration done
1365 */
system_rtc_calibration_get_status(void)1366 enum system_calibration_status system_rtc_calibration_get_status(void)
1367 {
1368 if (LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.NO_CAL_IN_PROGRESS) {
1369 return CALBRATION_NO_IN_PROGRESS;
1370 } else if (LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_DONE) {
1371 return CALBRATION_DONE;
1372 } else {
1373 return CALBRATION_IN_PROGRESS;
1374 }
1375 }
1376
1377 /**
1378 * \brief System calibration rtc clear status
1379 *
1380 * Use this function to clear system calibration rtc status.
1381 */
system_rtc_calibration_clear_status(void)1382 void system_rtc_calibration_clear_status(void)
1383 {
1384 //LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.reg = 0x01;
1385 }
1386
1387 /**
1388 * \brief System calibration rtc get results
1389 *
1390 * Use this function to get system calibration rtc results.
1391 *
1392 * \param[in,out] config Point to struct system_calibration_config
1393 */
system_rtc_calibration_result(struct system_calibration_config * config)1394 void system_rtc_calibration_result(struct system_calibration_config *config)
1395 {
1396 config->rtc_fractional_part = LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_FRAC_COUNT;
1397 config->rtc_integer_part = LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_INT_COUNT;
1398 }
1399
1400 /**
1401 * \brief System clock aon config
1402 *
1403 * Use this function to config system clock aon.
1404 *
1405 * \param[in] peripheral_aon Selection system peripheral aon
1406 * \param[in] aon_resource Selection system clock aon resource
1407 *
1408 * \return Status of operation.
1409 * \retval STATUS_OK Clock config correctly
1410 * \retval STATUS_ERR_INVALID_ARG If data is invalid
1411 */
system_clock_aon_config(enum system_peripheral_aon peripheral_aon,enum system_clock_aon_resource aon_resource)1412 enum status_code system_clock_aon_config( \
1413 enum system_peripheral_aon peripheral_aon, \
1414 enum system_clock_aon_resource aon_resource)
1415 {
1416 switch (peripheral_aon) {
1417 case PERIPHERAL_AON_SLEEP_TIMER:
1418 if (aon_resource == CLOCK_AON_RESOURCE_31_25_KHZ) {
1419 AON_GP_REGS0->AON_MISC_CTRL.reg |= \
1420 AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
1421 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1422 ~AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
1423 } else if (aon_resource == CLOCK_AON_RESOURCE_32_768_KHZ) {
1424 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1425 ~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
1426 AON_GP_REGS0->AON_MISC_CTRL.reg |= \
1427 AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
1428 } else if (aon_resource == CLOCK_AON_DEFAULT) {
1429 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1430 ~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
1431 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1432 ~AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
1433 }
1434 break;
1435
1436 case PERIPHERAL_AON_POWER_SEQUENCER:
1437 if (aon_resource == CLOCK_AON_RESOURCE_2_MHZ) {
1438 AON_GP_REGS0->AON_MISC_CTRL.reg |= \
1439 AON_GP_REGS_AON_MISC_CTRL_USE_RTC_AON_PWR_SEQ_CLK;
1440 AON_GP_REGS0->AON_MISC_CTRL.reg |= \
1441 AON_GP_REGS_AON_MISC_CTRL_USE_2M_AON_PWR_SEQ_CLK;
1442 } else if (aon_resource == CLOCK_AON_DEFAULT) {
1443 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1444 ~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_AON_PWR_SEQ_CLK;
1445 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1446 ~AON_GP_REGS_AON_MISC_CTRL_USE_2M_AON_PWR_SEQ_CLK;
1447 }
1448 break;
1449
1450 case PERIPHERAL_AON_PD:
1451 if (aon_resource == CLOCK_AON_RESOURCE_2_MHZ) {
1452 AON_GP_REGS0->AON_MISC_CTRL.reg |= \
1453 AON_GP_REGS_AON_MISC_CTRL_USE_OSC2M_AS_TB_CLK;
1454 } else if (aon_resource == CLOCK_AON_DEFAULT) {
1455 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1456 ~AON_GP_REGS_AON_MISC_CTRL_USE_OSC2M_AS_TB_CLK;
1457 }
1458
1459 default:
1460 return STATUS_ERR_INVALID_ARG;
1461 }
1462 return STATUS_OK;
1463 }
1464
1465 /**
1466 * \brief System clock peripheral aon enable
1467 *
1468 * Use this function to enable system clock peripheral aon.
1469 *
1470 * \param[in] peripheral_aon Selection peripheral
1471 *
1472 * \return Status of operation.
1473 * \retval STATUS_OK Clock config correctly
1474 * \retval STATUS_ERR_INVALID_ARG If data is invalid
1475 */
system_clock_peripheral_aon_enable(enum system_peripheral_aon peripheral_aon)1476 enum status_code system_clock_peripheral_aon_enable(enum system_peripheral_aon peripheral_aon)
1477 {
1478 switch (peripheral_aon) {
1479 case PERIPHERAL_AON_SLEEP_TIMER:
1480 AON_GP_REGS0->AON_MISC_CTRL.reg |= \
1481 AON_GP_REGS_AON_MISC_CTRL_AON_SLEEP_TIMER_CLK_EN;
1482 break;
1483
1484 case PERIPHERAL_AON_PD:
1485 AON_GP_REGS0->AON_MISC_CTRL.reg |= \
1486 AON_GP_REGS_AON_MISC_CTRL_AON_EXT_32KHZ_OUT_EN;
1487 break;
1488
1489 default:
1490 return STATUS_ERR_INVALID_ARG;
1491 }
1492 return STATUS_OK;
1493 }
1494
1495 /**
1496 * \brief System clock peripheral aon disable
1497 *
1498 * Use this function to enable system clock peripheral aon.
1499 *
1500 * \param[in] peripheral_aon Selection peripheral
1501 *
1502 * \return Status of operation.
1503 * \retval STATUS_OK Clock config correctly
1504 * \retval STATUS_ERR_INVALID_ARG If data is invalid
1505 */
system_clock_peripheral_aon_disable(enum system_peripheral_aon peripheral_aon)1506 enum status_code system_clock_peripheral_aon_disable(enum system_peripheral_aon peripheral_aon)
1507 {
1508 switch (peripheral_aon) {
1509 case PERIPHERAL_AON_SLEEP_TIMER:
1510 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1511 ~AON_GP_REGS_AON_MISC_CTRL_AON_SLEEP_TIMER_CLK_EN;
1512 break;
1513
1514 case PERIPHERAL_AON_PD:
1515 AON_GP_REGS0->AON_MISC_CTRL.reg &= \
1516 ~AON_GP_REGS_AON_MISC_CTRL_AON_EXT_32KHZ_OUT_EN;
1517 break;
1518
1519 default:
1520 return STATUS_ERR_INVALID_ARG;
1521 }
1522 return STATUS_OK;
1523 }
1524