1 /* 2 * =========================================================================================== 3 * 4 * Filename: sunxi_hal_spi.h 5 * 6 * Description: SPI HAL definition. 7 * 8 * Version: Melis3.0 9 * Create: 2020-04-08 11:11:56 10 * Revision: none 11 * Compiler: GCC:version 9.2.1 12 * 13 * Author: bantao@allwinnertech.com 14 * Organization: SWC-BPD 15 * Last Modified: 2020-04-08 16:02:11 16 * 17 * =========================================================================================== 18 */ 19 20 #ifndef _CIR_H_ 21 #define _CIR_H_ 22 23 #include "hal_clk.h" 24 #include "hal_reset.h" 25 26 #ifdef __cplusplus 27 extern "C" 28 { 29 #endif 30 31 /* Registers */ 32 #define CIR_CTRL (0x00) /* IR Control */ 33 #define CIR_RXCTRL (0x10) /* Rx Config */ 34 #define CIR_RXFIFO (0x20) /* Rx Data */ 35 #define CIR_RXINT (0x2C) /* Rx Interrupt Enable */ 36 #define CIR_RXSTA (0x30) /* Rx Interrupt Status */ 37 #define CIR_CONFIG (0x34) /* IR Sample Config */ 38 39 /*CIR_CTRL*/ 40 #define GEN_OFFSET 0 41 #define RXEN_OFFSET 1 42 #define CIR_ENABLE_OFFSET 4 43 #define CIR_MODE_OFFSET 6 44 /*global enable*/ 45 #define GEN (0x01 << GEN_OFFSET) 46 /*receiver block enable*/ 47 #define RXEN (0x01 << RXEN_OFFSET) 48 /*cir enable*/ 49 #define CIR_ENABLE (0x03 << CIR_ENABLE_OFFSET) 50 /*active pulse accept mode*/ 51 #define CIR_MODE (0x03 << CIR_MODE_OFFSET) 52 53 /*CIR_RXCTRL*/ 54 #define RPPI_OFFSET 2 55 #define RPPI (0x01 << RPPI_OFFSET) /*receiver pulse polarity invert*/ 56 57 /*CIR_RXINT*/ 58 #define ROI_EN_OFFSET 0 59 #define PREI_EN_OFFSET 1 60 #define RAI_EN_OFFSET 4 61 #define DRQ_EN_OFFSET 5 62 #define RAL_OFFSET 8 63 /*receiver fifo overrun interrupt enable*/ 64 #define ROI_EN (0x01 << ROI_EN_OFFSET) 65 /*receiver packet end interrupt enable*/ 66 #define PREI_EN (0x01 << PREI_EN_OFFSET) 67 /*rx fifo available interrupt enable*/ 68 #define RAI_EN (0x01 << RAI_EN_OFFSET) 69 /*rx fifo dma enable*/ 70 #define DRQ_EN (0x01 << DRQ_EN_OFFSET) 71 /*rx fifo available received byte level*/ 72 #define RAL (0x3f << RAL_OFFSET) 73 #define IRQ_MASK (0x3f) 74 75 /*CIR_RXSTA*/ 76 #define ROI_OFFSET 0 77 #define RPE_OFFSET 1 78 #define RA_OFFSET 4 79 #define STAT_OFFSET 7 80 #define RAC_OFFSET 8 81 #define ROI (0x01 << ROI_OFFSET) /*receiver fifo overrun*/ 82 #define RPE (0x01 << RPE_OFFSET) /*receiver packet end reg*/ 83 #define RA (0x01 << RA_OFFSET) /*rx fifo available*/ 84 #define STAT (0x01 << STAT_OFFSET) /*status of cir, 0:idle, 1:busy*/ 85 #define RAC (0x7f << RAC_OFFSET) /*rx fifo available counter*/ 86 87 /*CIR_CONFIG*/ 88 #define SCS_OFFSET 0 89 #define NTHR_OFFSET 2 90 #define ITHR_OFFSET 8 91 #define ATHR_OFFSET 16 92 #define ATHC_OFFSET 23 93 #define SCS2_OFFSET 24 94 #define SCS (0x03 << SCS_OFFSET) /*sample clk select for cir*/ 95 #define NTHR (0x3f << NTHR_OFFSET) /*noise threshold for cir*/ 96 #define ITHR (0xff << ITHR_OFFSET) /*idle threshold for cir*/ 97 #define ATHR (0x7f << ATHR_OFFSET) /*active threshold for cir*/ 98 #define ATHC (0x01 << ATHC_OFFSET) /*active threshold control for cir*/ 99 #define SCS2 (0x01 << SCS2_OFFSET) /*bit2 of sample clock select for cir*/ 100 101 #define CIR_NOISE_THR_NEC 32 102 #define CIR_NOISE_THR_RC5 22 103 104 typedef enum { 105 CIR_MASTER_0 = 0, 106 CIR_MASTER_NUM, 107 } cir_port_t; 108 109 typedef enum { 110 CIR_BOTH_PULSE = 0x01, /*both positive and negative pulses*/ 111 CIR_LOW_PULSE = 0x02, /*only negative pulse*/ 112 CIR_HIGH_PULSE = 0x03, /*only positive pulse*/ 113 } cir_mode_t; 114 115 typedef enum { 116 CIR_PIN_ERR = -4, 117 CIR_CLK_ERR = -3, 118 CIR_IRQ_ERR = -2, 119 CIR_PORT_ERR = -1, 120 CIR_OK = 0, 121 } cir_status_t; 122 123 typedef enum { 124 CIR_CLK_DIV64 = 0x0, 125 CIR_CLK_DIV128 = 0x01, 126 CIR_CLK_DIV256 = 0x02, 127 CIR_CLK_DIV512 = 0x03, 128 CIR_CLK = 0x04, 129 } cir_sample_clock_t; 130 131 typedef struct { 132 uint32_t gpio; 133 uint8_t enable_mux; 134 uint8_t disable_mux; 135 } cir_gpio_t; 136 137 typedef struct { 138 uint32_t bus_clk; 139 uint32_t mclk; 140 uint32_t pclk; 141 } cir_clk_t; 142 143 typedef int (*cir_callback_t)(cir_port_t port, uint32_t data_type, uint32_t data); 144 145 typedef struct { 146 cir_port_t port; 147 unsigned long base; 148 uint32_t irq; 149 cir_clk_t *clk; 150 cir_gpio_t *pin; 151 cir_callback_t callback; 152 uint8_t status; 153 154 hal_clk_t bclk; 155 hal_clk_t pclk; 156 hal_clk_t mclk; 157 hal_clk_t test_clk; 158 159 hal_clk_id_t m_clk_id; 160 hal_clk_id_t p_clk_id; 161 hal_clk_id_t b_clk_id; 162 hal_clk_id_t test_clk_id; 163 164 hal_clk_type_t cir_clk_type_R; 165 hal_clk_type_t cir_clk_type_FIXED; 166 hal_clk_type_t test_clk_type; 167 168 struct reset_control *cir_reset; 169 } sunxi_cir_t; 170 171 void sunxi_cir_callback_register(cir_port_t port, cir_callback_t callback); 172 void sunxi_cir_mode_enable(cir_port_t port, uint8_t enable); 173 void sunxi_cir_mode_config(cir_port_t port, cir_mode_t mode); 174 void sunxi_cir_sample_clock_select(cir_port_t port, cir_sample_clock_t div); 175 void sunxi_cir_sample_noise_threshold(cir_port_t port, int8_t threshold); 176 void sunxi_cir_sample_idle_threshold(cir_port_t port, int8_t threshold); 177 void sunxi_cir_sample_active_threshold(cir_port_t port, int8_t threshold); 178 void sunxi_cir_sample_active_thrctrl(cir_port_t port, int8_t enable); 179 void sunxi_cir_fifo_level(cir_port_t port, int8_t size); 180 void sunxi_cir_irq_enable(cir_port_t port, int enable); 181 void sunxi_cir_irq_disable(cir_port_t port); 182 void sunxi_cir_signal_invert(cir_port_t port, uint8_t invert); 183 void sunxi_cir_module_enable(cir_port_t port, int8_t enable); 184 cir_status_t sunxi_cir_init(cir_port_t port); 185 void sunxi_cir_deinit(cir_port_t port); 186 #ifdef CONFIG_STANDBY 187 void sunxi_cir_suspend(cir_port_t port); 188 void sunxi_cir_resume(cir_port_t port); 189 #endif 190 191 #ifdef __cplusplus 192 } 193 #endif 194 195 #endif 196