1 /***************************************************************************//** 2 * @file ald_qspi.h 3 * @brief Header file of QSPI module driver. 4 * @version V1.0 5 * @date 09 Nov 2019 6 * @author AE Team 7 * @note 8 * Change Logs: 9 * Date Author Notes 10 * 09 Nov 2019 AE Team The first version 11 * 12 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 13 * 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the License); you may 17 * not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 ********************************************************************************** 28 */ 29 30 #ifndef __ALD_QSPI_H_ 31 #define __ALD_QSPI_H_ 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #include "utils.h" 38 #include "ald_dma.h" 39 40 /** @addtogroup ES32FXXX_ALD 41 * @{ 42 */ 43 44 /** @addtogroup QSPI 45 * @{ 46 */ 47 /** @defgroup QSPI_Public_Types QSPI Public Types 48 * @{ 49 */ 50 /** 51 * @brief ALD QSPI state 52 */ 53 typedef enum { 54 QSPI_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ 55 QSPI_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ 56 } qspi_state_t; 57 58 /** 59 * @brief QSPI Instruction Transfer Type 60 */ 61 typedef enum { 62 QSPI_XFER_SINGLE = 0x00U, /**< Instruction shifted on DQ0 only*/ 63 QSPI_XFER_DUAL = 0x01U, /**< Instruction,Address and data sent on DQ0 and DQ1*/ 64 QSPI_XFER_QUAD = 0x02U, /**< Instruction,Address and data sent on DQ0,DQ1 and DQ2*/ 65 } qspi_xfer_t; 66 67 /** 68 * @brief QSPI Indirect Access SRAM fill level 69 */ 70 typedef enum { 71 QSPI_SRAM_RD = 0U, /**< SRAM fill level(indirect write partition)in units of words(4bytes)*/ 72 QSPI_SRAM_WR = 1U, /**< SRAM fill level(indirect read partition)in units of words(4bytes)*/ 73 } qspi_sram_t; 74 75 /** 76 * @brief QSPI Clock Phase 77 */ 78 typedef enum { 79 QSPI_CPHA_1E = 0U, /**< First edge*/ 80 QSPI_CPHA_2E = 1U, /**< Second edge*/ 81 } qspi_cpha_t; 82 83 /** 84 * @brief QSPI_Clock_Polarity QSPI Clock Polarity 85 */ 86 typedef enum { 87 QSPI_CPOL_L = 0U, /**< QSPI clock polarity low */ 88 QSPI_CPOL_H = 1U, /**< QSPI clock polarity high */ 89 } qspi_cpol_t; 90 91 /** 92 * @brief QSPI peripheral select decode 93 */ 94 typedef enum { 95 QSPI_SINGLE_CHIP = 0x0U, /**< Only 1 of 4 selects n_ss_out[3:0] is active */ 96 QSPI_MULTI_CHIP = 0x1U, /**< Allow external 4-to-16 decode */ 97 } qspi_nss_decode_t; 98 99 /** 100 * @brief QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler 101 */ 102 typedef enum { 103 QSPI_DIV_2 = 0x0U, /**< Master mode baud rate dibisor 2*/ 104 QSPI_DIV_4 = 0x1U, /**< Master mode baud rate dibisor 4*/ 105 QSPI_DIV_6 = 0x2U, /**< Master mode baud rate dibisor 6*/ 106 QSPI_DIV_8 = 0x3U, /**< Master mode baud rate dibisor 8*/ 107 QSPI_DIV_10 = 0x4U, /**< Master mode baud rate dibisor 10*/ 108 QSPI_DIV_12 = 0x5U, /**< Master mode baud rate dibisor 12*/ 109 QSPI_DIV_14 = 0x6U, /**< Master mode baud rate dibisor 14*/ 110 QSPI_DIV_16 = 0x7U, /**< Master mode baud rate dibisor 16*/ 111 QSPI_DIV_18 = 0x8U, /**< Master mode baud rate dibisor 18*/ 112 QSPI_DIV_20 = 0x9U, /**< Master mode baud rate dibisor 20*/ 113 QSPI_DIV_22 = 0xAU, /**< Master mode baud rate dibisor 22*/ 114 QSPI_DIV_24 = 0xBU, /**< Master mode baud rate dibisor 24*/ 115 QSPI_DIV_26 = 0xCU, /**< Master mode baud rate dibisor 26*/ 116 QSPI_DIV_28 = 0xDU, /**< Master mode baud rate dibisor 28*/ 117 QSPI_DIV_30 = 0xEU, /**< Master mode baud rate dibisor 30*/ 118 QSPI_DIV_32 = 0xFU, /**< Master mode baud rate dibisor 32*/ 119 } qspi_clk_div_t; 120 121 /** 122 * @brief QSPI Peripheral chip select decode 123 */ 124 typedef enum { 125 QSPI_CS_NSS0 = 0x0U, /**< NSS0 active*/ 126 QSPI_CS_NSS1 = 0x1U, /**< NSS1 active*/ 127 QSPI_CS_NSS2 = 0x3U, /**< NSS2 active*/ 128 QSPI_CS_NSS3 = 0x7U, /**< NSS3 active*/ 129 } qspi_nss_t; 130 131 /** 132 *@brief Size of flash connected to CS[x](x = 0 ~ 3)pin 133 */ 134 typedef enum { 135 QSPI_NSS_512M = 0x0U, /**< size of 512Mb*/ 136 QSPI_NSS_1G = 0x1U, /**< size of 1Gb*/ 137 QSPI_NSS_2G = 0x2U, /**< size of 2Gb*/ 138 QSPI_NSS_4G = 0x3U, /**< size of 3Gb*/ 139 } qspi_nss_size_t; 140 141 /** 142 *@brief Qspi external flash device configuration 143 */ 144 typedef struct { 145 uint8_t addr; /**< Peripheral address */ 146 uint16_t page; /**< Flash page size */ 147 uint16_t blk; /**< Flash block size */ 148 qspi_nss_size_t cs0; /**< NSS0 flash size */ 149 qspi_nss_size_t cs1; /**< NSS1 flash size */ 150 qspi_nss_size_t cs2; /**< NSS2 flash size */ 151 qspi_nss_size_t cs3; /**< NSS3 flash size */ 152 } qspi_device_size_t; 153 154 /** 155 * @brief QSPI Sample Edge Selection 156 */ 157 typedef enum { 158 QSPI_FALLING_E = 0x0U, /**< Data outputs from flash are sampled on falling edge of the ref_clk*/ 159 QSPI_RISING_E = 0x1U, /**< Data outputs from flash are sampled on rising edge of the ref_clk*/ 160 } qspi_data_sampled_t; 161 162 /** 163 * @brief Flash write-protected blocks configuration. 164 */ 165 typedef struct { 166 uint32_t lowblk; /**< the lower block in the range of blocks that is to be locked from writing*/ 167 uint32_t upblk; /**< upper block in the range of blocks that is to be locked from writing*/ 168 } qspi_wr_protect_t; 169 170 /** 171 * @brief QSPI STIG Command Structure. 172 */ 173 typedef struct { 174 uint32_t code; /**< command op-code*/ 175 uint32_t rd_len; /**< Number of Read Data Bytes*/ 176 uint32_t addr_len; /**< Number of Address Bytes*/ 177 uint32_t wr_len; /**< Number of Write Data Bytes*/ 178 uint32_t d_sycle; /**< Number of dummy cycles*/ 179 type_func_t mode_bit; /**< Mode Bit Configuration register are sent following the address bytes*/ 180 type_func_t op_addr; /**< If opcde requires an address*/ 181 uint32_t val; /**< Mode bits,sent to device following the address*/ 182 uint32_t addr; /**< Flash opcde address*/ 183 void *rd_buf; /**< Buffer for read data*/ 184 void *wr_buf; /**< Buffer with data to write*/ 185 } qspi_stig_cmd_t; 186 187 /** 188 * @brief QSPI base initialization structure. 189 */ 190 typedef struct { 191 qspi_clk_div_t clkdiv; /**< QSPI Baud Rate Clock Prescaler*/ 192 type_func_t wrppin; /**< QSPI Set Write Protect Pin*/ 193 qspi_nss_decode_t nssdcode; /**< QSPI Peripheral Select Decode*/ 194 qspi_nss_t chipsel; /**< QSPI Peripheral Select Line*/ 195 qspi_cpol_t cpol; /**< QSPI polarity */ 196 qspi_cpha_t chpa; /**< QSPI phase */ 197 } qspi_init_t; 198 199 /** 200 * @brief QSPI legacy initialization structure. 201 */ 202 typedef struct { 203 uint8_t tx_thrd; /**< Tx FIFO threshhold */ 204 uint8_t rx_thrd; /**< Rx FIFO threshhold */ 205 } qspi_legacy_cfg_t; 206 207 /** 208 * @brief QSPI Device Read Instruction Configuration structure. 209 */ 210 typedef struct { 211 uint8_t rdcde; /**< Read opcode in non-xip mode*/ 212 uint8_t dcyles; /**< Number of dummy read clock cycles*/ 213 uint8_t mbitval; /**< Mode bits,sent to device following the address bytes*/ 214 type_func_t ddrbit; /**< Opcode from bit 7 to 0 is compliant with DDR command*/ 215 type_func_t modebit; /**< Enable mode bit*/ 216 qspi_xfer_t addxfer; /**< Transfer type used for address*/ 217 qspi_xfer_t datxfer; /**< Transfer type used for data*/ 218 qspi_xfer_t instxfer; /**< Transfer type used for instruction*/ 219 } qspi_read_cfg_t; 220 221 /** 222 * @brief QSPI Device Write Instruction Configuration structure. 223 */ 224 typedef struct { 225 uint8_t wrcde; /**< Write opcode*/ 226 uint8_t dcyles; /**< Number of dummy read clock cycles*/ 227 qspi_xfer_t addxfer; /**< Transfer type used for address*/ 228 qspi_xfer_t datxfer; /**< Transfer type used for data*/ 229 qspi_xfer_t instxfer; /**< Transfer type used for instruction*/ 230 type_func_t autowel; /**< Turn off automatic*/ 231 } qspi_write_cfg_t; 232 233 /** 234 * @brief QSPI Indirect Configuration structure.involatile parameters 235 */ 236 typedef struct { 237 uint32_t saddr; /**< Flash start address, commence write operation*/ 238 uint32_t wrlen; /**< Number of indirect write bytes*/ 239 } qspi_indac_wr_cfg_t; 240 241 typedef struct { 242 uint32_t saddr; /**< FLASH start address, commence read operation*/ 243 uint32_t rdlen; /**< Number of indirect read bytes*/ 244 } qspi_indac_rd_cfg_t; 245 246 typedef struct { 247 uint32_t srampt; /**< Defines the size of the indirect read partion in the SRAM*/ 248 uint32_t trgaddr; /**< Indirect trigger address which is used by AHB controller*/ 249 uint32_t trgrng; /**< The offset of indirect trigger address*/ 250 uint32_t wrwmark; /**< Maximum fill level of SRAM before a DMA, 0xFFFFFFFF disable the function*/ 251 uint32_t rdwmark; /**< Fill level passes watermark, an interrupt generated*/ 252 } qspi_indac_cfg_t; 253 254 /** 255 * @brief QSPI DAC configuration. 256 */ 257 typedef struct { 258 type_func_t dtrprtcol; /**< DTR protocol*/ 259 type_func_t ahbdecoder; /**< AHB decoder, direct access mode only*/ 260 type_func_t xipimmed; /**< QSPI Enter XIP Immediately*/ 261 type_func_t xipnextrd; /**< QSPI Enter XIP Next Read*/ 262 type_func_t addrremap; /**< Enable AHB address re-mapping*/ 263 uint32_t remapaddr; /**< Remap incoming AHB address to different address*/ 264 type_func_t dmaperh; /**< QSPI dma interface*/ 265 qspi_read_cfg_t rdinit; /**< QSPI read instruction configuration*/ 266 qspi_write_cfg_t wrinit; /**< QSPI write instruction configuration*/ 267 } qspi_dac_cfg_t; 268 269 /** 270 * @brief QSPI Handle Structure definition 271 */ 272 typedef struct { 273 QSPI_TypeDef *perh; /**< QSPI registers base address*/ 274 qspi_init_t init; /**< QSPI communication parameters*/ 275 uint8_t *tx_buf; /**< Pointer to QSPI transfer buffer */ 276 uint16_t tx_size; /**< QSPI transfer size */ 277 uint16_t tx_cnt; /**< QSPI transfer counter */ 278 uint8_t *rx_buf; /**< Pointer to QSPI receive buffer */ 279 uint16_t rx_size; /**< QSPI receive size */ 280 uint16_t rx_cnt; /**< QSPI receive counter */ 281 282 dma_handle_t hdma; /**< QSPI Rx/Tx DMA Handle parameters*/ 283 284 qspi_state_t state; /**< QSPI communication state */ 285 __IO lock_state_t lock; /**< Locking object*/ 286 } qspi_handle_t; 287 288 /** 289 * @brief Defines command to be executed using STIG mechanism. 290 */ 291 typedef struct { 292 uint32_t ccsot; /**< range [0 ~ 255]*/ 293 uint32_t cseot; /**< range [0 ~ 255]*/ 294 uint32_t csdads; /**< range [0 ~ 255]*/ 295 uint32_t csda; /**< range [0 ~ 255]*/ 296 } qspi_dly_cfg_t; 297 298 /** 299 * @brief QSPI Read Data Capture Configuration. 300 */ 301 typedef struct { 302 uint32_t dlytd; /**< Delay transmitted data [0 ~ 15]*/ 303 uint32_t dlydcl; /**< Delay the read data capturing logic [0 ~ 15]*/ 304 qspi_data_sampled_t smpledge; /**< Sample edge selection(of the flash data outputs) @ref qspi_data_sampled_t*/ 305 } qspi_data_capture_cfg_t; 306 307 /** 308 * @brief QSPI Indirect Write Progress Status. 309 */ 310 typedef enum { 311 QSPI_INDWR_PROGRESS = (1U << 2), /**< Indirect write operation in progress*/ 312 QSPI_INDWR_CPLT = (1U << 5), /**< Indirect write completion*/ 313 } qspi_indwr_status_t; 314 315 /** 316 * @brief QSPI Indirect Read Progress Status. 317 */ 318 typedef enum { 319 QSPI_INDRD_PROGRESS = (1U << 2), /**< Indirect read operation in progress*/ 320 QSPI_RD_CPLT = (1U << 5), /**< Indirect read completion*/ 321 } qspi_indrd_flag_t; 322 323 /** 324 * @brief QSPI Auto Poll Configuration Struction. 325 */ 326 typedef struct { 327 uint32_t opcode; /**< Automatically poll operation code */ 328 uint32_t indx; /**< Polling bit index */ 329 uint32_t polarity; /**< Defines polling polarity */ 330 uint32_t validcnt; /**< Expect true result times */ 331 uint32_t repdly; /**< Defines additional delay for maintain de-assert during auto-polling phase */ 332 uint32_t polexpcnt; /**< Poll cycles,which polling expiration interrupt is generated*/ 333 } qspi_auto_poll_t; 334 335 /** 336 *@brief QSPI_Interrupt_definition QSPI Interrupt Definition 337 */ 338 typedef enum { 339 QSPI_IT_POLLF = (1U << 13), /**< Programmed polls cycles expired flag */ 340 QSPI_IT_INDRSFF = (1U << 12), /**< Indirect read partition of SRAM is full flag */ 341 QSPI_IT_SRFFF = (1U << 11), /**< Small rx FIFO full flag */ 342 QSPI_IT_SRFNEF = (1U << 10), /**< Small rx FIFO not empty flag */ 343 QSPI_IT_STFFF = (1U << 9), /**< Small tx FIFO full flag */ 344 QSPI_IT_STFNFF = (1U << 8), /**< Small tx FIFO not full flag */ 345 QSPI_IT_ROVF = (1U << 7), /**< Receive overflow flag */ 346 QSPI_IT_INDTWF = (1U << 6), /**< Indirect transfer watermark level breached flag */ 347 QSPI_IT_AHBAEF = (1U << 5), /**< Illegal AHB access detected flag */ 348 QSPI_IT_WPAF = (1U << 4), /**< Write to protected area was rejected flag */ 349 QSPI_IT_INDRRF = (1U << 3), /**< Indirect operation could not be accepted flag */ 350 QSPI_IT_INDCF = (1U << 2), /**< Controller has completed last triggered indirect operation flag */ 351 QSPI_IT_UDFF = (1U << 1), /**< Underflow detected flag */ 352 QSPI_IT_MODFF = (1U << 0), /**< Mode fail M flag */ 353 } qspi_it_t; 354 /** 355 * @brief QSPI_Flag_definition QSPI Flag Definition 356 */ 357 typedef enum { 358 QSPI_IF_POLLF = (1U << 13), /**< Programmed polls cycles expired flag */ 359 QSPI_IF_INDRSFF = (1U << 12), /**< Indirect read partition of SRAM is full flag */ 360 QSPI_IF_SRFFF = (1U << 11), /**< Small rx FIFO full flag */ 361 QSPI_IF_SRFNEF = (1U << 10), /**< Small rx FIFO not empty flag */ 362 QSPI_IF_STFFF = (1U << 9), /**< Small tx FIFO full flag */ 363 QSPI_IF_STFNFF = (1U << 8), /**< Small tx FIFO not full flag */ 364 QSPI_IF_ROVF = (1U << 7), /**< Receive overflow flag */ 365 QSPI_IF_INDTWF = (1U << 6), /**< Indirect transfer watermark level breached flag */ 366 QSPI_IF_AHBAEF = (1U << 5), /**< Illegal AHB access detected flag */ 367 QSPI_IF_WPAF = (1U << 4), /**< Write to protected area was rejected flag */ 368 QSPI_IF_INDRRF = (1U << 3), /**< Indirect operation could not be accepted flag */ 369 QSPI_IF_INDCF = (1U << 2), /**< Controller has completed last triggered indirect operation flag */ 370 QSPI_IF_UDFF = (1U << 1), /**< Underflow detected flag */ 371 QSPI_IF_MODFF = (1U << 0), /**< Mode fail M flag */ 372 } qspi_flag_t; 373 /** 374 * @} 375 */ 376 377 /** @defgroup QSPI_Private_Macros QSPI Private Macros 378 * @{ 379 */ 380 #define IS_QSPI_SRAM_PARTITION(x) ((x) < 255) 381 #define IS_QSPI_INDIRECT_TRIGGER_RANGE(x) (((x) < 16)) 382 #define IS_QSPI_INDIRECT_READ_WATERMARK(x) ((x) < 512) 383 #define IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x) (((x) == QSPI_SRAM_RD) || ((x) == QSPI_SRAM_WR)) 384 #define IS_QSPI_INDIRECT_READ_STATUS(x) (((x) == QSPI_INDRD_PROGRESS) || ((x) == QSPI_RD_CPLT)) 385 #define IS_QSPI_INDIRECT_WRITE_STATUS(x) (((x) == QSPI_INDWR_PROGRESS) || ((x) == QSPI_INDWR_CPLT)) 386 #define IS_QSPI_DEVICE_DELAY_CCSOT(x) ((x) < 256) 387 #define IS_QSPI_DEVICE_DELAY_CSEOT(x) ((x) < 256) 388 #define IS_QSPI_DEVICE_DELAY_CSDADS(x) ((x) < 256) 389 #define IS_QSPI_DEVICE_DELAY_CSDA(x) ((x) < 256) 390 391 #define IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x) ((x) < 16) 392 #define IS_QSPI_READ_DATA_SAMPLE_EDGE(x) (((x) == QSPI_FALLING_E) || \ 393 ((x) == QSPI_RISING_E)) 394 #define IS_QSPI_READ_DATA_DELAY_TRANSMIT(x) ((x) < 16) 395 #define IS_QSPI_ALL(x) ((x) == QSPI) 396 #define IS_QSPI_DCYLES(x) ((x) <= 31) 397 398 #define IS_QSPI_ADDR_SIZE(x) ((x) <= 15) 399 #define IS_QSPI_PAGE_SIZE(x) ((x) <= 0xfff) 400 #define IS_QSPI_BLOCK_SIZE(x) ((x) <= 0x1f) 401 #define IS_QSPI_NSS_SIZE(x) ((x) <= 3) 402 403 #define IS_QSPI_XFER_TYPE(x) (((x) == QSPI_XFER_SINGLE) || \ 404 ((x) == QSPI_XFER_DUAL) || \ 405 ((x) == QSPI_XFER_QUAD)) 406 #define IS_QSPI_DDR_BIT_ENABLE(x) (((x) == QSPI_READ_DDR_BIT_DISABLE) || \ 407 ((x) == QSPI_READ_DDR_BIT_ENABLE)) 408 #define IS_QSPI_MODE_BIT_ENABLE(x) (((x) == QSPI_READ_INST_MODE_BIT_DISABLE) || \ 409 ((x) == QSPI_READ_INST_MODE_BIT_ENABLE)) 410 #define IS_QSPI_RD_OPCODE(x) (((x) < 0xFF)) 411 #define IS_QSPI_WR_OPCODE(x) (((x) < 0xFF)) 412 #define IS_QSPI_CLOCK_PRESCALER(x) (((x) == QSPI_DIV_2) || \ 413 ((x) == QSPI_DIV_4) || \ 414 ((x) == QSPI_DIV_6) || \ 415 ((x) == QSPI_DIV_8) || \ 416 ((x) == QSPI_DIV_10) || \ 417 ((x) == QSPI_DIV_12) || \ 418 ((x) == QSPI_DIV_14) || \ 419 ((x) == QSPI_DIV_16) || \ 420 ((x) == QSPI_DIV_18) || \ 421 ((x) == QSPI_DIV_20) || \ 422 ((x) == QSPI_DIV_22) || \ 423 ((x) == QSPI_DIV_24) || \ 424 ((x) == QSPI_DIV_26) || \ 425 ((x) == QSPI_DIV_28) || \ 426 ((x) == QSPI_DIV_30) || \ 427 ((x) == QSPI_DIV_32)) 428 #define IS_QSPI_CLOCK_PHASE(x) (((x) == QSPI_CPHA_1E) || \ 429 ((x) == QSPI_CPHA_2E)) 430 #define IS_QSPI_CLOCK_POLARITY(x) (((x) == QSPI_CPOL_L) || \ 431 ((x) == QSPI_CPOL_H)) 432 #define IS_QSPI_IF(x) (((x) == QSPI_IF_POLLF) || \ 433 ((x) == QSPI_IF_INDRSFF) || \ 434 ((x) == QSPI_IF_SRFFF) || \ 435 ((x) == QSPI_IF_SRFNEF) || \ 436 ((x) == QSPI_IF_STFFF) || \ 437 ((x) == QSPI_IF_STFNFF) || \ 438 ((x) == QSPI_IF_ROVF) || \ 439 ((x) == QSPI_IF_INDTWF) || \ 440 ((x) == QSPI_IF_AHBAEF) || \ 441 ((x) == QSPI_IF_WPAF) || \ 442 ((x) == QSPI_IF_INDRRF) || \ 443 ((x) == QSPI_IF_INDCF) || \ 444 ((x) == QSPI_IF_UDFF) || \ 445 ((x) == QSPI_IF_MODFF)) 446 #define IS_QSPI_IT(x) (((x) == QSPI_IT_POLLF) || \ 447 ((x) == QSPI_IT_INDRSFF) || \ 448 ((x) == QSPI_IT_SRFFF) || \ 449 ((x) == QSPI_IT_SRFNEF) || \ 450 ((x) == QSPI_IT_STFFF) || \ 451 ((x) == QSPI_IT_STFNFF) || \ 452 ((x) == QSPI_IT_ROVF) || \ 453 ((x) == QSPI_IT_INDTWF) || \ 454 ((x) == QSPI_IT_AHBAEF) || \ 455 ((x) == QSPI_IT_WPAF) || \ 456 ((x) == QSPI_IT_INDRRF) || \ 457 ((x) == QSPI_IT_INDCF) || \ 458 ((x) == QSPI_IT_UDFF) || \ 459 ((x) == QSPI_IT_MODFF)) 460 461 /** 462 * @} 463 */ 464 465 /** 466 * @defgroup QSPI_Public_Macros QSPI Public Macros 467 * @{ 468 */ 469 #define QSPI_MEMORY_ADDRESS 0x90000000U 470 #define QSPI_SRAM_SIZE 255U 471 #define QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5s */ 472 #define QSPI_SRAM_DEPTH 0xFFU 473 #define QSPI_DAC_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK) 474 #define QSPI_DAC_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK) 475 #define QSPI_LEGACY_SPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK) 476 #define QSPI_LEGACY_SPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK) 477 #define QSPI_WRITE_PROTECT_ENABLE(hperh) SET_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK); 478 #define QSPI_WRITE_PROTECT_DISABLE(hperh) CLEAR_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK); 479 #define QSPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK) 480 #define QSPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK) 481 #define QSPI_AUTO_POLL_ENABLE(hperh) CLEAR_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK) 482 #define QSPI_AUTO_POLL_DISABLE(hperh) SET_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK) 483 #define QSPI_DMA_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK) 484 #define QSPI_DMA_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK) 485 #define QSPI_CANCEL_INDIRECT_READ(hperh) SET_BIT((hperh)->perh->IRTR, QSPI_IRTR_RDDIS_MSK) 486 /** 487 * @} 488 */ 489 490 /** @addtogroup QSPI_Public_Functions 491 * @{ 492 */ 493 494 /** @addtogroup QSPI_Public_Functions_Group1 495 * @{ 496 */ 497 /* QSPI basic execution functions */ 498 void ald_qspi_init(qspi_handle_t *hperh); 499 uint32_t ald_qspi_dac_rd(uint32_t addr); 500 void ald_qspi_dac_wr(uint32_t addr, uint32_t dat); 501 ald_status_t ald_qspi_read_config(qspi_handle_t* hperh, const qspi_read_cfg_t * rdcfg); 502 ald_status_t ald_qspi_write_config(qspi_handle_t* hperh, const qspi_write_cfg_t * wrcfg); 503 ald_status_t ald_qspi_device_delay_config(qspi_handle_t * hperh, qspi_dly_cfg_t *dlycfg); 504 ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t * hperh, qspi_data_capture_cfg_t *dtcptcfg); 505 ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t * devcfg); 506 ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg); 507 /** 508 * @} 509 */ 510 /** @addtogroup QSPI_Public_Functions_Group2 511 * @{ 512 */ 513 /* QSPI indirect and stig access execution functions */ 514 ald_status_t ald_qspi_indac_config(qspi_handle_t * hperh, qspi_indac_cfg_t *indcfg); 515 ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size); 516 ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size); 517 ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size); 518 ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size); 519 ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t* hperh, const qspi_stig_cmd_t * scmd); 520 #ifdef ALD_DMA 521 ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size); 522 ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size); 523 #endif 524 /** 525 * @} 526 */ 527 /** @addtogroup QSPI_Public_Functions_Group3 528 * @{ 529 */ 530 /* QSPI status functions */ 531 flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag); 532 void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag); 533 uint16_t qspi_read_sram_fill_level(qspi_handle_t * hperh, qspi_sram_t srt); 534 void ald_qspi_write_proect_config(qspi_handle_t * hperh, qspi_wr_protect_t* wpcfg); 535 void ald_qspi_write_proect_inverse(qspi_handle_t * hperh, type_func_t state); 536 ald_status_t ald_qspi_auto_poll(qspi_handle_t *hperh, qspi_auto_poll_t* apcfg); 537 void ald_qspi_irq_handler(qspi_handle_t *hperh); 538 void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state); 539 void ald_qspi_legacy_config(qspi_handle_t* hperh, const qspi_legacy_cfg_t *config); 540 flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status); 541 ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout); 542 /** 543 * @} 544 */ 545 /** 546 * @} 547 */ 548 /** 549 * @} 550 */ 551 /** 552 * @} 553 */ 554 #ifdef __cplusplus 555 } 556 #endif 557 #endif /* __ALD_QSPI_H__ */ 558