1 /**************************************************************************//**
2 *
3 * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Change Logs:
8 * Date Author Notes
9 * 2020-11-11 Wayne First version
10 *
11 ******************************************************************************/
12
13 #include <rthw.h>
14 #include <rtthread.h>
15 #include "drv_sys.h"
16 #include <stdio.h>
17
18 #define LOG_TAG "drv.sys"
19 #undef DBG_ENABLE
20 #define DBG_SECTION_NAME LOG_TAG
21 #define DBG_LEVEL LOG_LVL_DBG
22 #define DBG_COLOR
23 #include <rtdbg.h>
24
25 #define DEF_RAISING_CPU_FREQUENCY
26 //Dont enable #define DEF_RAISING_CPU_VOLTAGE
27
machine_shutdown(void)28 void machine_shutdown(void)
29 {
30 rt_kprintf("machine_shutdown...\n");
31 rt_hw_interrupt_disable();
32
33 /* Unlock */
34 SYS_UnlockReg();
35
36 while (1);
37 }
38
machine_reset(void)39 void machine_reset(void)
40 {
41 rt_kprintf("machine_reset...\n");
42 rt_hw_interrupt_disable();
43
44 /* Unlock */
45 SYS_UnlockReg();
46
47 SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
48 SYS->IPRST0 = 0;
49 while (1);
50 }
51
reboot(int argc,char ** argv)52 int reboot(int argc, char **argv)
53 {
54 machine_reset();
55 return 0;
56 }
57 MSH_CMD_EXPORT(reboot, Reboot System);
58
59
nu_sys_ip_reset(uint32_t u32ModuleIndex)60 void nu_sys_ip_reset(uint32_t u32ModuleIndex)
61 {
62 SYS_ResetModule(u32ModuleIndex);
63 }
64
nu_sys_usb0_role(void)65 E_SYS_USB0_ID nu_sys_usb0_role(void)
66 {
67 #if 0
68 /* Check Role on USB0 dual-role port. */
69 /*
70 [17] USB0_IDS
71 USB0_ID Status
72 0 = USB port 0 used as a USB device port.
73 1 = USB port 0 used as a USB host port.
74 */
75 return ((inpw(REG_SYS_MISCISR) & (1 << 17)) > 0) ? USB0_ID_HOST : USB0_ID_DEVICE;
76 #else
77 return USB0_ID_DEVICE;
78 #endif
79 }
80
nu_sys_check_register(S_NU_REG * psNuReg)81 void nu_sys_check_register(S_NU_REG *psNuReg)
82 {
83 if (psNuReg == RT_NULL)
84 return;
85
86 while (psNuReg->vu32RegAddr != 0)
87 {
88 vu32 vc32RegValue = *((vu32 *)psNuReg->vu32RegAddr);
89 vu32 vc32BMValue = vc32RegValue & psNuReg->vu32BitMask;
90 LOG_I("[%3s] %32s(0x%08x) %24s(0x%08x): 0x%08x(AndBitMask:0x%08x)\n",
91 (psNuReg->vu32Value == vc32BMValue) ? "Ok" : "!OK",
92 psNuReg->szVName,
93 psNuReg->vu32Value,
94 psNuReg->szRegName,
95 psNuReg->vu32RegAddr,
96 vc32RegValue,
97 vc32BMValue);
98 psNuReg++;
99 }
100 }
101
nu_tempsen_init()102 static int nu_tempsen_init()
103 {
104 SYS->TSENSRFCR &= ~SYS_TSENSRFCR_PD_Msk; // Disable power down, don't wait, takes double conv time (350ms * 2)
105 return 0;
106 }
107
nu_tempsen_get_value()108 static int nu_tempsen_get_value()
109 {
110 char sztmp[32];
111 double temp;
112 static rt_tick_t _old_tick = 0;
113 static int32_t count = 0;
114
115 _old_tick = rt_tick_get();
116
117 // Wait valid bit set
118 while ((SYS->TSENSRFCR & SYS_TSENSRFCR_DATAVALID_Msk) == 0)
119 {
120 // 700 ms after clear pd bit. other conversion takes 350 ms
121 if (rt_tick_get() > (500 + _old_tick))
122 {
123 return -1;
124 }
125 }
126
127 if (++count == 8)
128 {
129 count = 0;
130 temp = (double)((SYS->TSENSRFCR & 0x0FFF0000) >> 16) * 274.3531 / 4096.0 - 93.3332;
131 snprintf(sztmp, sizeof(sztmp), "Temperature: %.1f\n", temp);
132 LOG_I("%s", sztmp);
133 }
134
135 // Clear Valid bit
136 SYS->TSENSRFCR = SYS_TSENSRFCR_DATAVALID_Msk;
137
138 return 0;
139 }
140
nu_tempsen_hook(void)141 void nu_tempsen_hook(void)
142 {
143 nu_tempsen_get_value();
144 }
145
nu_tempsen_go(void)146 static int nu_tempsen_go(void)
147 {
148 rt_err_t err = rt_thread_idle_sethook(nu_tempsen_hook);
149
150 if (err != RT_EOK)
151 {
152 LOG_E("set %s idle hook failed!\n", __func__);
153 return -1;
154 }
155
156 nu_tempsen_init();
157
158 return 0;
159 }
160 //INIT_APP_EXPORT(nu_tempsen_go);
161 MSH_CMD_EXPORT(nu_tempsen_go, go tempsen);
162
163 #define REG_SYS_CHIPCFG (SYS_BASE + 0x1F4)
164
nu_chipcfg_ddrsize(void)165 uint32_t nu_chipcfg_ddrsize(void)
166 {
167 uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG);
168
169 return ((u32ChipCfg & 0xF0000) != 0) ? (1 << ((u32ChipCfg & 0xF0000) >> 16)) << 20 : 0;
170 }
171
nu_chipcfg_dump(void)172 void nu_chipcfg_dump(void)
173 {
174 uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG);
175 uint32_t u32ChipCfg_DDRSize = ((u32ChipCfg & 0xF0000) != 0) ? 1 << ((u32ChipCfg & 0xF0000) >> 16) : 0;
176 uint32_t u32ChipCfg_DDRType = ((u32ChipCfg & 0x8000) >> 15);
177
178 LOG_I("CHIPCFG: 0x%08x ", u32ChipCfg);
179 LOG_I("DDR SDRAM Size: %d MB", u32ChipCfg_DDRSize);
180 LOG_I("MCP DDR TYPE: %s", u32ChipCfg_DDRSize ? (u32ChipCfg_DDRType ? "DDR2" : "DDR3/3L") : "Unknown");
181 }
182
nu_clock_dump(void)183 void nu_clock_dump(void)
184 {
185 LOG_I("HXT: %d Hz", CLK_GetHXTFreq());
186 LOG_I("LXT: %d Hz", CLK_GetLXTFreq());
187 LOG_I("CAPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(CAPLL), CLK_GetPLLOpMode(CAPLL));
188 LOG_I("DDRPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(DDRPLL), CLK_GetPLLOpMode(DDRPLL));
189 LOG_I("APLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(APLL), CLK_GetPLLOpMode(APLL));
190 LOG_I("EPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(EPLL), CLK_GetPLLOpMode(EPLL));
191 LOG_I("VPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(VPLL), CLK_GetPLLOpMode(VPLL));
192
193 LOG_I("M4-CPU: %d Hz", CLK_GetCPUFreq());
194 LOG_I("SYSCLK0: %d Hz", CLK_GetSYSCLK0Freq());
195 LOG_I("SYSCLK1: %d Hz", CLK_GetSYSCLK1Freq());
196 LOG_I("HCLK0: %d Hz", CLK_GetHCLK0Freq());
197 LOG_I("HCLK1: %d Hz", CLK_GetHCLK1Freq());
198 LOG_I("HCLK2: %d Hz", CLK_GetHCLK2Freq());
199 LOG_I("HCLK3: %d Hz", CLK_GetHCLK3Freq());
200 LOG_I("PCLK0: %d Hz", CLK_GetPCLK0Freq());
201 LOG_I("PCLK1: %d Hz", CLK_GetPCLK1Freq());
202 LOG_I("PCLK2: %d Hz", CLK_GetPCLK2Freq());
203 LOG_I("PCLK3: %d Hz", CLK_GetPCLK3Freq());
204 LOG_I("PCLK4: %d Hz", CLK_GetPCLK4Freq());
205 }
206
207 static const char *szClockName [] =
208 {
209 "HXT",
210 "LXT",
211 "N/A",
212 "LIRC",
213 "HIRC",
214 "N/A",
215 "CAPLL",
216 "N/A",
217 "DDRPLL",
218 "EPLL",
219 "APLL",
220 "VPLL"
221 };
222 #define CLOCKNAME_SIZE (sizeof(szClockName)/sizeof(char*))
223
nu_clock_isready(void)224 void nu_clock_isready(void)
225 {
226 uint32_t u32IsReady, i;
227 for (i = 0; i < CLOCKNAME_SIZE; i++)
228 {
229 if (i == 5 || i == 7 || i == 2) continue;
230 u32IsReady = CLK_WaitClockReady(1 << i);
231 LOG_I("%s: %s\n", szClockName[i], (u32IsReady == 1) ? "[Stable]" : "[Unstable]");
232 }
233 }
234
235 extern uint32_t ma35d1_set_cpu_voltage(uint32_t sys_clk, uint32_t u32Vol);
nu_clock_raise(void)236 void nu_clock_raise(void)
237 {
238 uint32_t u32PllRefClk;
239
240 /* Unlock protected registers */
241 SYS_UnlockReg();
242
243 /* Enable HXT, LXT */
244 CLK->PWRCTL |= (CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_HIRCEN_Msk);
245 if (CLK->STATUS & CLK_STATUS_HXTSTB_Msk) // Check Ready
246 {
247 u32PllRefClk = __HXT;
248 }
249 else if (CLK->STATUS & CLK_STATUS_HIRCSTB_Msk) // Check Ready
250 {
251 u32PllRefClk = __HIRC; // HXT_CHECK_FAIL
252 }
253 else
254 {
255 return;
256 }
257
258 CLK_SetPLLFreq(VPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 102000000ul);
259 CLK_SetPLLFreq(APLL, PLL_OPMODE_INTEGER, u32PllRefClk, 144000000ul);
260 CLK_SetPLLFreq(EPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 500000000ul);
261
262 /* Waiting clock ready */
263 CLK_WaitClockReady(CLK_STATUS_VPLLSTB_Msk | CLK_STATUS_APLLSTB_Msk | CLK_STATUS_EPLLSTB_Msk);
264
265 #if defined(DEF_RAISING_CPU_FREQUENCY)
266 /* Switch clock source of CA35 to DDRPLL before raising CA-PLL */
267 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_CA35CKSEL_Msk)) | CLK_CLKSEL0_CA35CKSEL_DDRPLL;
268 #if defined(DEF_RAISING_CPU_VOLTAGE)
269 if (ma35d1_set_cpu_voltage(CLK_GetPLLClockFreq(SYSPLL), 0x68))
270 {
271 CLK_SetPLLFreq(CAPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 1000000000ul);
272 }
273 else
274 #endif
275 {
276 #if defined(DEF_RAISING_CPU_VOLTAGE)
277 ma35d1_set_cpu_voltage(CLK_GetPLLClockFreq(SYSPLL), 0x5F);
278 #endif
279 CLK_SetPLLFreq(CAPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 800000000ul);
280 }
281
282 /* Waiting clock ready */
283 CLK_WaitClockReady(CLK_STATUS_CAPLLSTB_Msk);
284
285 /* Switch clock source of CA35 to CA-PLL after raising */
286 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_CA35CKSEL_Msk)) | CLK_CLKSEL0_CA35CKSEL_CAPLL;
287 #endif
288
289 }
290
291 #ifdef FINSH_USING_MSH
292 MSH_CMD_EXPORT(nu_clock_dump, Dump all clocks);
293 MSH_CMD_EXPORT(nu_clock_raise, Raise clock);
294 MSH_CMD_EXPORT(nu_clock_isready, Check PLL clocks);
295 #endif
296
297
devmem(int argc,char * argv[])298 void devmem(int argc, char *argv[])
299 {
300 volatile unsigned int u32Addr;
301 unsigned int value = 0, mode = 0;
302
303 if (argc < 2 || argc > 3)
304 {
305 goto exit_devmem;
306 }
307
308 if (argc == 3)
309 {
310 if (rt_sscanf(argv[2], "0x%x", &value) != 1)
311 goto exit_devmem;
312 mode = 1; //Write
313 }
314
315 if (rt_sscanf(argv[1], "0x%x", &u32Addr) != 1)
316 goto exit_devmem;
317 else if (u32Addr & (4 - 1))
318 goto exit_devmem;
319
320 if (mode)
321 {
322 *((volatile uint32_t *)u32Addr) = value;
323 }
324 LOG_I("0x%08x\n", *((volatile uint32_t *)u32Addr));
325
326 return;
327 exit_devmem:
328 rt_kprintf("Read: devmem <physical address in hex>\n");
329 rt_kprintf("Write: devmem <physical address in hex> <value in hex format>\n");
330 return;
331 }
332 MSH_CMD_EXPORT(devmem, dump device registers);
333
devmem2(int argc,char * argv[])334 void devmem2(int argc, char *argv[])
335 {
336 volatile unsigned int u32Addr;
337 unsigned int value = 0, word_count = 1;
338
339 if (argc < 2 || argc > 3)
340 {
341 goto exit_devmem;
342 }
343
344 if (argc == 3)
345 {
346 if (rt_sscanf(argv[2], "%d", &value) != 1)
347 goto exit_devmem;
348 word_count = value;
349 }
350
351 if (rt_sscanf(argv[1], "0x%x", &u32Addr) != 1)
352 goto exit_devmem;
353 else if (u32Addr & (4 - 1))
354 goto exit_devmem;
355
356 if (word_count > 0)
357 {
358 LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t));
359 }
360
361 return;
362
363 exit_devmem:
364 rt_kprintf("devmem2: <physical address in hex> <count in dec>\n");
365 return;
366 }
367 MSH_CMD_EXPORT(devmem2, dump device registers);
368
369