1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2023-09-23 GuEe-GUI first version
9 */
10
11 #ifndef __PCIE_DESIGNWARE_H__
12 #define __PCIE_DESIGNWARE_H__
13
14 #include <rtthread.h>
15 #include <rtdevice.h>
16
17 /* Parameters for the waiting for link up routine */
18 #define LINK_WAIT_MAX_RETRIES 10
19 #define LINK_WAIT_USLEEP_MIN 90000
20 #define LINK_WAIT_USLEEP_MAX 100000
21
22 /* Parameters for the waiting for iATU enabled routine */
23 #define LINK_WAIT_MAX_IATU_RETRIES 5
24 #define LINK_WAIT_IATU 9
25
26 /* Synopsys-specific PCIe configuration registers */
27 #define PCIE_PORT_AFR 0x70c
28 #define PORT_AFR_N_FTS_MASK RT_GENMASK(15, 8)
29 #define PORT_AFR_N_FTS(n) RT_FIELD_PREP(PORT_AFR_N_FTS_MASK, n)
30 #define PORT_AFR_CC_N_FTS_MASK RT_GENMASK(23, 16)
31 #define PORT_AFR_CC_N_FTS(n) RT_FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n)
32 #define PORT_AFR_ENTER_ASPM RT_BIT(30)
33 #define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24
34 #define PORT_AFR_L0S_ENTRANCE_LAT_MASK RT_GENMASK(26, 24)
35 #define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27
36 #define PORT_AFR_L1_ENTRANCE_LAT_MASK RT_GENMASK(29, 27)
37
38 #define PCIE_PORT_LINK_CONTROL 0x710
39 #define PORT_LINK_LPBK_ENABLE RT_BIT(2)
40 #define PORT_LINK_DLL_LINK_EN RT_BIT(5)
41 #define PORT_LINK_FAST_LINK_MODE RT_BIT(7)
42 #define PORT_LINK_MODE_MASK RT_GENMASK(21, 16)
43 #define PORT_LINK_MODE(n) RT_FIELD_PREP(PORT_LINK_MODE_MASK, n)
44 #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
45 #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
46 #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
47 #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
48
49 #define PCIE_PORT_DEBUG0 0x728
50 #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
51 #define PORT_LOGIC_LTSSM_STATE_L0 0x11
52 #define PCIE_PORT_DEBUG1 0x72c
53 #define PCIE_PORT_DEBUG1_LINK_UP RT_BIT(4)
54 #define PCIE_PORT_DEBUG1_LINK_IN_TRAINING RT_BIT(29)
55
56 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c
57 #define PORT_LOGIC_N_FTS_MASK RT_GENMASK(7, 0)
58 #define PORT_LOGIC_SPEED_CHANGE RT_BIT(17)
59 #define PORT_LOGIC_LINK_WIDTH_MASK RT_GENMASK(12, 8)
60 #define PORT_LOGIC_LINK_WIDTH(n) RT_FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
61 #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
62 #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
63 #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
64 #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
65
66 #define PCIE_MSI_ADDR_LO 0x820
67 #define PCIE_MSI_ADDR_HI 0x824
68 #define PCIE_MSI_INTR0_ENABLE 0x828
69 #define PCIE_MSI_INTR0_MASK 0x82c
70 #define PCIE_MSI_INTR0_STATUS 0x830
71
72 #define PCIE_PORT_MULTI_LANE_CTRL 0x8c0
73 #define PORT_MLTI_UPCFG_SUPPORT RT_BIT(7)
74
75 #define PCIE_ATU_VIEWPORT 0x900
76 #define PCIE_ATU_REGION_INBOUND RT_BIT(31)
77 #define PCIE_ATU_REGION_OUTBOUND 0
78 #define PCIE_ATU_CR1 0x904
79 #define PCIE_ATU_TYPE_MEM 0x0
80 #define PCIE_ATU_TYPE_IO 0x2
81 #define PCIE_ATU_TYPE_CFG0 0x4
82 #define PCIE_ATU_TYPE_CFG1 0x5
83 #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
84 #define PCIE_ATU_CR2 0x908
85 #define PCIE_ATU_ENABLE RT_BIT(31)
86 #define PCIE_ATU_BAR_MODE_ENABLE RT_BIT(30)
87 #define PCIE_ATU_FUNC_NUM_MATCH_EN RT_BIT(19)
88 #define PCIE_ATU_LOWER_BASE 0x90c
89 #define PCIE_ATU_UPPER_BASE 0x910
90 #define PCIE_ATU_LIMIT 0x914
91 #define PCIE_ATU_LOWER_TARGET 0x918
92 #define PCIE_ATU_BUS(x) RT_FIELD_PREP(RT_GENMASK(31, 24), x)
93 #define PCIE_ATU_DEV(x) RT_FIELD_PREP(RT_GENMASK(23, 19), x)
94 #define PCIE_ATU_FUNC(x) RT_FIELD_PREP(RT_GENMASK(18, 16), x)
95 #define PCIE_ATU_UPPER_TARGET 0x91c
96
97 #define PCIE_MISC_CONTROL_1_OFF 0x8bc
98 #define PCIE_DBI_RO_WR_EN RT_BIT(0)
99
100 #define PCIE_MSIX_DOORBELL 0x948
101 #define PCIE_MSIX_DOORBELL_PF_SHIFT 24
102
103 #define PCIE_PL_CHK_REG_CONTROL_STATUS 0xb20
104 #define PCIE_PL_CHK_REG_CHK_REG_START RT_BIT(0)
105 #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS RT_BIT(1)
106 #define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR RT_BIT(16)
107 #define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR RT_BIT(17)
108 #define PCIE_PL_CHK_REG_CHK_REG_COMPLETE RT_BIT(18)
109
110 #define PCIE_PL_CHK_REG_ERR_ADDR 0xb28
111
112 /*
113 * iATU Unroll-specific register definitions
114 * From 4.80 core version the address translation will be made by unroll
115 */
116 #define PCIE_ATU_UNR_REGION_CTRL1 0x00
117 #define PCIE_ATU_UNR_REGION_CTRL2 0x04
118 #define PCIE_ATU_UNR_LOWER_BASE 0x08
119 #define PCIE_ATU_UNR_UPPER_BASE 0x0C
120 #define PCIE_ATU_UNR_LOWER_LIMIT 0x10
121 #define PCIE_ATU_UNR_LOWER_TARGET 0x14
122 #define PCIE_ATU_UNR_UPPER_TARGET 0x18
123 #define PCIE_ATU_UNR_UPPER_LIMIT 0x20
124
125 /*
126 * The default address offset between dbi_base and atu_base. Root controller
127 * drivers are not required to initialize atu_base if the offset matches this
128 * default; the driver core automatically derives atu_base from dbi_base using
129 * this offset, if atu_base not set.
130 */
131 #define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
132
133 /* Register address builder */
134 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
135 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) (((region) << 9) | RT_BIT(8))
136
137 #define MAX_MSI_IRQS 256
138 #define MAX_MSI_IRQS_PER_CTRL 32
139 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
140 #define MSI_REG_CTRL_BLOCK_SIZE 12
141 #define MSI_DEF_NUM_VECTORS 32
142
143 /* Maximum number of inbound/outbound iATUs */
144 #define MAX_IATU_IN 256
145 #define MAX_IATU_OUT 256
146
147 #define DWC_IATU_UNROLL_EN RT_BIT(0)
148 #define DWC_IATU_IOCFG_SHARED RT_BIT(1)
149
150 struct dw_pcie_host_ops;
151 struct dw_pcie_ep_ops;
152 struct dw_pcie_ops;
153
154 enum dw_pcie_region_type
155 {
156 DW_PCIE_REGION_UNKNOWN,
157 DW_PCIE_REGION_INBOUND,
158 DW_PCIE_REGION_OUTBOUND,
159 };
160
161 enum dw_pcie_device_mode
162 {
163 DW_PCIE_UNKNOWN_TYPE,
164 DW_PCIE_EP_TYPE,
165 DW_PCIE_LEG_EP_TYPE,
166 DW_PCIE_RC_TYPE,
167 };
168
169 enum dw_pcie_aspace_type
170 {
171 DW_PCIE_ASPACE_UNKNOWN,
172 DW_PCIE_ASPACE_MEM,
173 DW_PCIE_ASPACE_IO,
174 };
175
176 struct dw_pcie_port
177 {
178 void *cfg0_base;
179 rt_uint64_t cfg0_addr;
180 rt_uint64_t cfg0_size;
181
182 rt_ubase_t io_addr;
183 rt_ubase_t io_bus_addr;
184 rt_size_t io_size;
185
186 const struct dw_pcie_host_ops *ops;
187
188 int sys_irq;
189 int msi_irq;
190 struct rt_pic *irq_pic;
191 struct rt_pic *msi_pic;
192
193 void *msi_data;
194 rt_ubase_t msi_data_phy;
195
196 rt_uint32_t irq_count;
197 rt_uint32_t irq_mask[MAX_MSI_CTRLS];
198
199 struct rt_pci_host_bridge *bridge;
200 const struct rt_pci_ops *bridge_child_ops;
201
202 struct rt_spinlock lock;
203 RT_BITMAP_DECLARE(msi_map, MAX_MSI_IRQS);
204 };
205
206 struct dw_pcie_host_ops
207 {
208 rt_err_t (*host_init)(struct dw_pcie_port *port);
209 rt_err_t (*msi_host_init)(struct dw_pcie_port *port);
210 void (*set_irq_count)(struct dw_pcie_port *port);
211 };
212
213 struct dw_pcie_ep_func
214 {
215 rt_list_t list;
216
217 rt_uint8_t func_no;
218 rt_uint8_t msi_cap; /* MSI capability offset */
219 rt_uint8_t msix_cap; /* MSI-X capability offset */
220 };
221
222 struct dw_pcie_ep
223 {
224 struct rt_pci_ep *epc;
225 struct rt_pci_ep_bar *epc_bar[PCI_STD_NUM_BARS];
226
227 rt_list_t func_nodes;
228
229 const struct dw_pcie_ep_ops *ops;
230
231 rt_uint64_t aspace;
232 rt_uint64_t aspace_size;
233 rt_size_t page_size;
234
235 rt_uint8_t bar_to_atu[PCI_STD_NUM_BARS];
236 rt_ubase_t *outbound_addr;
237
238 rt_bitmap_t *ib_window_map;
239 rt_bitmap_t *ob_window_map;
240 rt_uint32_t num_ib_windows;
241 rt_uint32_t num_ob_windows;
242
243 void *msi_mem;
244 rt_ubase_t msi_mem_phy;
245 };
246
247 struct dw_pcie_ep_ops
248 {
249 rt_err_t (*ep_init)(struct dw_pcie_ep *ep);
250 rt_err_t (*raise_irq)(struct dw_pcie_ep *ep, rt_uint8_t func_no, enum rt_pci_ep_irq type, unsigned irq);
251 rt_off_t (*func_select)(struct dw_pcie_ep *ep, rt_uint8_t func_no);
252 };
253
254 struct dw_pcie
255 {
256 struct rt_device *dev;
257
258 void *dbi_base;
259 void *dbi_base2;
260 void *atu_base;
261
262 rt_uint32_t version;
263 rt_uint32_t num_viewport;
264 rt_uint32_t num_lanes;
265 rt_uint32_t link_gen;
266 rt_uint32_t user_speed;
267 rt_uint8_t iatu_unroll_enabled; /* Internal Address Translation Unit */
268 rt_uint8_t fts_number[2]; /* Fast Training Sequences */
269
270 struct dw_pcie_port port;
271 struct dw_pcie_ep endpoint;
272 const struct dw_pcie_ops *ops;
273
274 void *priv;
275 };
276
277 struct dw_pcie_ops
278 {
279 rt_uint64_t (*cpu_addr_fixup)(struct dw_pcie *pcie, rt_uint64_t cpu_addr);
280 rt_uint32_t (*read_dbi)(struct dw_pcie *pcie, void *base, rt_uint32_t reg, rt_size_t size);
281 void (*write_dbi)(struct dw_pcie *pcie, void *base, rt_uint32_t reg, rt_size_t size, rt_uint32_t val);
282 void (*write_dbi2)(struct dw_pcie *pcie, void *base, rt_uint32_t reg, rt_size_t size, rt_uint32_t val);
283 rt_bool_t (*link_up)(struct dw_pcie *pcie);
284 rt_err_t (*start_link)(struct dw_pcie *pcie);
285 void (*stop_link)(struct dw_pcie *pcie);
286 };
287
288 #define to_dw_pcie_from_port(ptr) rt_container_of((ptr), struct dw_pcie, port)
289 #define to_dw_pcie_from_endpoint(ptr) rt_container_of((ptr), struct dw_pcie, endpoint)
290
291 #ifdef RT_PCI_DW_HOST
292 #undef RT_PCI_DW_HOST
293 #define RT_PCI_DW_HOST 1
294 #define HOST_API
295 #define HOST_RET(...) ;
296 #else
297 #define HOST_API rt_inline
298 #define HOST_RET(...) { return __VA_ARGS__; }
299 #endif
300
301 #ifdef RT_PCI_DW_EP
302 #undef RT_PCI_DW_EP
303 #define RT_PCI_DW_EP 1
304 #define EP_API
305 #define EP_RET(...) ;
306 #else
307 #define EP_API rt_inline
308 #define EP_RET(...) { return __VA_ARGS__; }
309 #endif
310
311 rt_uint8_t dw_pcie_find_capability(struct dw_pcie *pci, rt_uint8_t cap);
312 rt_uint16_t dw_pcie_find_ext_capability(struct dw_pcie *pci, rt_uint8_t cap);
313
314 rt_err_t dw_pcie_read(void *addr, rt_size_t size, rt_uint32_t *out_val);
315 rt_err_t dw_pcie_write(void *addr, rt_size_t size, rt_uint32_t val);
316
317 rt_uint32_t dw_pcie_read_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size);
318 void dw_pcie_write_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size, rt_uint32_t val);
319 void dw_pcie_write_dbi2(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size, rt_uint32_t val);
320 rt_uint32_t dw_pcie_readl_atu(struct dw_pcie *pci, rt_uint32_t reg);
321 void dw_pcie_writel_atu(struct dw_pcie *pci, rt_uint32_t reg, rt_uint32_t val);
322 rt_bool_t dw_pcie_link_up(struct dw_pcie *pci);
323 void dw_pcie_upconfig_setup(struct dw_pcie *pci);
324 rt_err_t dw_pcie_wait_for_link(struct dw_pcie *pci);
325 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, rt_uint64_t cpu_addr, rt_uint64_t pci_addr, rt_size_t size);
326 void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, rt_uint8_t func_no, int index, int type, rt_uint64_t cpu_addr, rt_uint64_t pci_addr, rt_size_t size);
327 rt_err_t dw_pcie_prog_inbound_atu(struct dw_pcie *pci, rt_uint8_t func_no, int index, int bar, rt_uint64_t cpu_addr, enum dw_pcie_aspace_type aspace_type);
328 void dw_pcie_disable_atu(struct dw_pcie *pci, int index, enum dw_pcie_region_type type);
329 void dw_pcie_setup(struct dw_pcie *pci);
330
dw_pcie_writel_dbi(struct dw_pcie * pci,rt_uint32_t reg,rt_uint32_t val)331 rt_inline void dw_pcie_writel_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_uint32_t val)
332 {
333 dw_pcie_write_dbi(pci, reg, 0x4, val);
334 }
335
dw_pcie_readl_dbi(struct dw_pcie * pci,rt_uint32_t reg)336 rt_inline rt_uint32_t dw_pcie_readl_dbi(struct dw_pcie *pci, rt_uint32_t reg)
337 {
338 return dw_pcie_read_dbi(pci, reg, 0x4);
339 }
340
dw_pcie_writew_dbi(struct dw_pcie * pci,rt_uint32_t reg,rt_uint16_t val)341 rt_inline void dw_pcie_writew_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_uint16_t val)
342 {
343 dw_pcie_write_dbi(pci, reg, 0x2, val);
344 }
345
dw_pcie_readw_dbi(struct dw_pcie * pci,rt_uint32_t reg)346 rt_inline rt_uint16_t dw_pcie_readw_dbi(struct dw_pcie *pci, rt_uint32_t reg)
347 {
348 return dw_pcie_read_dbi(pci, reg, 0x2);
349 }
350
dw_pcie_writeb_dbi(struct dw_pcie * pci,rt_uint32_t reg,rt_uint8_t val)351 rt_inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_uint8_t val)
352 {
353 dw_pcie_write_dbi(pci, reg, 0x1, val);
354 }
355
dw_pcie_readb_dbi(struct dw_pcie * pci,rt_uint32_t reg)356 rt_inline rt_uint8_t dw_pcie_readb_dbi(struct dw_pcie *pci, rt_uint32_t reg)
357 {
358 return dw_pcie_read_dbi(pci, reg, 0x1);
359 }
360
dw_pcie_writel_dbi2(struct dw_pcie * pci,rt_uint32_t reg,rt_uint32_t val)361 rt_inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, rt_uint32_t reg, rt_uint32_t val)
362 {
363 dw_pcie_write_dbi2(pci, reg, 0x4, val);
364 }
365
dw_pcie_dbi_ro_writable_enable(struct dw_pcie * pci,rt_bool_t enable)366 rt_inline void dw_pcie_dbi_ro_writable_enable(struct dw_pcie *pci, rt_bool_t enable)
367 {
368 const rt_uint32_t reg = PCIE_MISC_CONTROL_1_OFF;
369
370 if (enable)
371 {
372 dw_pcie_writel_dbi(pci, reg, dw_pcie_readl_dbi(pci, reg) | PCIE_DBI_RO_WR_EN);
373 }
374 else
375 {
376 dw_pcie_writel_dbi(pci, reg, dw_pcie_readl_dbi(pci, reg) & ~PCIE_DBI_RO_WR_EN);
377 }
378 }
379
dw_pcie_iatu_unroll_enabled(struct dw_pcie * pci)380 rt_inline rt_uint8_t dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
381 {
382 return dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) == 0xffffffff ? 1 : 0;
383 }
384
dw_pcie_readl_ob_unroll(struct dw_pcie * pci,rt_uint32_t index,rt_uint32_t reg)385 rt_inline rt_uint32_t dw_pcie_readl_ob_unroll(struct dw_pcie *pci,
386 rt_uint32_t index, rt_uint32_t reg)
387 {
388 return dw_pcie_readl_atu(pci, PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index) + reg);
389 }
390
dw_pcie_writel_ob_unroll(struct dw_pcie * pci,rt_uint32_t index,rt_uint32_t reg,rt_uint32_t val)391 rt_inline void dw_pcie_writel_ob_unroll(struct dw_pcie *pci,
392 rt_uint32_t index, rt_uint32_t reg, rt_uint32_t val)
393 {
394 dw_pcie_writel_atu(pci, PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index) + reg, val);
395 }
396
dw_pcie_readl_ib_unroll(struct dw_pcie * pci,rt_uint32_t index,rt_uint32_t reg)397 rt_inline rt_uint32_t dw_pcie_readl_ib_unroll(struct dw_pcie *pci,
398 rt_uint32_t index, rt_uint32_t reg)
399 {
400 return dw_pcie_readl_atu(pci, PCIE_GET_ATU_INB_UNR_REG_OFFSET(index) + reg);
401 }
402
dw_pcie_writel_ib_unroll(struct dw_pcie * pci,rt_uint32_t index,rt_uint32_t reg,rt_uint32_t val)403 rt_inline void dw_pcie_writel_ib_unroll(struct dw_pcie *pci,
404 rt_uint32_t index, rt_uint32_t reg, rt_uint32_t val)
405 {
406 dw_pcie_writel_atu(pci, reg + PCIE_GET_ATU_INB_UNR_REG_OFFSET(index), val);
407 }
408
409 HOST_API rt_err_t dw_handle_msi_irq(struct dw_pcie_port *port) HOST_RET(-RT_ENOSYS)
410 HOST_API void dw_pcie_msi_init(struct dw_pcie_port *port) HOST_RET()
411 HOST_API void dw_pcie_free_msi(struct dw_pcie_port *port) HOST_RET()
412
413 HOST_API void dw_pcie_setup_rc(struct dw_pcie_port *port) HOST_RET()
414
415 HOST_API rt_err_t dw_pcie_host_init(struct dw_pcie_port *port) HOST_RET(-RT_ENOSYS)
416 HOST_API void dw_pcie_host_deinit(struct dw_pcie_port *port) HOST_RET()
417
418 HOST_API void dw_pcie_host_free(struct dw_pcie_port *port) HOST_RET()
419
420 HOST_API void *dw_pcie_own_conf_map(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg) HOST_RET(RT_NULL)
421
422 EP_API rt_err_t dw_pcie_ep_init(struct dw_pcie_ep *ep) EP_RET(-RT_ENOSYS)
423 EP_API rt_err_t dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) EP_RET(-RT_ENOSYS)
424 EP_API void dw_pcie_ep_exit(struct dw_pcie_ep *ep) EP_RET()
425
426 EP_API rt_err_t dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no) EP_RET(-RT_ENOSYS)
427 EP_API rt_err_t dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no, unsigned irq) EP_RET(-RT_ENOSYS)
428 EP_API rt_err_t dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no, unsigned irq) EP_RET(-RT_ENOSYS)
429 EP_API rt_err_t dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, rt_uint8_t func_no, unsigned irq) EP_RET(-RT_ENOSYS)
430
431 EP_API void dw_pcie_ep_reset_bar(struct dw_pcie *pci, int bar_idx) EP_RET()
432
433 EP_API rt_err_t dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, rt_uint8_t func_no,
434 int bar_idx, rt_ubase_t cpu_addr, enum dw_pcie_aspace_type aspace_type) EP_RET(-RT_ENOSYS)
435 EP_API rt_err_t dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, rt_uint8_t func_no,
436 rt_ubase_t phys_addr, rt_uint64_t pci_addr, rt_size_t size) EP_RET(-RT_ENOSYS)
437
438 EP_API struct dw_pcie_ep_func *dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, rt_uint8_t func_no) EP_RET(RT_NULL)
439
440 #endif /* __PCIE_DESIGNWARE_H__ */
441