1 /* 2 * Copyright (c) 2006-2024, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-07-25 weety first version 9 * 2024-05-25 HPMicro add HS400 support 10 * 2024-05-26 HPMicro add UHS-I support 11 */ 12 13 #ifndef __HOST_H__ 14 #define __HOST_H__ 15 16 #include <rtthread.h> 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 struct rt_mmcsd_io_cfg 23 { 24 rt_uint32_t clock; /* clock rate */ 25 rt_uint16_t vdd; 26 27 /* vdd stores the bit number of the selected voltage range from below. */ 28 29 rt_uint8_t bus_mode; /* command output mode */ 30 31 #define MMCSD_BUSMODE_OPENDRAIN 1 32 #define MMCSD_BUSMODE_PUSHPULL 2 33 34 rt_uint8_t chip_select; /* SPI chip select */ 35 36 #define MMCSD_CS_IGNORE 0 37 #define MMCSD_CS_HIGH 1 38 #define MMCSD_CS_LOW 2 39 40 rt_uint8_t power_mode; /* power supply mode */ 41 42 #define MMCSD_POWER_OFF 0 43 #define MMCSD_POWER_UP 1 44 #define MMCSD_POWER_ON 2 45 46 rt_uint8_t bus_width; /* data bus width */ 47 48 #define MMCSD_BUS_WIDTH_1 0 49 #define MMCSD_BUS_WIDTH_4 2 50 #define MMCSD_BUS_WIDTH_8 3 51 52 unsigned char timing; /* timing specification used */ 53 54 #define MMCSD_TIMING_LEGACY 0 55 #define MMCSD_TIMING_MMC_HS 1 56 #define MMCSD_TIMING_SD_HS 2 57 #define MMCSD_TIMING_UHS_SDR12 3 58 #define MMCSD_TIMING_UHS_SDR25 4 59 #define MMCSD_TIMING_UHS_SDR50 5 60 #define MMCSD_TIMING_UHS_SDR104 6 61 #define MMCSD_TIMING_UHS_DDR50 7 62 #define MMCSD_TIMING_MMC_DDR52 8 63 #define MMCSD_TIMING_MMC_HS200 9 64 #define MMCSD_TIMING_MMC_HS400 10 65 #define MMCSD_TIMING_MMC_HS400_ENH_DS 11 66 67 unsigned char drv_type; /* driver type (A, B, C, D) */ 68 69 #define MMCSD_SET_DRIVER_TYPE_B 0 70 #define MMCSD_SET_DRIVER_TYPE_A 1 71 #define MMCSD_SET_DRIVER_TYPE_C 2 72 #define MMCSD_SET_DRIVER_TYPE_D 3 73 74 unsigned char signal_voltage; 75 76 #define MMCSD_SIGNAL_VOLTAGE_330 0 77 #define MMCSD_SIGNAL_VOLTAGE_180 1 78 #define MMCSD_SIGNAL_VOLTAGE_120 2 79 }; 80 81 struct rt_mmcsd_host; 82 struct rt_mmcsd_req; 83 84 struct rt_mmcsd_host_ops 85 { 86 void (*request)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req); 87 void (*set_iocfg)(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); 88 rt_int32_t (*get_card_status)(struct rt_mmcsd_host *host); 89 void (*enable_sdio_irq)(struct rt_mmcsd_host *host, rt_int32_t en); 90 rt_int32_t (*execute_tuning)(struct rt_mmcsd_host *host, rt_int32_t opcode); 91 rt_int32_t (*switch_uhs_voltage)(struct rt_mmcsd_host *host); 92 }; 93 94 struct rt_mmcsd_host 95 { 96 char name[RT_NAME_MAX]; 97 struct rt_mmcsd_card *card; 98 const struct rt_mmcsd_host_ops *ops; 99 rt_uint32_t freq_min; 100 rt_uint32_t freq_max; 101 struct rt_mmcsd_io_cfg io_cfg; 102 rt_uint32_t valid_ocr; /* current valid OCR */ 103 #define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */ 104 #define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */ 105 #define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */ 106 #define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */ 107 #define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */ 108 #define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */ 109 #define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */ 110 #define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */ 111 #define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */ 112 #define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */ 113 #define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */ 114 #define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */ 115 #define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */ 116 #define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */ 117 #define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */ 118 #define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */ 119 #define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */ 120 #define OCR_S18R (1 << 24) /* Switch to 1V8 Request */ 121 rt_uint32_t flags; /* define device capabilities */ 122 #define MMCSD_BUSWIDTH_4 (1 << 0) 123 #define MMCSD_BUSWIDTH_8 (1 << 1) 124 #define MMCSD_MUTBLKWRITE (1 << 2) 125 #define MMCSD_HOST_IS_SPI (1 << 3) 126 #define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI) 127 #define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */ 128 #define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed SDR */ 129 #define MMCSD_SUP_DDR_3V3 (1 << 6) 130 #define MMCSD_SUP_DDR_1V8 (1 << 7) 131 #define MMCSD_SUP_DDR_1V2 (1 << 8) 132 #define MMCSD_SUP_HIGHSPEED_DDR (MMCSD_SUP_DDR_3V3 | MMCSD_SUP_DDR_1V8 | MMCSD_SUP_DDR_1V2)/* HIGH SPEED DDR */ 133 #define MMCSD_SUP_HS200_1V8 (1 << 9) 134 #define MMCSD_SUP_HS200_1V2 (1 << 10) 135 #define MMCSD_SUP_HS200 (MMCSD_SUP_HS200_1V2 | MMCSD_SUP_HS200_1V8) /* hs200 sdr */ 136 #define MMCSD_SUP_NONREMOVABLE (1 << 11) 137 #define controller_is_removable(host) (!(host->flags & MMCSD_SUP_NONREMOVABLE)) 138 #define MMCSD_SUP_HS400_1V8 (1 << 12) 139 #define MMCSD_SUP_HS400_1V2 (1 << 13) 140 #define MMCSD_SUP_HS400 (MMCSD_SUP_HS400_1V2 | MMCSD_SUP_HS400_1V8) /* hs400 ddr */ 141 #define MMCSD_SUP_ENH_DS (1 << 14) 142 #define MMCSD_SUP_SDR50 (1 << 15) 143 #define MMCSD_SUP_SDR104 (1 << 16) 144 #define MMCSD_SUP_DDR50 (1 << 17) 145 146 rt_uint32_t max_seg_size; /* maximum size of one dma segment */ 147 rt_uint32_t max_dma_segs; /* maximum number of dma segments in one request */ 148 rt_uint32_t max_blk_size; /* maximum block size */ 149 rt_uint32_t max_blk_count; /* maximum block count */ 150 151 rt_uint32_t id; /* Assigned host id */ 152 153 rt_uint32_t spi_use_crc; 154 struct rt_mutex bus_lock; 155 struct rt_semaphore sem_ack; 156 157 rt_uint32_t sdio_irq_num; 158 struct rt_semaphore *sdio_irq_sem; 159 struct rt_thread *sdio_irq_thread; 160 161 void *private_data; 162 }; 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif 168