1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2020-07-26     lizhirui     the first version
9  */
10 #ifndef __MIPS_MMU_H__
11 #define __MIPS_MMU_H__
12 
13 typedef enum cpu_mode_t
14 {
15     CPU_MODE_KERNEL = 0x00,
16     CPU_MODE_SUPERVISOR = 0x01,
17     CPU_MODE_USER = 0x02
18 }cpu_mode_t;
19 
20 typedef enum page_mask_enum_t
21 {
22     PAGE_MASK_4KB = 0x00,
23     PAGE_MASK_16KB = 0x03,
24     PAGE_MASK_64KB = 0x0F,
25     PAGE_MASK_256KB = 0x3F,
26     PAGE_MASK_1MB = 0xFF,
27     PAGE_MASK_4MB = 0x3FF,
28     PAGE_MASK_16MB = 0xFFF,
29     PAGE_MASK_64MB = 0x3FFF,
30     PAGE_MASK_256MB = 0xFFFF,
31     PAGE_MASK_1GB = 0x3FFFF
32 }page_mask_enum_t;
33 
34 typedef struct page_mask_t
35 {
36     uint64_t : 11;
37     uint64_t : 2;
38     uint64_t mask : 18;
39     uint64_t : 33;
40 }page_mask_t;
41 
42 typedef struct entry_lo_t
43 {
44     uint64_t g : 1;
45     uint64_t v : 1;
46     uint64_t d : 1;
47     uint64_t c : 3;
48     uint64_t pfn : 24;
49     uint64_t pfnx : 3;
50     uint64_t : 29;
51     uint64_t xi : 1;
52     uint64_t ri : 1;
53 }entry_lo_t;
54 
55 typedef struct entry_hi_t
56 {
57     uint64_t asid : 8;
58     uint64_t : 5;
59     uint64_t vpn2 : 27;
60     uint64_t : 22;
61     uint64_t r : 2;
62 }entry_hi_t;
63 
64 typedef struct tlb_item_t
65 {
66     entry_lo_t entry_lo[2];
67     entry_hi_t entry_hi;
68     page_mask_t page_mask;
69 }tlb_item_t;
70 
71 #define read_c0_diag()        __read_32bit_c0_register($22, 0)
72 #define write_c0_diag(val)    __write_32bit_c0_register($22, 0, val)
73 #define read_c0_badvaddr()    __read_64bit_c0_register($8, 0)
74 #define read_c0_random()      __read_32bit_c0_register($1, 0)
75 
76 #define reg_type_convert(variable,new_type) *((new_type *)(&variable))
77 #define lowbit(x) ((x) & (-(x)))
78 
79 void mmu_init();
80 void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
81 cpu_mode_t mmu_get_cpu_mode();
82 void mmu_clear_tlb();
83 void mmu_clear_itlb();
84 uint32_t mmu_get_max_tlb_index();
85 void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
86 void mmu_tlb_write_random(tlb_item_t *tlb_item);
87 void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
88 uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
89 void mmu_tlb_item_init(tlb_item_t *tlb_item);
90 void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
91 uint32_t mmu_tlb_get_random();
92 uint32_t mmu_tlb_get_index();
93 void mmu_tlb_set_index(uint32_t index);
94 uint32_t mmu_tlb_is_matched();
95 uint64_t mmu_tlb_get_bad_vaddr();
96 
97 void tlb_dump();
98 
99 #endif
100