1 /**
2 ******************************************************************************
3 * @file bl702_pds.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl702.h"
38 #include "bl702_pds.h"
39
40 /** @addtogroup BL702_Peripheral_Driver
41 * @{
42 */
43
44 /** @addtogroup PDS
45 * @{
46 */
47
48 /** @defgroup PDS_Private_Macros
49 * @{
50 */
51
52 /*@} end of group PDS_Private_Macros */
53
54 /** @defgroup PDS_Private_Types
55 * @{
56 */
57
58 /*@} end of group PDS_Private_Types */
59
60 /** @defgroup PDS_Private_Variables
61 * @{
62 */
63 static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX][1] = { { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL } };
64
65 /*@} end of group PDS_Private_Variables */
66
67 /** @defgroup PDS_Global_Variables
68 * @{
69 */
70
71 /*@} end of group PDS_Global_Variables */
72
73 /** @defgroup PDS_Private_Fun_Declaration
74 * @{
75 */
76
77 /*@} end of group PDS_Private_Fun_Declaration */
78
79 /** @defgroup PDS_Private_Functions
80 * @{
81 */
82
83 /*@} end of group PDS_Private_Functions */
84
85 /** @defgroup PDS_Public_Functions
86 * @{
87 */
88
89 /****************************************************************************/ /**
90 * @brief power down sleep ram configure
91 *
92 * @param ramCfg: power down sleep force ram configuration
93 *
94 * @return SUCCESS or ERROR
95 *
96 *******************************************************************************/
PDS_RAM_Config(PDS_RAM_CFG_Type * ramCfg)97 BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg)
98 {
99 if (NULL == ramCfg) {
100 return ERROR;
101 }
102
103 /* PDS_RAM1 config */
104 BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg);
105
106 return SUCCESS;
107 }
108
109 /****************************************************************************/ /**
110 * @brief power down sleep set pad configure
111 *
112 * @param pin: power down sleep pad num
113 * @param cfg: power down sleep pad type
114 *
115 * @return SUCCESS or ERROR
116 *
117 *******************************************************************************/
PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin,PDS_PAD_CFG_Type cfg)118 BL_Err_Type ATTR_TCM_SECTION PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg)
119 {
120 uint32_t tmpVal = 0;
121 uint32_t tmpPu = 0;
122 uint32_t tmpPd = 0;
123
124 if (pin < PDS_PAD_PIN_GPIO_23) {
125 /* GPIO17 - GPIO22 */
126 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD);
127
128 switch (cfg) {
129 case PDS_PAD_CFG_PULL_NONE:
130 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin);
131 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin);
132 break;
133
134 case PDS_PAD_CFG_PULL_DOWN:
135 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin);
136 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin);
137 break;
138
139 case PDS_PAD_CFG_PULL_UP:
140 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin);
141 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin);
142 break;
143
144 case PDS_PAD_CFG_ACTIVE_IE:
145 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin);
146 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin);
147 break;
148
149 default:
150 break;
151 }
152
153 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD, tmpPd);
154 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU, tmpPu);
155 BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal);
156 } else {
157 /* GPIO23 - GPIO28 */
158 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD);
159
160 switch (cfg) {
161 case PDS_PAD_CFG_PULL_NONE:
162 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
163 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
164 break;
165
166 case PDS_PAD_CFG_PULL_DOWN:
167 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
168 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
169 break;
170
171 case PDS_PAD_CFG_PULL_UP:
172 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
173 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
174 break;
175
176 case PDS_PAD_CFG_ACTIVE_IE:
177 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
178 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
179 break;
180
181 default:
182 break;
183 }
184
185 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD, tmpPd);
186 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU, tmpPu);
187 BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal);
188 }
189
190 return SUCCESS;
191 }
192
193 /****************************************************************************/ /**
194 * @brief Enable power down sleep
195 *
196 * @param cfg: power down sleep configuration 1
197 * @param cfg4: power down sleep configuration 2
198 * @param pdsSleepCnt: power down sleep count cycle
199 *
200 * @return SUCCESS or ERROR
201 *
202 *******************************************************************************/
PDS_App_Enable(PDS_CTL_Type * cfg,PDS_CTL4_Type * cfg4,uint32_t pdsSleepCnt)203 BL_Err_Type ATTR_TCM_SECTION PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
204 {
205 uint32_t tmpVal=0;
206 /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
207 /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
208 if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
209 return ERROR;
210 } else if (pdsSleepCnt > PDS_WARMUP_LATENCY_CNT) {
211 BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
212 } else {
213 /* PDS sleep time 0 ,means mask pds_timer wakeup */
214 }
215
216 /* PDS_CTL4 config */
217 BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);
218
219 /* PDS_CTL config */
220 if (cfg->pdsStart) {
221 /* clear pds int */
222 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
223 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
224 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
225
226 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
227 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
228 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
229
230 BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
231 BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
232 } else {
233 BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
234 }
235
236 return SUCCESS;
237 }
238
239 /****************************************************************************/ /**
240 * @brief power down sleep force configure
241 *
242 * @param cfg2: power down sleep force configuration 1
243 * @param cfg3: power down sleep force configuration 2
244 *
245 * @return SUCCESS or ERROR
246 *
247 *******************************************************************************/
PDS_Force_Config(PDS_CTL2_Type * cfg2,PDS_CTL3_Type * cfg3)248 BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3)
249 {
250 /* PDS_CTL2 config */
251 BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);
252
253 /* PDS_CTL3 config */
254 BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);
255
256 return SUCCESS;
257 }
258
259 /****************************************************************************/ /**
260 * @brief power down sleep force configure
261 *
262 * @param defaultLvCfg: power down sleep default level configuration
263 * @param pdsSleepCnt: power down sleep time count
264 *
265 * @return SUCCESS or ERROR
266 *
267 *******************************************************************************/
PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type * defaultLvCfg,uint32_t pdsSleepCnt)268 BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt)
269 {
270 PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3));
271 PDS_App_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);
272
273 return SUCCESS;
274 }
275
276 /****************************************************************************/ /**
277 * @brief power down sleep int enable
278 *
279 * @param intType: PDS int type
280 * @param enable: ENABLE or DISABLE
281 *
282 * @return SUCCESS or ERROR
283 *
284 *******************************************************************************/
PDS_IntEn(PDS_INT_Type intType,BL_Fun_Type enable)285 BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable)
286 {
287 uint32_t offset = 0;
288 uint32_t tmpVal = 0;
289
290 if ((intType < PDS_INT_PDS_SLEEP_CNT) || (intType > PDS_INT_KYS_QDEC)) {
291 return ERROR;
292 }
293
294 switch (intType) {
295 case PDS_INT_WAKEUP:
296 case PDS_INT_RF_DONE:
297 case PDS_INT_PLL_DONE:
298 return ERROR;
299
300 case PDS_INT_PDS_SLEEP_CNT:
301 offset = 16;
302 break;
303
304 case PDS_INT_HBN_IRQ_OUT0:
305 offset = 17;
306 break;
307
308 case PDS_INT_HBN_IRQ_OUT1:
309 offset = 18;
310 break;
311
312 case PDS_INT_GPIO_IRQ:
313 offset = 19;
314 break;
315
316 case PDS_INT_IRRX:
317 offset = 20;
318 break;
319
320 case PDS_INT_BLE_SLP_IRQ:
321 offset = 21;
322 break;
323
324 case PDS_INT_USB_WKUP:
325 offset = 22;
326 break;
327
328 case PDS_INT_KYS_QDEC:
329 offset = 23;
330 break;
331
332 case PDS_INT_MAX:
333 break;
334
335 default:
336 break;
337 }
338
339 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
340
341 if (enable) {
342 tmpVal = tmpVal | (1 << offset);
343 } else {
344 tmpVal = tmpVal & ~(1 << offset);
345 }
346
347 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
348
349 return SUCCESS;
350 }
351
352 /****************************************************************************/ /**
353 * @brief power down sleep int mask
354 *
355 * @param intType: PDS int type
356 * @param intMask: MASK or UNMASK
357 *
358 * @return SUCCESS or ERROR
359 *
360 *******************************************************************************/
PDS_IntMask(PDS_INT_Type intType,BL_Mask_Type intMask)361 BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask)
362 {
363 uint32_t offset = 0;
364 uint32_t tmpVal = 0;
365
366 if (intType > PDS_INT_PLL_DONE) {
367 return ERROR;
368 }
369
370 switch (intType) {
371 case PDS_INT_WAKEUP:
372 offset = 8;
373 break;
374
375 case PDS_INT_RF_DONE:
376 offset = 10;
377 break;
378
379 case PDS_INT_PLL_DONE:
380 offset = 11;
381 break;
382
383 case PDS_INT_PDS_SLEEP_CNT:
384 case PDS_INT_HBN_IRQ_OUT0:
385 case PDS_INT_HBN_IRQ_OUT1:
386 case PDS_INT_GPIO_IRQ:
387 case PDS_INT_IRRX:
388 case PDS_INT_BLE_SLP_IRQ:
389 case PDS_INT_USB_WKUP:
390 case PDS_INT_KYS_QDEC:
391 case PDS_INT_MAX:
392 default:
393 return ERROR;
394 }
395
396 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
397
398 if (intMask != UNMASK) {
399 tmpVal = tmpVal | (1 << offset);
400 } else {
401 tmpVal = tmpVal & ~(1 << offset);
402 }
403
404 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
405
406 return SUCCESS;
407 }
408
409 /****************************************************************************/ /**
410 * @brief get power down sleep int status
411 *
412 * @param intType: PDS int type
413 *
414 * @return SET or RESET
415 *
416 *******************************************************************************/
PDS_Get_IntStatus(PDS_INT_Type intType)417 BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)
418 {
419 uint32_t offset = 0;
420
421 switch (intType) {
422 case PDS_INT_WAKEUP:
423 offset = 0;
424 break;
425
426 case PDS_INT_RF_DONE:
427 offset = 2;
428 break;
429
430 case PDS_INT_PLL_DONE:
431 offset = 3;
432 break;
433
434 case PDS_INT_PDS_SLEEP_CNT:
435 offset = 24;
436 break;
437
438 case PDS_INT_HBN_IRQ_OUT0:
439 offset = 25;
440 break;
441
442 case PDS_INT_HBN_IRQ_OUT1:
443 offset = 26;
444 break;
445
446 case PDS_INT_GPIO_IRQ:
447 offset = 27;
448 break;
449
450 case PDS_INT_IRRX:
451 offset = 28;
452 break;
453
454 case PDS_INT_BLE_SLP_IRQ:
455 offset = 29;
456 break;
457
458 case PDS_INT_USB_WKUP:
459 offset = 30;
460 break;
461
462 case PDS_INT_KYS_QDEC:
463 offset = 31;
464 break;
465
466 case PDS_INT_MAX:
467 break;
468
469 default:
470 break;
471 }
472
473 return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << offset)) ? SET : RESET;
474 }
475
476 /****************************************************************************/ /**
477 * @brief clear power down sleep int status
478 *
479 * @param None
480 *
481 * @return SUCCESS or ERROR
482 *
483 *******************************************************************************/
PDS_IntClear(void)484 BL_Err_Type PDS_IntClear(void)
485 {
486 uint32_t tmpVal = 0;
487
488 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
489 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
490 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
491
492 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
493 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
494 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
495
496 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
497 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
498 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
499
500 return SUCCESS;
501 }
502
503 /****************************************************************************/ /**
504 * @brief get power down sleep PLL status
505 *
506 * @param None
507 *
508 * @return PDS PLL status
509 *
510 *******************************************************************************/
PDS_Get_PdsPllStstus(void)511 PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void)
512 {
513 return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE);
514 }
515
516 /****************************************************************************/ /**
517 * @brief get power down sleep RF status
518 *
519 * @param None
520 *
521 * @return PDS RF status
522 *
523 *******************************************************************************/
PDS_Get_PdsRfStstus(void)524 PDS_RF_STS_Type PDS_Get_PdsRfStstus(void)
525 {
526 return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE);
527 }
528
529 /****************************************************************************/ /**
530 * @brief get power down sleep status
531 *
532 * @param None
533 *
534 * @return PDS status
535 *
536 *******************************************************************************/
PDS_Get_PdsStstus(void)537 PDS_STS_Type PDS_Get_PdsStstus(void)
538 {
539 return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE);
540 }
541
542 /****************************************************************************/ /**
543 * @brief power down sleep clear reset event
544 *
545 * @param None
546 *
547 * @return SUCCESS or ERROR
548 *
549 *******************************************************************************/
PDS_Clear_Reset_Event(void)550 BL_Err_Type PDS_Clear_Reset_Event(void)
551 {
552 uint32_t tmpVal = 0;
553
554 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
555 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
556 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
557
558 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
559 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
560 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
561
562 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
563 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
564 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
565
566 return SUCCESS;
567 }
568
569 /****************************************************************************/ /**
570 * @brief get power down sleep reset event
571 *
572 * @param event: power down sleep reset event
573 *
574 * @return SET or RESET
575 *
576 *******************************************************************************/
PDS_Get_Reset_Event(PDS_RST_EVENT_Type event)577 BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event)
578 {
579 uint32_t tmpVal = 0;
580
581 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
582 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_RESET_EVENT);
583
584 return (tmpVal & (1 << event)) ? SET : RESET;
585 }
586
587 /****************************************************************************/ /**
588 * @brief set power down sleep VDDCORE gpio interrupt config
589 *
590 * @param src: PDS VDDCORE src pin num
591 * @param mode: PDS VDDCORE src pin interrupt type
592 *
593 * @return SUCCESS or ERROR
594 *
595 *******************************************************************************/
PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src,PDS_AON_GPIO_INT_Trigger_Type mode)596 BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src, PDS_AON_GPIO_INT_Trigger_Type mode)
597 {
598 uint32_t tmpVal = 0;
599
600 CHECK_PARAM(IS_PDS_VDDCORE_GPIO_SRC_TYPE(src));
601 CHECK_PARAM(IS_PDS_AON_GPIO_INT_Trigger_TYPE(mode));
602
603 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
604 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, src);
605 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, mode);
606 BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
607
608 return SUCCESS;
609 }
610
611 /****************************************************************************/ /**
612 * @brief set power down sleep VDDCORE gpio interrupt mask
613 *
614 * @param intMask: None
615 *
616 * @return SUCCESS or ERROR
617 *
618 *******************************************************************************/
PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask)619 BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask)
620 {
621 uint32_t tmpVal = 0;
622
623 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
624
625 if (intMask != UNMASK) {
626 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
627 } else {
628 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
629 }
630
631 BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
632
633 return SUCCESS;
634 }
635
636 /****************************************************************************/ /**
637 * @brief set power down sleep VDDCORE gpio interrupt mask
638 *
639 * @param None
640 *
641 * @return SUCCESS or ERROR
642 *
643 *******************************************************************************/
PDS_Get_Vddcore_GPIO_IntStatus(void)644 BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void)
645 {
646 return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_STAT) ? SET : RESET;
647 }
648
649 /****************************************************************************/ /**
650 * @brief set power down sleep VDDCORE gpio interrupt mask
651 *
652 * @param None
653 *
654 * @return SUCCESS or ERROR
655 *
656 *******************************************************************************/
PDS_Set_Vddcore_GPIO_IntClear(void)657 BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void)
658 {
659 uint32_t tmpVal = 0;
660
661 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
662 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
663 BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
664
665 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
666 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
667 BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
668
669 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
670 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
671 BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
672
673 return SUCCESS;
674 }
675
676 /****************************************************************************/ /**
677 * @brief Install PDS interrupt callback function
678 *
679 * @param intType: PDS int type
680 * @param cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
681 *
682 * @return SUCCESS or ERROR
683 *
684 *******************************************************************************/
PDS_Int_Callback_Install(PDS_INT_Type intType,intCallback_Type * cbFun)685 BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun)
686 {
687 pdsIntCbfArra[intType][0] = cbFun;
688
689 return SUCCESS;
690 }
691
692 /****************************************************************************/ /**
693 * @brief Trim RC32M
694 *
695 * @param None
696 *
697 * @return SUCCESS or ERROR
698 *
699 *******************************************************************************/
700 #ifndef BFLB_USE_ROM_DRIVER
701 __WEAK
PDS_Trim_RC32M(void)702 BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
703 {
704 Efuse_Ana_RC32M_Trim_Type trim;
705 int32_t tmpVal = 0;
706
707 EF_Ctrl_Read_RC32M_Trim(&trim);
708
709 if (trim.trimRc32mExtCodeEn) {
710 if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) {
711 tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);
712 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt);
713 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);
714 BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);
715 BL702_Delay_US(2);
716 return SUCCESS;
717 }
718 }
719
720 return ERROR;
721 }
722 #endif
723
724 /****************************************************************************/ /**
725 * @brief Select RC32M as PLL ref source
726 *
727 * @param None
728 *
729 * @return SUCCESS or ERROR
730 *
731 *******************************************************************************/
732 #ifndef BFLB_USE_ROM_DRIVER
733 __WEAK
PDS_Select_RC32M_As_PLL_Ref(void)734 BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void)
735 {
736 uint32_t tmpVal = 0;
737
738 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
739 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
740 BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
741
742 return SUCCESS;
743 }
744 #endif
745
746 /****************************************************************************/ /**
747 * @brief Select XTAL as PLL ref source
748 *
749 * @param None
750 *
751 * @return SUCCESS or ERROR
752 *
753 *******************************************************************************/
754 #ifndef BFLB_USE_ROM_DRIVER
755 __WEAK
PDS_Select_XTAL_As_PLL_Ref(void)756 BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void)
757 {
758 uint32_t tmpVal = 0;
759
760 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
761 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
762 BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
763
764 return SUCCESS;
765 }
766 #endif
767
768 /****************************************************************************/ /**
769 * @brief Power on PLL
770 *
771 * @param xtalType: xtal type
772 *
773 * @return SUCCESS or ERROR
774 *
775 *******************************************************************************/
776 #ifndef BFLB_USE_ROM_DRIVER
777 __WEAK
PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)778 BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
779 {
780 uint32_t tmpVal = 0;
781
782 /* Check parameter*/
783 CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType));
784
785 /**************************/
786 /* select PLL XTAL source */
787 /**************************/
788
789 if ((xtalType == PDS_PLL_XTAL_RC32M) || (xtalType == PDS_PLL_XTAL_NONE)) {
790 PDS_Trim_RC32M();
791 PDS_Select_RC32M_As_PLL_Ref();
792 } else {
793 PDS_Select_XTAL_As_PLL_Ref();
794 }
795
796 /*******************************************/
797 /* PLL power down first, not indispensable */
798 /*******************************************/
799 /* power off PLL first, this step is not indispensable */
800 PDS_Power_Off_PLL();
801
802 /********************/
803 /* PLL param config */
804 /********************/
805
806 /* clkpll_icp_1u */
807 /* clkpll_icp_5u */
808 /* clkpll_int_frac_sw */
809 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP);
810 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 0);
811 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 2);
812 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 0);
813 BL_WR_REG(PDS_BASE, PDS_CLKPLL_CP, tmpVal);
814
815 /* clkpll_c3 */
816 /* clkpll_cz */
817 /* clkpll_rz */
818 /* clkpll_r4 */
819 /* clkpll_r4_short */
820 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ);
821 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 3);
822 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 1);
823 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 1);
824 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 1);
825 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4, 2);
826 BL_WR_REG(PDS_BASE, PDS_CLKPLL_RZ, tmpVal);
827
828 /* clkpll_refdiv_ratio */
829 /* clkpll_postdiv */
830 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
831 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 0x14);
832 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 2);
833 BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
834
835 /* clkpll_sdmin */
836 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
837 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
838 BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
839
840 /* clkpll_sel_fb_clk */
841 /* clkpll_sel_sample_clk can be 0/1, default is 1 */
842 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_FBDV);
843 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_FB_CLK, 1);
844 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_SAMPLE_CLK, 1);
845 BL_WR_REG(PDS_BASE, PDS_CLKPLL_FBDV, tmpVal);
846
847 /*************************/
848 /* PLL power up sequence */
849 /*************************/
850
851 /* pu_clkpll_sfreg=1 */
852 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
853 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
854 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
855
856 BL702_Delay_US(5);
857
858 /* pu_clkpll=1 */
859 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
860 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL);
861 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
862
863 /* clkpll_pu_cp=1 */
864 /* clkpll_pu_pfd=1 */
865 /* clkpll_pu_fbdv=1 */
866 /* clkpll_pu_postdiv=1 */
867 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
868 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
869 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
870 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
871 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
872 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
873
874 BL702_Delay_US(5);
875
876 /* clkpll_sdm_reset=1 */
877 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
878 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
879 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
880 BL702_Delay_US(1);
881 /* clkpll_reset_fbdv=1 */
882 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
883 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
884 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
885 BL702_Delay_US(2);
886 /* clkpll_reset_fbdv=0 */
887 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
888 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
889 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
890 BL702_Delay_US(1);
891 /* clkpll_sdm_reset=0 */
892 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
893 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
894 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
895
896 return SUCCESS;
897 }
898 #endif
899 /** PLL output config **/
900 /*
901 [8] 1'h0 r/w clkpll_en_32m
902 [7] 1'h0 r/w clkpll_en_48m
903 [6] 1'h0 r/w clkpll_en_80m
904 [5] 1'h0 r/w clkpll_en_96m
905 [4] 1'h0 r/w clkpll_en_120m
906 [3] 1'h0 r/w clkpll_en_160m
907 [2] 1'h0 r/w clkpll_en_192m
908 [1] 1'h0 r/w clkpll_en_240m
909 [0] 1'h0 r/w clkpll_en_480m
910 */
911
912 /****************************************************************************/ /**
913 * @brief Enable all PLL clock
914 *
915 * @param None
916 *
917 * @return SUCCESS or ERROR
918 *
919 *******************************************************************************/
920 #ifndef BFLB_USE_ROM_DRIVER
921 __WEAK
PDS_Enable_PLL_All_Clks(void)922 BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void)
923 {
924 uint32_t tmpVal = 0;
925
926 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
927 tmpVal |= 0x1FF;
928 BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
929
930 return SUCCESS;
931 }
932 #endif
933
934 /****************************************************************************/ /**
935 * @brief Disable all PLL clock
936 *
937 * @param None
938 *
939 * @return SUCCESS or ERROR
940 *
941 *******************************************************************************/
942 #ifndef BFLB_USE_ROM_DRIVER
943 __WEAK
PDS_Disable_PLL_All_Clks(void)944 BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void)
945 {
946 uint32_t tmpVal = 0;
947
948 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
949 tmpVal &= (~0x1FF);
950 BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
951
952 return SUCCESS;
953 }
954 #endif
955
956 /****************************************************************************/ /**
957 * @brief Enable PLL clock
958 *
959 * @param pllClk: PLL clock type
960 *
961 * @return SUCCESS or ERROR
962 *
963 *******************************************************************************/
964 #ifndef BFLB_USE_ROM_DRIVER
965 __WEAK
PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)966 BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
967 {
968 uint32_t tmpVal = 0;
969
970 /* Check parameter*/
971 CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
972
973 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
974 tmpVal |= (1 << pllClk);
975 BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
976
977 return SUCCESS;
978 }
979 #endif
980
981 /****************************************************************************/ /**
982 * @brief Disable PLL clock
983 *
984 * @param pllClk: PLL clock type
985 *
986 * @return SUCCESS or ERROR
987 *
988 *******************************************************************************/
989 #ifndef BFLB_USE_ROM_DRIVER
990 __WEAK
PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)991 BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
992 {
993 uint32_t tmpVal = 0;
994
995 /* Check parameter*/
996 CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
997
998 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
999 tmpVal &= (~(1 << pllClk));
1000 BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
1001
1002 return SUCCESS;
1003 }
1004 #endif
1005
1006 /****************************************************************************/ /**
1007 * @brief Power off PLL
1008 *
1009 * @param None
1010 *
1011 * @return SUCCESS or ERROR
1012 *
1013 *******************************************************************************/
1014 #ifndef BFLB_USE_ROM_DRIVER
1015 __WEAK
PDS_Power_Off_PLL(void)1016 BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void)
1017 {
1018 uint32_t tmpVal = 0;
1019
1020 /* pu_clkpll_sfreg=0 */
1021 /* pu_clkpll=0 */
1022 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
1023 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
1024 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL);
1025 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
1026
1027 /* clkpll_pu_cp=0 */
1028 /* clkpll_pu_pfd=0 */
1029 /* clkpll_pu_fbdv=0 */
1030 /* clkpll_pu_postdiv=0 */
1031 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
1032 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
1033 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
1034 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
1035 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
1036 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
1037
1038 return SUCCESS;
1039 }
1040 #endif
1041
1042 /****************************************************************************/ /**
1043 * @brief Set Audio PLL clock
1044 *
1045 * @param audioPLLFreq: Audio PLL sel frequency , have two vaild input 12.288 or 11.289 MHZ
1046 *
1047 * @return SUCCESS or ERROR
1048 *
1049 *******************************************************************************/
1050 __WEAK
PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq)1051 BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq)
1052 {
1053 uint32_t sdmin_table[] = { 0x374BC6, 0x32CCED, 0x32CCED, 0x6E978D, 0x6C0000, 0x3E8000};
1054 uint32_t tmpVal = 0;
1055
1056 CHECK_PARAM(IS_PDS_AUDIO_PLL_TYPE(audioPLLFreq));
1057
1058 /*set PDS_CLKPLL_REFDIV_RATIO as 0x2 */
1059 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
1060 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 0x2);
1061 BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
1062
1063 /*set clkpll_sdmin as sdmin*/
1064 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
1065 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, (uint32_t)sdmin_table[audioPLLFreq % (sizeof(sdmin_table) / sizeof(sdmin_table[0]))]);
1066
1067 BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
1068
1069 /*reset pll */
1070 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
1071
1072 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL_SFREG, 1);
1073 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
1074
1075 BL702_Delay_MS(10);
1076
1077 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL, 1);
1078 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
1079
1080 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 1);
1081 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
1082
1083 BL702_Delay_MS(10);
1084
1085 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 0);
1086 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
1087
1088 /*set div for audio pll */
1089 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
1090
1091 if (audioPLLFreq != AUDIO_PLL_5644800_HZ) {
1092 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 36);
1093 } else {
1094 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 72);
1095 }
1096
1097 BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
1098
1099 return SUCCESS;
1100 }
1101
1102 /****************************************************************************/ /**
1103 * @brief PDS software reset
1104 *
1105 * @param None
1106 *
1107 * @return SUCCESS or ERROR
1108 *
1109 *******************************************************************************/
1110 #ifndef BFLB_USE_ROM_DRIVER
1111 __WEAK
PDS_Reset(void)1112 void ATTR_TCM_SECTION PDS_Reset(void)
1113 {
1114 uint32_t tmpVal = 0;
1115
1116 tmpVal = *(uint32_t *)0x40000010;
1117 tmpVal = tmpVal | (1 << 14);
1118 *(uint32_t *)0x40000010 = tmpVal;
1119
1120 tmpVal = *(uint32_t *)0x40000010;
1121 tmpVal = tmpVal & ~(1 << 14);
1122 *(uint32_t *)0x40000010 = tmpVal;
1123 }
1124 #endif
1125
1126 /****************************************************************************/ /**
1127 * @brief Enable power down sleep
1128 *
1129 * @param cfg: power down sleep configuration 1
1130 * @param pdsSleepCnt: power down sleep count cycle
1131 *
1132 * @return SUCCESS or ERROR
1133 *
1134 *******************************************************************************/
1135 #ifndef BFLB_USE_ROM_DRIVER
1136 __WEAK
PDS_Enable(PDS_CFG_Type * cfg,uint32_t pdsSleepCnt)1137 void ATTR_TCM_SECTION PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt)
1138 {
1139 uint32_t *p = (uint32_t *)cfg;
1140
1141 if (pdsSleepCnt - PDS_WARMUP_CNT <= 0) {
1142 return;
1143 }
1144
1145 BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_CNT);
1146
1147 /* Set PDS control register */
1148 BL_WR_REG(PDS_BASE, PDS_CTL, *p);
1149 }
1150 #endif
1151
1152 /****************************************************************************/ /**
1153 * @brief PDS Auto mode wake up counter config
1154 *
1155 * @param sleepDuration: sleep time, total pds = sleep_duration + max_warmup_cnt (32K clock cycles),
1156 * recommend maxWarmCnt*N+2
1157 *
1158 * @return None
1159 *
1160 *******************************************************************************/
1161 #ifndef BFLB_USE_ROM_DRIVER
1162 __WEAK
PDS_Auto_Time_Config(uint32_t sleepDuration)1163 void ATTR_TCM_SECTION PDS_Auto_Time_Config(uint32_t sleepDuration)
1164 {
1165 /* PDS_TIME1 */
1166 BL_WR_REG(PDS_BASE, PDS_TIME1, sleepDuration);
1167 }
1168 #endif
1169
1170 /****************************************************************************/ /**
1171 * @brief PDS Auto mode config and enable
1172 *
1173 * @param powerCfg: PDS Auto mode power domain config
1174 * @param normalCfg: PDS Auto mode power normal config
1175 * @param enable: PDS Auto mode Enable or Disable
1176 *
1177 * @return None
1178 *
1179 *******************************************************************************/
1180 #ifndef BFLB_USE_ROM_DRIVER
1181 __WEAK
PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type * powerCfg,PDS_AUTO_NORMAL_CFG_Type * normalCfg,BL_Fun_Type enable)1182 void ATTR_TCM_SECTION PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable)
1183 {
1184 uint32_t pdsCtl = 0;
1185
1186 CHECK_PARAM(IS_PDS_LDO_VOLTAGE_TYPE(normalCfg->vddcoreVol));
1187
1188 /* power config */
1189 pdsCtl |= (powerCfg->mbgPower << 31) |
1190 (powerCfg->ldo18rfPower << 30) |
1191 (powerCfg->sfregPower << 29) |
1192 (powerCfg->pllPower << 28) |
1193 (powerCfg->cpu0Power << 19) |
1194 (powerCfg->rc32mPower << 17) |
1195 (powerCfg->xtalPower << 14) |
1196 (powerCfg->allPower << 13) |
1197 (powerCfg->isoPower << 11) |
1198 (powerCfg->bzPower << 10) |
1199 (powerCfg->sramDisStanby << 9) |
1200 (powerCfg->cgPower << 8) |
1201 (powerCfg->cpu1Power << 7) |
1202 (powerCfg->usbPower << 3);
1203 pdsCtl = BL_SET_REG_BITS_VAL(pdsCtl, PDS_CR_PDS_LDO_VOL, normalCfg->vddcoreVol);
1204 pdsCtl |= (normalCfg->vddcoreVolEn << 18) |
1205 (normalCfg->cpu0NotNeedWFI << 21) |
1206 (normalCfg->cpu1NotNeedWFI << 20) |
1207 (normalCfg->busReset << 16) |
1208 (normalCfg->disIrqWakeUp << 15) |
1209 (normalCfg->powerOffXtalForever << 2) |
1210 (normalCfg->sleepForever << 1);
1211 BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl);
1212
1213 pdsCtl = BL_RD_REG(PDS_BASE, PDS_CTL);
1214
1215 if (enable) {
1216 pdsCtl |= (1 << 0);
1217 } else {
1218 pdsCtl &= ~(1 << 0);
1219 }
1220
1221 BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl);
1222 }
1223 #endif
1224
1225 /****************************************************************************/ /**
1226 * @brief PDS force turn off XXX domain
1227 *
1228 * @param domain: PDS domain
1229 *
1230 * @return None
1231 *
1232 *******************************************************************************/
1233 #ifndef BFLB_USE_ROM_DRIVER
1234 __WEAK
PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain)1235 void ATTR_TCM_SECTION PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain)
1236 {
1237 uint32_t tmpVal = 0;
1238
1239 /* memory sleep */
1240 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1241 tmpVal |= 1 << (domain + PDS_FORCE_MEM_STBY_OFFSET);
1242 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1243
1244 /* gate clock */
1245 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1246 tmpVal |= 1 << (domain + PDS_FORCE_GATE_CLK_OFFSET);
1247 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1248
1249 /* pds reset */
1250 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1251 tmpVal |= 1 << (domain + PDS_FORCE_PDS_RST_OFFSET);
1252 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1253
1254 /* isolation on */
1255 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1256 tmpVal |= 1 << (domain + PDS_FORCE_ISO_EN_OFFSET);
1257 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1258
1259 /* power off */
1260 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1261 tmpVal |= 1 << (domain + PDS_FORCE_PWR_OFF_OFFSET);
1262 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1263 }
1264 #endif
1265
1266 /****************************************************************************/ /**
1267 * @brief PDS force turn on XXX domain
1268 *
1269 * @param domain: PDS domain
1270 *
1271 * @return None
1272 *
1273 *******************************************************************************/
1274 #ifndef BFLB_USE_ROM_DRIVER
1275 __WEAK
PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain)1276 void ATTR_TCM_SECTION PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain)
1277 {
1278 uint32_t tmpVal = 0;
1279
1280 /* power on */
1281 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1282 tmpVal &= ~(1 << (domain + PDS_FORCE_PWR_OFF_OFFSET));
1283 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1284
1285 /* isolation off */
1286 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1287 tmpVal &= ~(1 << (domain + PDS_FORCE_ISO_EN_OFFSET));
1288 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1289
1290 /* pds de_reset */
1291 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1292 tmpVal &= ~(1 << (domain + PDS_FORCE_PDS_RST_OFFSET));
1293 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1294
1295 /* memory active */
1296 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1297 tmpVal &= ~(1 << (domain + PDS_FORCE_MEM_STBY_OFFSET));
1298 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1299
1300 /* clock on */
1301 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
1302 tmpVal &= ~(1 << (domain + PDS_FORCE_GATE_CLK_OFFSET));
1303 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
1304 }
1305 #endif
1306
1307 /****************************************************************************/ /**
1308 * @brief Power down sleep wake up interrupt handler
1309 *
1310 * @param None
1311 *
1312 * @return None
1313 *
1314 *******************************************************************************/
PDS_WAKEUP_IRQHandler(void)1315 void PDS_WAKEUP_IRQHandler(void)
1316 {
1317 for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {
1318 if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType][0] != NULL)) {
1319 pdsIntCbfArra[intType][0]();
1320 }
1321 }
1322 PDS_Set_Vddcore_GPIO_IntClear();
1323 PDS_IntClear();
1324 }
1325
1326 /****************************************************************************/ /**
1327 * @brief PDS wakeup IRQHandler install
1328 *
1329 * @param None
1330 *
1331 * @return SUCCESS or ERROR
1332 *
1333 *******************************************************************************/
PDS_WAKEUP_IRQHandler_Install(void)1334 BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void)
1335 {
1336 Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);
1337 return SUCCESS;
1338 }
1339
1340 /****************************************************************************/ /**
1341 * @brief
1342 *
1343 * @param
1344 *
1345 * @return
1346 *
1347 *******************************************************************************/
PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel)1348 BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel)
1349 {
1350 uint32_t tmpVal = 0;
1351
1352 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
1353 //clkpll_vg11_sel
1354 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_VG11_SEL, vg11Sel);
1355 BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
1356
1357 return SUCCESS;
1358 }
1359
1360 /*@} end of group PDS_Public_Functions */
1361
1362 /*@} end of group PDS */
1363
1364 /*@} end of group BL702_Peripheral_Driver */
1365