1 /** @file sys_vim.c
2 * @brief VIM Driver Inmplmentation File
3 * @date
4 * @version 03.05.02
5 *
6 */
7
8 /* (c) Texas Instruments 2009-2013, All rights reserved. */
9
10
11 #include "sys_vim.h"
12 #include "system.h"
13
14
15 /* Vim Ram Definition */
16 /** @struct vimRam
17 * @brief Vim Ram Definition
18 *
19 * This type is used to access the Vim Ram.
20 */
21 /** @typedef vimRAM_t
22 * @brief Vim Ram Type Definition
23 *
24 * This type is used to access the Vim Ram.
25 */
26 typedef volatile struct vimRam
27 {
28 t_isrFuncPTR ISR[VIM_CHANNELS + 1U];
29 } vimRAM_t;
30
31 #define vimRAM ((vimRAM_t *)0xFFF82000U)
32
33 /** @fn void vimInit(void)
34 * @brief Initializes VIM module
35 *
36 * This function initializes VIM RAM and registers
37 */
38
vimInit(void)39 void vimInit(void)
40 {
41 /* Set Fall-Back Address Parity Error Register */
42 /*VIM_FBPARERR = (uint32)&vimParityErrorHandler;*/
43
44 /* set IRQ/FIQ priorities */
45 vimREG->FIRQPR0 = SYS_FIQ
46 | (SYS_FIQ << 1U)
47 | (SYS_IRQ << 2U)
48 | (SYS_IRQ << 3U)
49 | (SYS_IRQ << 4U)
50 | (SYS_IRQ << 5U)
51 | (SYS_IRQ << 6U)
52 | (SYS_IRQ << 7U)
53 | (SYS_IRQ << 8U)
54 | (SYS_IRQ << 9U)
55 | (SYS_IRQ << 10U)
56 | (SYS_IRQ << 11U)
57 | (SYS_IRQ << 12U)
58 | (SYS_IRQ << 13U)
59 | (SYS_IRQ << 14U)
60 | (SYS_IRQ << 15U)
61 | (SYS_IRQ << 16U)
62 | (SYS_IRQ << 17U)
63 | (SYS_IRQ << 18U)
64 | (SYS_IRQ << 19U)
65 | (SYS_IRQ << 20U)
66 | (SYS_IRQ << 21U)
67 | (SYS_IRQ << 22U)
68 | (SYS_IRQ << 23U)
69 | (SYS_IRQ << 24U)
70 | (SYS_IRQ << 25U)
71 | (SYS_IRQ << 26U)
72 | (SYS_IRQ << 27U)
73 | (SYS_IRQ << 28U)
74 | (SYS_IRQ << 29U)
75 | (SYS_IRQ << 30U)
76 | (SYS_IRQ << 31U);
77
78 vimREG->FIRQPR1 = SYS_IRQ
79 | (SYS_IRQ << 1U)
80 | (SYS_IRQ << 2U)
81 | (SYS_IRQ << 3U)
82 | (SYS_IRQ << 4U)
83 | (SYS_IRQ << 5U)
84 | (SYS_IRQ << 6U)
85 | (SYS_IRQ << 7U)
86 | (SYS_IRQ << 8U)
87 | (SYS_IRQ << 9U)
88 | (SYS_IRQ << 10U)
89 | (SYS_IRQ << 11U)
90 | (SYS_IRQ << 12U)
91 | (SYS_IRQ << 13U)
92 | (SYS_IRQ << 14U)
93 | (SYS_IRQ << 15U)
94 | (SYS_IRQ << 16U)
95 | (SYS_IRQ << 17U)
96 | (SYS_IRQ << 18U)
97 | (SYS_IRQ << 19U)
98 | (SYS_IRQ << 20U)
99 | (SYS_IRQ << 21U)
100 | (SYS_IRQ << 22U)
101 | (SYS_IRQ << 23U)
102 | (SYS_IRQ << 24U)
103 | (SYS_IRQ << 25U)
104 | (SYS_IRQ << 26U)
105 | (SYS_IRQ << 27U)
106 | (SYS_IRQ << 28U)
107 | (SYS_IRQ << 29U)
108 | (SYS_IRQ << 30U)
109 | (SYS_IRQ << 31U);
110
111
112 vimREG->FIRQPR2 = SYS_IRQ
113 | (SYS_IRQ << 1U)
114 | (SYS_IRQ << 2U)
115 | (SYS_IRQ << 3U)
116 | (SYS_IRQ << 4U)
117 | (SYS_IRQ << 5U)
118 | (SYS_IRQ << 6U)
119 | (SYS_IRQ << 7U)
120 | (SYS_IRQ << 8U)
121 | (SYS_IRQ << 9U)
122 | (SYS_IRQ << 10U)
123 | (SYS_IRQ << 11U)
124 | (SYS_IRQ << 12U)
125 | (SYS_IRQ << 13U)
126 | (SYS_IRQ << 14U)
127 | (SYS_IRQ << 15U)
128 | (SYS_IRQ << 16U)
129 | (SYS_IRQ << 17U)
130 | (SYS_IRQ << 18U)
131 | (SYS_IRQ << 19U)
132 | (SYS_IRQ << 20U)
133 | (SYS_IRQ << 21U)
134 | (SYS_IRQ << 22U)
135 | (SYS_IRQ << 23U)
136 | (SYS_IRQ << 24U)
137 | (SYS_IRQ << 25U)
138 | (SYS_IRQ << 26U)
139 | (SYS_IRQ << 27U)
140 | (SYS_IRQ << 28U)
141 | (SYS_IRQ << 29U)
142 | (SYS_IRQ << 30U)
143 | (SYS_IRQ << 31U);
144
145 vimREG->FIRQPR3 = SYS_IRQ
146 | (SYS_IRQ << 1U)
147 | (SYS_IRQ << 2U)
148 | (SYS_IRQ << 3U)
149 | (SYS_IRQ << 4U)
150 | (SYS_IRQ << 5U)
151 | (SYS_IRQ << 6U)
152 | (SYS_IRQ << 7U)
153 | (SYS_IRQ << 8U)
154 | (SYS_IRQ << 9U)
155 | (SYS_IRQ << 10U)
156 | (SYS_IRQ << 11U)
157 | (SYS_IRQ << 12U)
158 | (SYS_IRQ << 13U)
159 | (SYS_IRQ << 14U)
160 | (SYS_IRQ << 15U)
161 | (SYS_IRQ << 16U)
162 | (SYS_IRQ << 17U)
163 | (SYS_IRQ << 18U)
164 | (SYS_IRQ << 19U)
165 | (SYS_IRQ << 20U)
166 | (SYS_IRQ << 21U)
167 | (SYS_IRQ << 22U)
168 | (SYS_IRQ << 23U)
169 | (SYS_IRQ << 24U)
170 | (SYS_IRQ << 25U)
171 | (SYS_IRQ << 26U)
172 | (SYS_IRQ << 27U)
173 | (SYS_IRQ << 28U)
174 | (SYS_IRQ << 29U)
175 | (SYS_IRQ << 30U)
176 | (SYS_IRQ << 31U);
177
178
179 /* enable interrupts */
180 vimREG->REQMASKSET0 = 1U
181 | (1U << 1U)
182 | (0U << 2U)
183 | (0U << 3U)
184 | (0U << 4U)
185 | (1U << 5U)
186 | (0U << 6U)
187 | (0U << 7U)
188 | (0U << 8U)
189 | (0U << 9U)
190 | (0U << 10U)
191 | (0U << 11U)
192 | (0U << 12U)
193 | (1U << 13U)
194 | (0U << 14U)
195 | (0U << 15U)
196 | (0U << 16U)
197 | (0U << 17U)
198 | (0U << 18U)
199 | (0U << 19U)
200 | (0U << 20U)
201 | (0U << 21U)
202 | (0U << 22U)
203 | (0U << 23U)
204 | (0U << 24U)
205 | (0U << 25U)
206 | (0U << 26U)
207 | (0U << 27U)
208 | (0U << 28U)
209 | (0U << 29U)
210 | (0U << 30U)
211 | (0U << 31U);
212
213 vimREG->REQMASKSET1 = 0U
214 | (0U << 1U)
215 | (0U << 2U)
216 | (0U << 3U)
217 | (0U << 4U)
218 | (0U << 5U)
219 | (0U << 6U)
220 | (0U << 7U)
221 | (0U << 8U)
222 | (0U << 9U)
223 | (0U << 10U)
224 | (0U << 11U)
225 | (0U << 12U)
226 | (0U << 13U)
227 | (0U << 14U)
228 | (0U << 15U)
229 | (0U << 16U)
230 | (0U << 17U)
231 | (0U << 18U)
232 | (0U << 19U)
233 | (0U << 20U)
234 | (0U << 21U)
235 | (0U << 22U)
236 | (0U << 23U)
237 | (0U << 24U)
238 | (0U << 25U)
239 | (0U << 26U)
240 | (0U << 27U)
241 | (0U << 28U)
242 | (0U << 29U)
243 | (0U << 30U)
244 | (0U << 31U);
245
246 vimREG->REQMASKSET2 = 0U
247 | (0U << 1U)
248 | (0U << 2U)
249 | (0U << 3U)
250 | (0U << 4U)
251 | (0U << 5U)
252 | (0U << 6U)
253 | (0U << 7U)
254 | (0U << 8U)
255 | (0U << 9U)
256 | (0U << 10U)
257 | (0U << 11U)
258 | (0U << 12U)
259 | (0U << 13U)
260 | (0U << 14U)
261 | (0U << 15U)
262 | (0U << 16U)
263 | (0U << 17U)
264 | (0U << 18U)
265 | (0U << 19U)
266 | (0U << 20U)
267 | (0U << 21U)
268 | (0U << 22U)
269 | (0U << 23U)
270 | (0U << 24U)
271 | (0U << 25U)
272 | (0U << 26U)
273 | (0U << 27U)
274 | (0U << 28U)
275 | (0U << 29U)
276 | (0U << 30U)
277 | (0U << 31U);
278
279 vimREG->REQMASKSET3 = 0U
280 | (0U << 1U)
281 | (0U << 2U)
282 | (0U << 3U)
283 | (0U << 4U)
284 | (0U << 5U)
285 | (0U << 6U)
286 | (0U << 7U)
287 | (0U << 8U)
288 | (0U << 9U)
289 | (0U << 10U)
290 | (0U << 11U)
291 | (0U << 12U)
292 | (0U << 13U)
293 | (0U << 14U)
294 | (0U << 15U)
295 | (0U << 16U)
296 | (0U << 17U)
297 | (0U << 18U)
298 | (0U << 19U)
299 | (0U << 20U)
300 | (0U << 21U)
301 | (0U << 22U)
302 | (0U << 23U)
303 | (0U << 24U)
304 | (0U << 25U)
305 | (0U << 26U)
306 | (0U << 27U)
307 | (0U << 28U)
308 | (0U << 29U)
309 | (0U << 30U)
310 | (0U << 31U);
311 }
312
313 /** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
314 * @brief Map selected interrupt request to the selected channel
315 *
316 * @param[in] request: Interrupt request number 2..95
317 * @param[in] channel: VIM Channel number 2..95
318 * @param[in] handler: Address of the interrupt handler
319 *
320 * This function will map selected interrupt request to the selected channel.
321 *
322 */
vimChannelMap(uint32 request,uint32 channel,t_isrFuncPTR handler)323 void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
324 {
325 uint32 i,j;
326 i = channel >> 2U; /* Find the register to configure */
327 j = channel -(i<<2U); /* Find the offset of the type */
328 j = 3U-j; /* reverse the byte order */
329 j = j<<3U; /* find the bit location */
330
331 /*Mapping the required interrupt request to the required channel*/
332 vimREG->CHANCTRL[i] &= ~(0xFFU << j);
333 vimREG->CHANCTRL[i] |= (request << j);
334
335 /*Updating VIMRAM*/
336 vimRAM->ISR[channel+1] = handler;
337 }
338
339 /** @fn void vimEnableInterrupt(uint32 channel, boolean inttype)
340 * @brief Enable interrupt for the the selected channel
341 *
342 * @param[in] channel: VIM Channel number 2..95
343 * @param[in] handler: Interrupt type
344 * - SYS_IRQ: Selected channel will be enabled as IRQ
345 * - SYS_FIQ: Selected channel will be enabled as FIQ
346 *
347 * This function will enable interrupt for the selected channel.
348 *
349 */
vimEnableInterrupt(uint32 channel,boolean inttype)350 void vimEnableInterrupt(uint32 channel, boolean inttype)
351 {
352 if (channel >= 64)
353 {
354 if(inttype == SYS_IRQ)
355 {
356 vimREG->FIRQPR2 &= ~(1 << (channel-64));
357 }
358 else
359 {
360 vimREG->FIRQPR2 |= 1 << (channel-64);
361 }
362 vimREG->REQMASKSET2 = 1 << (channel-64);
363 }
364 else if (channel >= 32)
365 {
366 if(inttype == SYS_IRQ)
367 {
368 vimREG->FIRQPR1 &= ~(1 << (channel-32));
369 }
370 else
371 {
372 vimREG->FIRQPR1 |= 1 << (channel-32);
373 }
374 vimREG->REQMASKSET1 = 1 << (channel-32);
375 }
376 else if (channel >= 2)
377 {
378 if(inttype == SYS_IRQ)
379 {
380 vimREG->FIRQPR0 &= ~(1 << channel);
381 }
382 else
383 {
384 vimREG->FIRQPR0 |= 1 << channel;
385 }
386 vimREG->REQMASKSET0 = 1 << channel;
387 }
388 else
389 {
390
391 }
392 }
393
394 /** @fn void vimDisableInterrupt(uint32 channel)
395 * @brief Disable interrupt for the the selected channel
396 *
397 * @param[in] channel: VIM Channel number 2..95
398 *
399 * This function will disable interrupt for the selected channel.
400 *
401 */
vimDisableInterrupt(uint32 channel)402 void vimDisableInterrupt(uint32 channel)
403 {
404 if (channel >= 64)
405 {
406 vimREG->REQMASKCLR2 = 1 << (channel-64);
407 }
408 else if (channel >=32)
409 {
410 vimREG->REQMASKCLR1 = 1 << (channel-32);
411 }
412 else if (channel >= 2)
413 {
414 vimREG->REQMASKCLR0 = 1 << channel;
415 }
416 else
417 {
418
419 }
420 }
421
422 /** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
423 * @brief Get the initial or current values of the configuration registers
424 *
425 * @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
426 * @param[in] type: whether initial or current value of the configuration registers need to be stored
427 * - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
428 * - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
429 *
430 * This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
431 *
432 */
433
vimGetConfigValue(vim_config_reg_t * config_reg,config_value_type_t type)434 void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
435 {
436 uint32 temp[24U] = VIM_CHANCTRL_CONFIGVALUE;
437 uint32 i;
438
439 if (type == InitialValue)
440 {
441 config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE;
442 config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE;
443 config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE;
444 config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE;
445 config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE;
446 config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE;
447 config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE;
448 config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE;
449 config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE;
450 config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE;
451 config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE;
452 config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE;
453 config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE;
454
455 for (i=0U; i<24U;i++)
456 {
457 config_reg->CONFIG_CHANCTRL[i] = temp[i];
458 }
459 }
460 else
461 {
462 config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0;
463 config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1;
464 config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2;
465 config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3;
466 config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0;
467 config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1;
468 config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2;
469 config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3;
470 config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0;
471 config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1;
472 config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2;
473 config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3;
474 config_reg->CONFIG_CAPEVT = vimREG->CAPEVT;
475
476 for (i=0U; i<24U; i++)
477 {
478 config_reg->CONFIG_CHANCTRL[i] = vimREG->CHANCTRL[i];
479 }
480
481
482 }
483 }
484
485
486 #if 0
487 #pragma CODE_STATE(vimParityErrorHandler, 32)
488 #pragma INTERRUPT(vimParityErrorHandler, IRQ)
489
490 void vimParityErrorHandler(void)
491 {
492 /* Identify the corrupted address */
493 uint32 error_addr = VIM_ADDERR;
494
495 /* Identify the channel number */
496 uint32 error_channel = ((error_addr & 0x1FF) >> 2) - 1;
497
498 /* Correct the corrupted location */
499 vimRAM->ISR[error_channel + 1] = s_vim_init[error_channel + 1];
500
501 /* Clear Parity Error Flag */
502 VIM_PARFLG = 1;
503
504 /* Disable and enable the highest priority pending channel */
505 sint32 channel;
506 channel = vimREG->FIQINDEX - 1;
507 if (vimREG->FIQINDEX != 0)
508 {
509 channel = vimREG->FIQINDEX - 1;
510 }
511 else
512 {
513 channel = vimREG->IRQINDEX - 1;
514 }
515 if (channel >= 0)
516 {
517 if (channel < 32)
518 {
519 vimREG->REQMASKCLR0 = 1 << channel;
520 vimREG->REQMASKSET0 = 1 << channel;
521 }
522 else if (channel < 64)
523 {
524 vimREG->REQMASKCLR1 = 1 << (channel-32);
525 vimREG->REQMASKSET1 = 1 << (channel-32);
526 }
527 else
528 {
529 vimREG->REQMASKCLR2 = 1 << (channel-64);
530 vimREG->REQMASKSET2 = 1 << (channel-64);
531 }
532 }
533 }
534 #endif
535