1 /*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2021-08-31 AisinoChip first version
9 */
10
11 #include "board.h"
12 #include <rtdevice.h>
13
14 #ifdef RT_USING_SPI
15
16 #if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2)
17
18 #include "spi_config.h"
19
20 enum
21 {
22 #ifdef BSP_USING_SPI1
23 SPI1_INDEX,
24 #endif
25 #ifdef BSP_USING_SPI2
26 SPI2_INDEX,
27 #endif
28 SPI_MAX_INDEX
29 };
30
31 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
32 struct dma_config
33 {
34 DMA_Channel_TypeDef *Instance;
35 rt_uint32_t dma_rcc;
36 IRQn_Type dma_irq;
37 rt_uint32_t channel;
38 rt_uint32_t request;
39 };
40 #endif
41
42 struct acm32_hw_spi_cs
43 {
44 enum_GPIOx_t GPIOx;
45 uint16_t GPIO_Pin;
46 };
47
48 struct acm32_spi_config
49 {
50 SPI_TypeDef *Instance;
51 char *bus_name;
52 IRQn_Type irq_type;
53 enum_Enable_ID_t enable_id;
54 #if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
55 struct dma_config *dma_rx;
56 #endif
57 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA)
58 struct dma_config *dma_tx;
59 #endif
60
61 enum_GPIOx_t cs_port;
62 rt_uint32_t cs_pin;
63 rt_uint32_t cs_alternate;
64
65 enum_GPIOx_t sck_port;
66 rt_uint32_t sck_pin;
67 rt_uint32_t sck_alternate;
68
69 enum_GPIOx_t mosi_port;
70 rt_uint32_t mosi_pin;
71 rt_uint32_t mosi_alternate;
72
73 enum_GPIOx_t miso_port;
74 rt_uint32_t miso_pin;
75 rt_uint32_t miso_alternate;
76
77 enum_GPIOx_t wp_port;
78 rt_uint32_t wp_pin;
79 rt_uint32_t wp_alternate;
80
81 enum_GPIOx_t hold_port;
82 rt_uint32_t hold_pin;
83 rt_uint32_t hold_alternate;
84 };
85
86 struct acm32_spi_device
87 {
88 rt_uint32_t pin;
89 char *bus_name;
90 char *device_name;
91 };
92
93 #define SPI_USING_RX_DMA_FLAG (1<<0)
94 #define SPI_USING_TX_DMA_FLAG (1<<1)
95
96 struct acm32_spi
97 {
98 SPI_HandleTypeDef handle;
99 struct acm32_spi_config *config;
100 struct rt_spi_configuration *cfg;
101
102 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
103 struct
104 {
105 #if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
106 DMA_HandleTypeDef handle_rx;
107 #endif
108 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA)
109 DMA_HandleTypeDef handle_tx;
110 #endif
111 } dma;
112
113 rt_uint8_t spi_dma_flag;
114 #endif
115
116 struct rt_spi_bus spi_bus;
117 };
118
119 static struct acm32_spi_config spi_config[] =
120 {
121 #ifdef BSP_USING_SPI1
122 SPI1_BUS_CONFIG,
123 #endif
124
125 #ifdef BSP_USING_SPI2
126 SPI2_BUS_CONFIG,
127 #endif
128 };
129
130 static struct acm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
131
acm32_spi_init(struct acm32_spi * spi_drv,struct rt_spi_configuration * cfg)132 static rt_err_t acm32_spi_init(struct acm32_spi *spi_drv, struct rt_spi_configuration *cfg)
133 {
134 RT_ASSERT(spi_drv != RT_NULL);
135 RT_ASSERT(cfg != RT_NULL);
136
137 SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
138
139 if (cfg->mode & RT_SPI_SLAVE)
140 {
141 spi_handle->Init.SPI_Mode = SPI_MODE_SLAVE;
142 }
143 else
144 {
145 spi_handle->Init.SPI_Mode = SPI_MODE_MASTER;
146 }
147
148 spi_handle->Init.X_Mode = SPI_1X_MODE;
149 if (cfg->mode & RT_SPI_3WIRE)
150 {
151 return -RT_EINVAL;
152 }
153
154 if (cfg->data_width != 8)
155 {
156 return -RT_EINVAL;
157 }
158
159 switch (cfg->mode & RT_SPI_MODE_3)
160 {
161 case RT_SPI_MODE_0:
162 spi_handle->Init.SPI_Work_Mode = SPI_WORK_MODE_0;
163 break;
164 case RT_SPI_MODE_1:
165 spi_handle->Init.SPI_Work_Mode = SPI_WORK_MODE_1;
166 break;
167 case RT_SPI_MODE_2:
168 spi_handle->Init.SPI_Work_Mode = SPI_WORK_MODE_2;
169 break;
170 case RT_SPI_MODE_3:
171 spi_handle->Init.SPI_Work_Mode = SPI_WORK_MODE_3;
172 break;
173 }
174
175 if (cfg->mode & RT_SPI_MSB)
176 {
177 spi_handle->Init.First_Bit = SPI_FIRSTBIT_MSB;
178 }
179 else
180 {
181 spi_handle->Init.First_Bit = SPI_FIRSTBIT_LSB;
182 }
183
184 uint32_t SPI_APB_CLOCK;
185 SPI_APB_CLOCK = System_Get_SystemClock();
186
187 if (cfg->max_hz >= SPI_APB_CLOCK / 4)
188 {
189 spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_4;
190 }
191 else if (cfg->max_hz >= SPI_APB_CLOCK / 8)
192 {
193 spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_8;
194 }
195 else if (cfg->max_hz >= SPI_APB_CLOCK / 16)
196 {
197 spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_16;
198 }
199 else if (cfg->max_hz >= SPI_APB_CLOCK / 32)
200 {
201 spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_32;
202 }
203 else if (cfg->max_hz >= SPI_APB_CLOCK / 64)
204 {
205 spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_64;
206 }
207 else if (cfg->max_hz >= SPI_APB_CLOCK / 128)
208 {
209 spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_128;
210 }
211 else
212 {
213 /* min prescaler 254 */
214 spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_254;
215 }
216
217 if (HAL_SPI_Init(spi_handle) != HAL_OK)
218 {
219 return -RT_EIO;
220 }
221
222 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
223 #if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
224 /* DMA configuration */
225 if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
226 {
227 HAL_DMA_Init(&spi_drv->dma.handle_rx);
228
229 __HAL_LINK_DMA(spi_drv->handle, HDMA_Rx, spi_drv->dma.handle_rx);
230 }
231 #endif
232
233 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA)
234 if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
235 {
236 HAL_DMA_Init(&spi_drv->dma.handle_tx);
237
238 __HAL_LINK_DMA(spi_drv->handle, HDMA_Tx, spi_drv->dma.handle_tx);
239 }
240 #endif
241 #endif
242
243 return RT_EOK;
244 }
245
spixfer(struct rt_spi_device * device,struct rt_spi_message * message)246 static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
247 {
248 HAL_StatusTypeDef state;
249 rt_uint8_t *recv_buf;
250 const rt_uint8_t *send_buf;
251 rt_uint32_t timeout = 1000;
252
253 RT_ASSERT(device != RT_NULL);
254 RT_ASSERT(device->bus != RT_NULL);
255 RT_ASSERT(device->bus->parent.user_data != RT_NULL);
256 RT_ASSERT(message != RT_NULL);
257
258 struct acm32_spi *spi_drv = rt_container_of(device->bus, struct acm32_spi, spi_bus);
259 SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
260 struct acm32_hw_spi_cs *cs = device->parent.user_data;
261
262 if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS))
263 {
264 HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_CLEAR);
265 }
266
267 recv_buf = message->recv_buf;
268 send_buf = message->send_buf;
269
270 /* start once data exchange in DMA mode */
271 if (message->send_buf && message->recv_buf)
272 {
273 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
274 if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG))
275 {
276 if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
277 {
278 state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, message->length);
279 while (HAL_SPI_GetTxState(spi_handle) != SPI_TX_STATE_IDLE);
280 }
281 else
282 {
283 state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, message->length, timeout);
284 }
285
286 if (state == HAL_OK)
287 {
288 if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
289 {
290 state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, message->length);
291 while (HAL_SPI_GetRxState(spi_handle) != SPI_RX_STATE_IDLE);
292 }
293 else
294 {
295 state = HAL_SPI_Receive_IT(spi_handle, (uint8_t *)recv_buf, message->length);
296 while (HAL_SPI_GetRxState(spi_handle) != SPI_RX_STATE_IDLE);
297 }
298 }
299 }
300 else
301 #endif
302 {
303 state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, message->length, timeout);
304 }
305
306 if (state != HAL_OK)
307 {
308 message->length = 0;
309 }
310 }
311 else if (message->send_buf)
312 {
313 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA)
314 if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
315 {
316 state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, message->length);
317 while (HAL_SPI_GetTxState(spi_handle) != SPI_TX_STATE_IDLE);
318 }
319 else
320 #endif
321 {
322 state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, message->length, 0);
323 }
324 if (state != HAL_OK)
325 {
326 message->length = 0;
327 }
328 }
329 else
330 {
331 memset((uint8_t *)recv_buf, 0xff, message->length);
332 #if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
333 if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
334 {
335 state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, message->length);
336 while (HAL_SPI_GetRxState(spi_handle) != SPI_RX_STATE_IDLE);
337 }
338 else
339 #endif
340 {
341 rt_kprintf("expect %d bytes\n", message->length);
342 state = HAL_SPI_Receive_IT(spi_handle, (uint8_t *)recv_buf, message->length);
343 while (HAL_SPI_GetRxState(spi_handle) != SPI_RX_STATE_IDLE);
344 rt_kprintf("recv %d bytes\n", spi_handle->Rx_Count);
345 }
346 if (state != HAL_OK)
347 {
348 message->length = 0;
349 }
350 }
351
352 if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
353 {
354 HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
355 }
356
357 return message->length;
358 }
359
_configure(struct rt_spi_device * device,struct rt_spi_configuration * configuration)360 static rt_err_t _configure(struct rt_spi_device *device,
361 struct rt_spi_configuration *configuration)
362 {
363 RT_ASSERT(device != RT_NULL);
364 RT_ASSERT(configuration != RT_NULL);
365
366 struct acm32_spi *spi_drv = rt_container_of(device->bus, struct acm32_spi, spi_bus);
367 spi_drv->cfg = configuration;
368
369 return acm32_spi_init(spi_drv, configuration);
370 }
371
372 static const struct rt_spi_ops acm_spi_ops =
373 {
374 .configure = _configure,
375 .xfer = spixfer,
376 };
377
rt_hw_spi_bus_init(void)378 static int rt_hw_spi_bus_init(void)
379 {
380 rt_err_t result = RT_EOK;
381
382 for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
383 {
384 spi_bus_obj[i].config = &spi_config[i];
385 spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
386 spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
387
388 #if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
389 if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
390 {
391 /* Configure the DMA handler for Transmission process */
392 spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
393 spi_bus_obj[i].dma.handle_rx.Init.Data_Flow = DMA_DATA_FLOW_P2M;
394 spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
395 spi_bus_obj[i].dma.handle_rx.Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE;
396 spi_bus_obj[i].dma.handle_rx.Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE;
397 spi_bus_obj[i].dma.handle_rx.Init.Request_ID = spi_config[i].dma_rx->request;
398 spi_bus_obj[i].dma.handle_rx.Init.Source_Width = DMA_SRC_WIDTH_BYTE;
399 spi_bus_obj[i].dma.handle_rx.Init.Desination_Width = DMA_DST_WIDTH_BYTE;
400 spi_bus_obj[i].dma.handle_rx.DMA_ITC_Callback = NULL;
401 spi_bus_obj[i].dma.handle_rx.DMA_IE_Callback = NULL;
402 }
403 #endif
404
405 #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA)
406 if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
407 {
408 spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
409 spi_bus_obj[i].dma.handle_tx.Init.Data_Flow = DMA_DATA_FLOW_M2P;
410 spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
411 spi_bus_obj[i].dma.handle_tx.Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_ENABLE;
412 spi_bus_obj[i].dma.handle_tx.Init.Desination_Inc = DMA_DST_ADDR_INCREASE_DISABLE;
413 spi_bus_obj[i].dma.handle_tx.Init.Request_ID = spi_config[i].dma_tx->request;
414 spi_bus_obj[i].dma.handle_tx.Init.Source_Width = DMA_SRC_WIDTH_BYTE;
415 spi_bus_obj[i].dma.handle_tx.Init.Desination_Width = DMA_DST_WIDTH_BYTE;
416 spi_bus_obj[i].dma.handle_tx.DMA_ITC_Callback = NULL;
417 spi_bus_obj[i].dma.handle_tx.DMA_IE_Callback = NULL;
418 }
419 #endif
420
421 result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &acm_spi_ops);
422 RT_ASSERT(result == RT_EOK);
423 }
424
425 return result;
426 }
427
428 #if defined(BSP_USING_SPI1)
SPI1_IRQHandler(void)429 void SPI1_IRQHandler(void)
430 {
431 /* enter interrupt */
432 rt_interrupt_enter();
433
434 HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
435
436 /* leave interrupt */
437 rt_interrupt_leave();
438 }
439 #endif
440
441 #if defined(BSP_USING_SPI2)
SPI2_IRQHandler(void)442 void SPI2_IRQHandler(void)
443 {
444 /* enter interrupt */
445 rt_interrupt_enter();
446
447 HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
448
449 /* leave interrupt */
450 rt_interrupt_leave();
451 }
452 #endif
453
acm32_get_dma_info(void)454 static void acm32_get_dma_info(void)
455 {
456 #ifdef BSP_SPI1_RX_USING_DMA
457 spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
458 static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
459 spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
460 #endif
461 #ifdef BSP_SPI1_TX_USING_DMA
462 spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
463 static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
464 spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
465 #endif
466
467 #ifdef BSP_SPI2_RX_USING_DMA
468 spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
469 static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
470 spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
471 #endif
472 #ifdef BSP_SPI2_TX_USING_DMA
473 spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
474 static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
475 spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
476 #endif
477 }
478
rt_hw_spi_init(void)479 int rt_hw_spi_init(void)
480 {
481 acm32_get_dma_info();
482 return rt_hw_spi_bus_init();
483 }
484 INIT_BOARD_EXPORT(rt_hw_spi_init);
485
get_gpio_alternate(enum_GPIOx_t gpio_port,uint16_t gpio_pin)486 static uint32_t get_gpio_alternate(enum_GPIOx_t gpio_port, uint16_t gpio_pin)
487 {
488 /* SPI1_CS : PA2->AF3 PA4->AF1 PA15->AF1 PB0->AF1 PB11->AF5 */
489 /* SPI2_CS : PA8->AF4 PB9->AF4 PB12->AF4 */
490 if (gpio_port == GPIOA || gpio_port == GPIOB)
491 {
492 if (gpio_port == GPIOA)
493 {
494 switch (gpio_pin)
495 {
496 case GPIO_PIN_2:
497 return GPIO_FUNCTION_3;
498 case GPIO_PIN_4:
499 return GPIO_FUNCTION_1;
500 case GPIO_PIN_8:
501 return GPIO_FUNCTION_4;
502 case GPIO_PIN_15:
503 return GPIO_FUNCTION_1;
504 default:
505 return RT_UINT32_MAX;
506 }
507 }
508 else
509 {
510 switch (gpio_pin)
511 {
512 case GPIO_PIN_0:
513 return GPIO_FUNCTION_1;
514 case GPIO_PIN_9:
515 return GPIO_FUNCTION_4;
516 case GPIO_PIN_11:
517 return GPIO_FUNCTION_5;
518 case GPIO_PIN_12:
519 return GPIO_FUNCTION_4;
520 default:
521 return RT_UINT32_MAX;
522 }
523 }
524 }
525
526 return RT_UINT32_MAX;
527 }
528
529 /**
530 * Attach the spi device to SPI bus, this function must be used after initialization.
531 */
rt_hw_spi_device_attach(const char * bus_name,const char * device_name,enum_GPIOx_t cs_gpiox,uint16_t cs_gpio_pin)532 rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, enum_GPIOx_t cs_gpiox, uint16_t cs_gpio_pin)
533 {
534 rt_uint32_t alternate;
535 RT_ASSERT(bus_name != RT_NULL);
536 RT_ASSERT(device_name != RT_NULL);
537
538 rt_err_t result;
539 struct rt_spi_device *spi_device;
540 struct acm32_hw_spi_cs *cs_pin;
541
542 alternate = get_gpio_alternate(cs_gpiox, cs_gpio_pin);
543 if (alternate == RT_UINT32_MAX)
544 {
545 return -RT_EINVAL;
546 }
547
548 /* initialize the cs pin && select the slave*/
549 GPIO_InitTypeDef GPIO_Initure;
550 GPIO_Initure.Pin = cs_gpio_pin;
551 GPIO_Initure.Mode = GPIO_MODE_OUTPUT_PP;
552 GPIO_Initure.Pull = GPIO_PULLUP;
553 GPIO_Initure.Alternate = alternate;
554 HAL_GPIO_Init(cs_gpiox, &GPIO_Initure);
555
556 /* attach the device to spi bus*/
557 spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
558 RT_ASSERT(spi_device != RT_NULL);
559 cs_pin = (struct acm32_hw_spi_cs *)rt_malloc(sizeof(struct acm32_hw_spi_cs));
560 RT_ASSERT(cs_pin != RT_NULL);
561 cs_pin->GPIOx = cs_gpiox;
562 cs_pin->GPIO_Pin = cs_gpio_pin;
563 result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
564
565 RT_ASSERT(result == RT_EOK);
566
567 return result;
568 }
569
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)570 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
571 {
572 GPIO_InitTypeDef GPIO_Handle;
573 struct acm32_spi *spi_drv;
574 struct acm32_spi_config *spi_config;
575
576 RT_ASSERT(hspi != RT_NULL);
577
578 spi_drv = rt_container_of(hspi, struct acm32_spi, handle);
579
580 RT_ASSERT(spi_drv->spi_bus.parent.user_data != RT_NULL);
581
582 spi_config = (struct acm32_spi_config *)spi_drv->spi_bus.parent.user_data;
583
584 /* Enable Clock */
585 System_Module_Enable(spi_config->enable_id);
586
587 /* SPI CS */
588 GPIO_Handle.Pin = spi_config->cs_pin;
589 GPIO_Handle.Mode = GPIO_MODE_AF_PP;
590 GPIO_Handle.Pull = GPIO_PULLUP;
591 GPIO_Handle.Alternate = spi_config->cs_alternate ;
592 HAL_GPIO_Init(spi_config->cs_port, &GPIO_Handle);
593
594 /* SPI SCK */
595 GPIO_Handle.Pin = spi_config->sck_pin;
596 GPIO_Handle.Mode = GPIO_MODE_AF_PP;
597 GPIO_Handle.Pull = GPIO_PULLUP;
598 GPIO_Handle.Alternate = spi_config->sck_alternate ;
599 HAL_GPIO_Init(spi_config->sck_port, &GPIO_Handle);
600
601 /* SPI MOSI */
602 GPIO_Handle.Pin = spi_config->mosi_pin;
603 GPIO_Handle.Mode = GPIO_MODE_AF_PP;
604 GPIO_Handle.Pull = GPIO_PULLUP;
605 GPIO_Handle.Alternate = spi_config->mosi_alternate ;
606 HAL_GPIO_Init(spi_config->mosi_port, &GPIO_Handle);
607
608 /* SPI MISO */
609 GPIO_Handle.Pin = spi_config->miso_pin;
610 GPIO_Handle.Mode = GPIO_MODE_AF_PP;
611 GPIO_Handle.Pull = GPIO_PULLUP;
612 GPIO_Handle.Alternate = spi_config->miso_alternate ;
613 HAL_GPIO_Init(spi_config->miso_port, &GPIO_Handle);
614
615 if (hspi->Init.X_Mode == SPI_4X_MODE)
616 {
617 /* SPI WP */
618 GPIO_Handle.Pin = spi_config->wp_pin;
619 GPIO_Handle.Mode = GPIO_MODE_AF_PP;
620 GPIO_Handle.Pull = GPIO_PULLUP;
621 GPIO_Handle.Alternate = spi_config->wp_alternate ;
622 HAL_GPIO_Init(spi_config->wp_port, &GPIO_Handle);
623
624 /* SPI HOLD */
625 GPIO_Handle.Pin = spi_config->hold_pin;
626 GPIO_Handle.Mode = GPIO_MODE_AF_PP;
627 GPIO_Handle.Pull = GPIO_PULLUP;
628 GPIO_Handle.Alternate = spi_config->hold_alternate ;
629 HAL_GPIO_Init(spi_config->hold_port, &GPIO_Handle);
630 }
631
632 /* Clear Pending Interrupt */
633 NVIC_ClearPendingIRQ(spi_config->irq_type);
634
635 /* Enable External Interrupt */
636 NVIC_EnableIRQ(spi_config->irq_type);
637 }
638 #endif /* BSP_USING_SPI1 || BSP_USING_SPI2 */
639 #endif /* RT_USING_SPI */
640
641