1;/*! 2; * @file startup_apm32f10x_hd.s 3; * 4; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd 5; * 6; * @version V1.0.3 7; * 8; * @date 2022-07-25 9; * 10; * @attention 11; * 12; * Copyright (C) 2020-2022 Geehy Semiconductor 13; * 14; * You may not use this file except in compliance with the 15; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16; * 17; * The program is only for reference, which is distributed in the hope 18; * that it will be useful and instructional for customers to develop 19; * their software. Unless required by applicable law or agreed to in 20; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23; * and limitations under the License. 24; */ 25 26; <h> Stack Configuration 27; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 28; </h> 29 30Stack_Size EQU 0x00000400 31 32 AREA STACK, NOINIT, READWRITE, ALIGN=3 33Stack_Mem SPACE Stack_Size 34__initial_sp 35 36 37; <h> Heap Configuration 38; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 39; </h> 40 41Heap_Size EQU 0x00000200 42 43 AREA HEAP, NOINIT, READWRITE, ALIGN=3 44__heap_base 45Heap_Mem SPACE Heap_Size 46__heap_limit 47 48 PRESERVE8 49 THUMB 50 51 52; Vector Table Mapped to Address 0 at Reset 53 AREA RESET, DATA, READONLY 54 EXPORT __Vectors 55 EXPORT __Vectors_End 56 EXPORT __Vectors_Size 57 58__Vectors DCD __initial_sp ; Top of Stack 59 DCD Reset_Handler ; Reset Handler 60 DCD NMI_Handler ; NMI Handler 61 DCD HardFault_Handler ; Hard Fault Handler 62 DCD MemManage_Handler ; MPU Fault Handler 63 DCD BusFault_Handler ; Bus Fault Handler 64 DCD UsageFault_Handler ; Usage Fault Handler 65 DCD 0 ; Reserved 66 DCD 0 ; Reserved 67 DCD 0 ; Reserved 68 DCD 0 ; Reserved 69 DCD SVC_Handler ; SVCall Handler 70 DCD DebugMon_Handler ; Debug Monitor Handler 71 DCD 0 ; Reserved 72 DCD PendSV_Handler ; PendSV Handler 73 DCD SysTick_Handler ; SysTick Handler 74 75 ; External Interrupts 76 DCD WWDT_IRQHandler ; Window Watchdog 77 DCD PVD_IRQHandler ; PVD through EINT Line detect 78 DCD TAMPER_IRQHandler ; Tamper 79 DCD RTC_IRQHandler ; RTC 80 DCD FLASH_IRQHandler ; Flash 81 DCD RCM_IRQHandler ; RCM 82 DCD EINT0_IRQHandler ; EINT Line 0 83 DCD EINT1_IRQHandler ; EINT Line 1 84 DCD EINT2_IRQHandler ; EINT Line 2 85 DCD EINT3_IRQHandler ; EINT Line 3 86 DCD EINT4_IRQHandler ; EINT Line 4 87 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 88 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 89 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 90 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 91 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 92 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 93 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 94 DCD ADC1_2_IRQHandler ; ADC1 & ADC2 95 DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX 96 DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0 97 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 98 DCD CAN1_SCE_IRQHandler ; CAN1 SCE 99 DCD EINT9_5_IRQHandler ; EINT Line 9..5 100 DCD TMR1_BRK_IRQHandler ; TMR1 Break 101 DCD TMR1_UP_IRQHandler ; TMR1 Update 102 DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation 103 DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare 104 DCD TMR2_IRQHandler ; TMR2 105 DCD TMR3_IRQHandler ; TMR3 106 DCD TMR4_IRQHandler ; TMR4 107 DCD I2C1_EV_IRQHandler ; I2C1 Event 108 DCD I2C1_ER_IRQHandler ; I2C1 Error 109 DCD I2C2_EV_IRQHandler ; I2C2 Event 110 DCD I2C2_ER_IRQHandler ; I2C2 Error 111 DCD SPI1_IRQHandler ; SPI1 112 DCD SPI2_IRQHandler ; SPI2 113 DCD USART1_IRQHandler ; USART1 114 DCD USART2_IRQHandler ; USART2 115 DCD USART3_IRQHandler ; USART3 116 DCD EINT15_10_IRQHandler ; EINT Line 15..10 117 DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line 118 DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend 119 DCD TMR8_BRK_IRQHandler ; TMR8 Break 120 DCD TMR8_UP_IRQHandler ; TMR8 Update 121 DCD TMR8_TRG_COM_IRQHandler ; TMR8 Trigger and Commutation 122 DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare 123 DCD ADC3_IRQHandler ; ADC3 124 DCD EMMC_IRQHandler ; EMMC 125 DCD SDIO_IRQHandler ; SDIO 126 DCD TMR5_IRQHandler ; TMR5 127 DCD SPI3_IRQHandler ; SPI3 128 DCD UART4_IRQHandler ; UART4 129 DCD UART5_IRQHandler ; UART5 130 DCD TMR6_IRQHandler ; TMR6 131 DCD TMR7_IRQHandler ; TMR7 132 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 133 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 134 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 135 DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 136 DCD 0 ; Reserved 137 DCD USBD2_HP_CAN2_TX_IRQHandler ; USBD2 High Priority or CAN2 TX 138 DCD USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low Priority or CAN2 RX0 139 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 140 DCD CAN2_SCE_IRQHandler ; CAN2 SCE 141__Vectors_End 142 143__Vectors_Size EQU __Vectors_End - __Vectors 144 145 AREA |.text|, CODE, READONLY 146 147; Reset handler 148Reset_Handler PROC 149 EXPORT Reset_Handler [WEAK] 150 IMPORT __main 151 IMPORT SystemInit 152 LDR R0, =SystemInit 153 BLX R0 154 LDR R0, =__main 155 BX R0 156 ENDP 157 158; Dummy Exception Handlers (infinite loops which can be modified) 159 160NMI_Handler PROC 161 EXPORT NMI_Handler [WEAK] 162 B . 163 ENDP 164HardFault_Handler\ 165 PROC 166 EXPORT HardFault_Handler [WEAK] 167 B . 168 ENDP 169MemManage_Handler\ 170 PROC 171 EXPORT MemManage_Handler [WEAK] 172 B . 173 ENDP 174BusFault_Handler\ 175 PROC 176 EXPORT BusFault_Handler [WEAK] 177 B . 178 ENDP 179UsageFault_Handler\ 180 PROC 181 EXPORT UsageFault_Handler [WEAK] 182 B . 183 ENDP 184SVC_Handler PROC 185 EXPORT SVC_Handler [WEAK] 186 B . 187 ENDP 188DebugMon_Handler\ 189 PROC 190 EXPORT DebugMon_Handler [WEAK] 191 B . 192 ENDP 193PendSV_Handler PROC 194 EXPORT PendSV_Handler [WEAK] 195 B . 196 ENDP 197SysTick_Handler PROC 198 EXPORT SysTick_Handler [WEAK] 199 B . 200 ENDP 201 202Default_Handler PROC 203 204 EXPORT WWDT_IRQHandler [WEAK] 205 EXPORT PVD_IRQHandler [WEAK] 206 EXPORT TAMPER_IRQHandler [WEAK] 207 EXPORT RTC_IRQHandler [WEAK] 208 EXPORT FLASH_IRQHandler [WEAK] 209 EXPORT RCM_IRQHandler [WEAK] 210 EXPORT EINT0_IRQHandler [WEAK] 211 EXPORT EINT1_IRQHandler [WEAK] 212 EXPORT EINT2_IRQHandler [WEAK] 213 EXPORT EINT3_IRQHandler [WEAK] 214 EXPORT EINT4_IRQHandler [WEAK] 215 EXPORT DMA1_Channel1_IRQHandler [WEAK] 216 EXPORT DMA1_Channel2_IRQHandler [WEAK] 217 EXPORT DMA1_Channel3_IRQHandler [WEAK] 218 EXPORT DMA1_Channel4_IRQHandler [WEAK] 219 EXPORT DMA1_Channel5_IRQHandler [WEAK] 220 EXPORT DMA1_Channel6_IRQHandler [WEAK] 221 EXPORT DMA1_Channel7_IRQHandler [WEAK] 222 EXPORT ADC1_2_IRQHandler [WEAK] 223 EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] 224 EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] 225 EXPORT CAN1_RX1_IRQHandler [WEAK] 226 EXPORT CAN1_SCE_IRQHandler [WEAK] 227 EXPORT EINT9_5_IRQHandler [WEAK] 228 EXPORT TMR1_BRK_IRQHandler [WEAK] 229 EXPORT TMR1_UP_IRQHandler [WEAK] 230 EXPORT TMR1_TRG_COM_IRQHandler [WEAK] 231 EXPORT TMR1_CC_IRQHandler [WEAK] 232 EXPORT TMR2_IRQHandler [WEAK] 233 EXPORT TMR3_IRQHandler [WEAK] 234 EXPORT TMR4_IRQHandler [WEAK] 235 EXPORT I2C1_EV_IRQHandler [WEAK] 236 EXPORT I2C1_ER_IRQHandler [WEAK] 237 EXPORT I2C2_EV_IRQHandler [WEAK] 238 EXPORT I2C2_ER_IRQHandler [WEAK] 239 EXPORT SPI1_IRQHandler [WEAK] 240 EXPORT SPI2_IRQHandler [WEAK] 241 EXPORT USART1_IRQHandler [WEAK] 242 EXPORT USART2_IRQHandler [WEAK] 243 EXPORT USART3_IRQHandler [WEAK] 244 EXPORT EINT15_10_IRQHandler [WEAK] 245 EXPORT RTCAlarm_IRQHandler [WEAK] 246 EXPORT USBDWakeUp_IRQHandler [WEAK] 247 EXPORT TMR8_BRK_IRQHandler [WEAK] 248 EXPORT TMR8_UP_IRQHandler [WEAK] 249 EXPORT TMR8_TRG_COM_IRQHandler [WEAK] 250 EXPORT TMR8_CC_IRQHandler [WEAK] 251 EXPORT ADC3_IRQHandler [WEAK] 252 EXPORT EMMC_IRQHandler [WEAK] 253 EXPORT SDIO_IRQHandler [WEAK] 254 EXPORT TMR5_IRQHandler [WEAK] 255 EXPORT SPI3_IRQHandler [WEAK] 256 EXPORT UART4_IRQHandler [WEAK] 257 EXPORT UART5_IRQHandler [WEAK] 258 EXPORT TMR6_IRQHandler [WEAK] 259 EXPORT TMR7_IRQHandler [WEAK] 260 EXPORT DMA2_Channel1_IRQHandler [WEAK] 261 EXPORT DMA2_Channel2_IRQHandler [WEAK] 262 EXPORT DMA2_Channel3_IRQHandler [WEAK] 263 EXPORT DMA2_Channel4_5_IRQHandler [WEAK] 264 EXPORT USBD2_HP_CAN2_TX_IRQHandler [WEAK] 265 EXPORT USBD2_LP_CAN2_RX0_IRQHandler [WEAK] 266 EXPORT CAN2_RX1_IRQHandler [WEAK] 267 EXPORT CAN2_SCE_IRQHandler [WEAK] 268 269WWDT_IRQHandler 270PVD_IRQHandler 271TAMPER_IRQHandler 272RTC_IRQHandler 273FLASH_IRQHandler 274RCM_IRQHandler 275EINT0_IRQHandler 276EINT1_IRQHandler 277EINT2_IRQHandler 278EINT3_IRQHandler 279EINT4_IRQHandler 280DMA1_Channel1_IRQHandler 281DMA1_Channel2_IRQHandler 282DMA1_Channel3_IRQHandler 283DMA1_Channel4_IRQHandler 284DMA1_Channel5_IRQHandler 285DMA1_Channel6_IRQHandler 286DMA1_Channel7_IRQHandler 287ADC1_2_IRQHandler 288USBD1_HP_CAN1_TX_IRQHandler 289USBD1_LP_CAN1_RX0_IRQHandler 290CAN1_RX1_IRQHandler 291CAN1_SCE_IRQHandler 292EINT9_5_IRQHandler 293TMR1_BRK_IRQHandler 294TMR1_UP_IRQHandler 295TMR1_TRG_COM_IRQHandler 296TMR1_CC_IRQHandler 297TMR2_IRQHandler 298TMR3_IRQHandler 299TMR4_IRQHandler 300I2C1_EV_IRQHandler 301I2C1_ER_IRQHandler 302I2C2_EV_IRQHandler 303I2C2_ER_IRQHandler 304SPI1_IRQHandler 305SPI2_IRQHandler 306USART1_IRQHandler 307USART2_IRQHandler 308USART3_IRQHandler 309EINT15_10_IRQHandler 310RTCAlarm_IRQHandler 311USBDWakeUp_IRQHandler 312TMR8_BRK_IRQHandler 313TMR8_UP_IRQHandler 314TMR8_TRG_COM_IRQHandler 315TMR8_CC_IRQHandler 316ADC3_IRQHandler 317EMMC_IRQHandler 318SDIO_IRQHandler 319TMR5_IRQHandler 320SPI3_IRQHandler 321UART4_IRQHandler 322UART5_IRQHandler 323TMR6_IRQHandler 324TMR7_IRQHandler 325DMA2_Channel1_IRQHandler 326DMA2_Channel2_IRQHandler 327DMA2_Channel3_IRQHandler 328DMA2_Channel4_5_IRQHandler 329USBD2_HP_CAN2_TX_IRQHandler 330USBD2_LP_CAN2_RX0_IRQHandler 331CAN2_RX1_IRQHandler 332CAN2_SCE_IRQHandler 333 B . 334 335 ENDP 336 337 ALIGN 338 339;******************************************************************************* 340; User Stack and Heap initialization 341;******************************************************************************* 342 IF :DEF:__MICROLIB 343 344 EXPORT __initial_sp 345 EXPORT __heap_base 346 EXPORT __heap_limit 347 348 ELSE 349 350 IMPORT __use_two_region_memory 351 EXPORT __user_initial_stackheap 352 353__user_initial_stackheap 354 355 LDR R0, = Heap_Mem 356 LDR R1, = (Stack_Mem + Stack_Size) 357 LDR R2, = (Heap_Mem + Heap_Size) 358 LDR R3, = Stack_Mem 359 BX LR 360 361 ALIGN 362 363 ENDIF 364 365 END 366 367;*******************************END OF FILE************************************ 368 369