1/*! 2 * @file startup_apm32f103_hd.S 3 * 4 * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f103_hd 5 * 6 * @version V1.0.1 7 * 8 * @date 2022-12-01 9 * 10 * @attention 11 * 12 * Copyright (C) 2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 .syntax unified 27 .cpu cortex-m3 28 .fpu softvfp 29 .thumb 30 31.global g_apm32_Vectors 32.global Default_Handler 33 34.word _start_address_init_data 35.word _start_address_data 36.word _end_address_data 37.word _start_address_bss 38.word _end_address_bss 39 40 .section .text.Reset_Handler 41 .weak Reset_Handler 42 .type Reset_Handler, %function 43// Reset handler routine 44Reset_Handler: 45 46 ldr r0, =_start_address_data 47 ldr r1, =_end_address_data 48 ldr r2, =_start_address_init_data 49 movs r3, #0 50 b L_loop0_0 51 52L_loop0: 53 ldr r4, [r2, r3] 54 str r4, [r0, r3] 55 adds r3, r3, #4 56 57L_loop0_0: 58 adds r4, r0, r3 59 cmp r4, r1 60 bcc L_loop0 61 62 ldr r2, =_start_address_bss 63 ldr r4, =_end_address_bss 64 movs r3, #0 65 b L_loop1 66 67L_loop2: 68 str r3, [r2] 69 adds r2, r2, #4 70 71L_loop1: 72 cmp r2, r4 73 bcc L_loop2 74 75 bl SystemInit 76 bl __libc_init_array 77 bl entry 78 bx lr 79.size Reset_Handler, .-Reset_Handler 80 81// This is the code that gets called when the processor receives an unexpected interrupt. 82 .section .text.Default_Handler,"ax",%progbits 83Default_Handler: 84L_Loop_infinite: 85 b L_Loop_infinite 86 .size Default_Handler, .-Default_Handler 87 88// The minimal vector table for a Cortex M3. 89 .section .isr_vector,"a",%progbits 90 .type g_apm32_Vectors, %object 91 .size g_apm32_Vectors, .-g_apm32_Vectors 92 93// Vector Table Mapped to Address 0 at Reset 94g_apm32_Vectors: 95 96 .word _end_stack // Top of Stack 97 .word Reset_Handler // Reset Handler 98 .word NMI_Handler // NMI Handler 99 .word HardFault_Handler // Hard Fault Handler 100 .word MemManage_Handler // MPU Fault Handler 101 .word BusFault_Handler // Bus Fault Handler 102 .word UsageFault_Handler // Usage Fault Handler 103 .word 0 // Reserved 104 .word 0 // Reserved 105 .word 0 // Reserved 106 .word 0 // Reserved 107 .word SVC_Handler // SVCall Handler 108 .word DebugMon_Handler // Debug Monitor Handler 109 .word 0 // Reserved 110 .word PendSV_Handler // PendSV Handler 111 .word SysTick_Handler // SysTick Handler 112 .word WWDT_IRQHandler // Window Watchdog 113 .word PVD_IRQHandler // PVD through EINT Line detect 114 .word TAMPER_IRQHandler // Tamper 115 .word RTC_IRQHandler // RTC 116 .word FLASH_IRQHandler // Flash 117 .word RCM_IRQHandler // RCM 118 .word EINT0_IRQHandler // EINT Line 0 119 .word EINT1_IRQHandler // EINT Line 1 120 .word EINT2_IRQHandler // EINT Line 2 121 .word EINT3_IRQHandler // EINT Line 3 122 .word EINT4_IRQHandler // EINT Line 4 123 .word DMA1_Channel1_IRQHandler // DMA1 Channel 1 124 .word DMA1_Channel2_IRQHandler // DMA1 Channel 2 125 .word DMA1_Channel3_IRQHandler // DMA1 Channel 3 126 .word DMA1_Channel4_IRQHandler // DMA1 Channel 4 127 .word DMA1_Channel5_IRQHandler // DMA1 Channel 5 128 .word DMA1_Channel6_IRQHandler // DMA1 Channel 6 129 .word DMA1_Channel7_IRQHandler // DMA1 Channel 7 130 .word ADC1_2_IRQHandler // ADC1 & ADC2 131 .word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX 132 .word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0 133 .word CAN1_RX1_IRQHandler // CAN1 RX1 134 .word CAN1_SCE_IRQHandler // CAN1 SCE 135 .word EINT9_5_IRQHandler // EINT Line 9..5 136 .word TMR1_BRK_IRQHandler // TMR1 Break 137 .word TMR1_UP_IRQHandler // TMR1 Update 138 .word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation 139 .word TMR1_CC_IRQHandler // TMR1 Capture Compare 140 .word TMR2_IRQHandler // TMR2 141 .word TMR3_IRQHandler // TMR3 142 .word TMR4_IRQHandler // TMR4 143 .word I2C1_EV_IRQHandler // I2C1 Event 144 .word I2C1_ER_IRQHandler // I2C1 Error 145 .word I2C2_EV_IRQHandler // I2C2 Event 146 .word I2C2_ER_IRQHandler // I2C2 Error 147 .word SPI1_IRQHandler // SPI1 148 .word SPI2_IRQHandler // SPI2 149 .word USART1_IRQHandler // USART1 150 .word USART2_IRQHandler // USART2 151 .word USART3_IRQHandler // USART3 152 .word EINT15_10_IRQHandler // EINT Line 15..10 153 .word RTCAlarm_IRQHandler // RTC Alarm through EINT Line 154 .word USBDWakeUp_IRQHandler // USBD Wakeup from suspend 155 .word TMR8_BRK_IRQHandler // TMR8 Break 156 .word TMR8_UP_IRQHandler // TMR8 Update 157 .word TMR8_TRG_COM_IRQHandler // TMR8 Trigger and Commutation 158 .word TMR8_CC_IRQHandler // TMR8 Capture Compare 159 .word ADC3_IRQHandler // ADC3 160 .word FSMC_IRQHandler // EMMC 161 .word SDIO_IRQHandler // SDIO 162 .word TMR5_IRQHandler // TMR5 163 .word SPI3_IRQHandler // SPI3 164 .word UART4_IRQHandler // UART4 165 .word UART5_IRQHandler // UART5 166 .word TMR6_IRQHandler // TMR6 167 .word TMR7_IRQHandler // TMR7 168 .word DMA2_Channel1_IRQHandler // DMA2 Channel1 169 .word DMA2_Channel2_IRQHandler // DMA2 Channel2 170 .word DMA2_Channel3_IRQHandler // DMA2 Channel3 171 .word DMA2_Channel4_5_IRQHandler // DMA2 Channel4 & Channel5 172 .word 0 // Reserved 173 .word USBD2_HP_CAN2_TX_IRQHandler // USBD2 High Priority or CAN2 TX 174 .word USBD2_LP_CAN2_RX0_IRQHandler // USBD2 Low Priority or CAN2 RX0 175 .word CAN2_RX1_IRQHandler // CAN2 RX1 176 .word CAN2_SCE_IRQHandler // CAN2 SCE 177 178// Default exception/interrupt handler 179 180 .weak NMI_Handler 181 .thumb_set NMI_Handler,Default_Handler 182 183 .weak HardFault_Handler 184 .thumb_set HardFault_Handler,Default_Handler 185 186 .weak MemManage_Handler 187 .thumb_set MemManage_Handler,Default_Handler 188 189 .weak BusFault_Handler 190 .thumb_set BusFault_Handler,Default_Handler 191 192 .weak UsageFault_Handler 193 .thumb_set UsageFault_Handler,Default_Handler 194 195 .weak SVC_Handler 196 .thumb_set SVC_Handler,Default_Handler 197 198 .weak DebugMon_Handler 199 .thumb_set DebugMon_Handler,Default_Handler 200 201 .weak PendSV_Handler 202 .thumb_set PendSV_Handler,Default_Handler 203 204 .weak SysTick_Handler 205 .thumb_set SysTick_Handler,Default_Handler 206 207 .weak WWDT_IRQHandler 208 .thumb_set WWDT_IRQHandler,Default_Handler 209 210 .weak PVD_IRQHandler 211 .thumb_set PVD_IRQHandler,Default_Handler 212 213 .weak TAMPER_IRQHandler 214 .thumb_set TAMPER_IRQHandler,Default_Handler 215 216 .weak RTC_IRQHandler 217 .thumb_set RTC_IRQHandler,Default_Handler 218 219 .weak FLASH_IRQHandler 220 .thumb_set FLASH_IRQHandler,Default_Handler 221 222 .weak RCM_IRQHandler 223 .thumb_set RCM_IRQHandler,Default_Handler 224 225 .weak EINT0_IRQHandler 226 .thumb_set EINT0_IRQHandler,Default_Handler 227 228 .weak EINT1_IRQHandler 229 .thumb_set EINT1_IRQHandler,Default_Handler 230 231 .weak EINT2_IRQHandler 232 .thumb_set EINT2_IRQHandler,Default_Handler 233 234 .weak EINT3_IRQHandler 235 .thumb_set EINT3_IRQHandler,Default_Handler 236 237 .weak EINT4_IRQHandler 238 .thumb_set EINT4_IRQHandler,Default_Handler 239 240 .weak DMA1_Channel1_IRQHandler 241 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 242 243 .weak DMA1_Channel2_IRQHandler 244 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 245 246 .weak DMA1_Channel3_IRQHandler 247 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 248 249 .weak DMA1_Channel4_IRQHandler 250 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 251 252 .weak DMA1_Channel5_IRQHandler 253 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 254 255 .weak DMA1_Channel6_IRQHandler 256 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 257 258 .weak DMA1_Channel7_IRQHandler 259 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 260 261 .weak ADC1_2_IRQHandler 262 .thumb_set ADC1_2_IRQHandler,Default_Handler 263 264 .weak USBD1_HP_CAN1_TX_IRQHandler 265 .thumb_set USBD1_HP_CAN1_TX_IRQHandler,Default_Handler 266 267 .weak USBD1_LP_CAN1_RX0_IRQHandler 268 .thumb_set USBD1_LP_CAN1_RX0_IRQHandler,Default_Handler 269 270 .weak CAN1_RX1_IRQHandler 271 .thumb_set CAN1_RX1_IRQHandler,Default_Handler 272 273 .weak CAN1_SCE_IRQHandler 274 .thumb_set CAN1_SCE_IRQHandler,Default_Handler 275 276 .weak EINT9_5_IRQHandler 277 .thumb_set EINT9_5_IRQHandler,Default_Handler 278 279 .weak TMR1_BRK_IRQHandler 280 .thumb_set TMR1_BRK_IRQHandler,Default_Handler 281 282 .weak TMR1_UP_IRQHandler 283 .thumb_set TMR1_UP_IRQHandler,Default_Handler 284 285 .weak TMR1_TRG_COM_IRQHandler 286 .thumb_set TMR1_TRG_COM_IRQHandler,Default_Handler 287 288 .weak TMR1_CC_IRQHandler 289 .thumb_set TMR1_CC_IRQHandler,Default_Handler 290 291 .weak TMR2_IRQHandler 292 .thumb_set TMR2_IRQHandler,Default_Handler 293 294 .weak TMR3_IRQHandler 295 .thumb_set TMR3_IRQHandler,Default_Handler 296 297 .weak TMR4_IRQHandler 298 .thumb_set TMR4_IRQHandler,Default_Handler 299 300 .weak I2C1_EV_IRQHandler 301 .thumb_set I2C1_EV_IRQHandler,Default_Handler 302 303 .weak I2C1_ER_IRQHandler 304 .thumb_set I2C1_ER_IRQHandler,Default_Handler 305 306 .weak I2C2_EV_IRQHandler 307 .thumb_set I2C2_EV_IRQHandler,Default_Handler 308 309 .weak I2C2_ER_IRQHandler 310 .thumb_set I2C2_ER_IRQHandler,Default_Handler 311 312 .weak SPI1_IRQHandler 313 .thumb_set SPI1_IRQHandler,Default_Handler 314 315 .weak SPI2_IRQHandler 316 .thumb_set SPI2_IRQHandler,Default_Handler 317 318 .weak USART1_IRQHandler 319 .thumb_set USART1_IRQHandler,Default_Handler 320 321 .weak USART2_IRQHandler 322 .thumb_set USART2_IRQHandler,Default_Handler 323 324 .weak USART3_IRQHandler 325 .thumb_set USART3_IRQHandler,Default_Handler 326 327 .weak EINT15_10_IRQHandler 328 .thumb_set EINT15_10_IRQHandler,Default_Handler 329 330 .weak RTCAlarm_IRQHandler 331 .thumb_set RTCAlarm_IRQHandler,Default_Handler 332 333 .weak USBDWakeUp_IRQHandler 334 .thumb_set USBDWakeUp_IRQHandler,Default_Handler 335 336 .weak TMR8_BRK_IRQHandler 337 .thumb_set TMR8_BRK_IRQHandler,Default_Handler 338 339 .weak TMR8_UP_IRQHandler 340 .thumb_set TMR8_UP_IRQHandler,Default_Handler 341 342 .weak TMR8_TRG_COM_IRQHandler 343 .thumb_set TMR8_TRG_COM_IRQHandler,Default_Handler 344 345 .weak TMR8_CC_IRQHandler 346 .thumb_set TMR8_CC_IRQHandler,Default_Handler 347 348 .weak ADC3_IRQHandler 349 .thumb_set ADC3_IRQHandler,Default_Handler 350 351 .weak FSMC_IRQHandler 352 .thumb_set FSMC_IRQHandler,Default_Handler 353 354 .weak SDIO_IRQHandler 355 .thumb_set SDIO_IRQHandler,Default_Handler 356 357 .weak TMR5_IRQHandler 358 .thumb_set TMR5_IRQHandler,Default_Handler 359 360 .weak SPI3_IRQHandler 361 .thumb_set SPI3_IRQHandler,Default_Handler 362 363 .weak UART4_IRQHandler 364 .thumb_set UART4_IRQHandler,Default_Handler 365 366 .weak UART5_IRQHandler 367 .thumb_set UART5_IRQHandler,Default_Handler 368 369 .weak TMR6_IRQHandler 370 .thumb_set TMR6_IRQHandler,Default_Handler 371 372 .weak TMR7_IRQHandler 373 .thumb_set TMR7_IRQHandler,Default_Handler 374 375 .weak DMA2_Channel1_IRQHandler 376 .thumb_set DMA2_Channel1_IRQHandler,Default_Handler 377 378 .weak DMA2_Channel2_IRQHandler 379 .thumb_set DMA2_Channel2_IRQHandler,Default_Handler 380 381 .weak DMA2_Channel3_IRQHandler 382 .thumb_set DMA2_Channel3_IRQHandler,Default_Handler 383 384 .weak DMA2_Channel4_5_IRQHandler 385 .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler 386 387 .weak USBD2_HP_CAN2_TX_IRQHandler 388 .thumb_set USBD2_HP_CAN2_TX_IRQHandler,Default_Handler 389 390 .weak USBD2_LP_CAN2_RX0_IRQHandler 391 .thumb_set USBD2_LP_CAN2_RX0_IRQHandler,Default_Handler 392 393 .weak CAN2_RX1_IRQHandler 394 .thumb_set CAN2_RX1_IRQHandler,Default_Handler 395 396 .weak CAN2_SCE_IRQHandler 397 .thumb_set CAN2_SCE_IRQHandler,Default_Handler 398 399