1/*! 2 * @file startup_apm32s10x_md.S 3 * 4 * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32s10x_md 5 * 6 * @version V1.0.0 7 * 8 * @date 2022-12-31 9 * 10 * @attention 11 * 12 * Copyright (C) 2022-2023 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 .syntax unified 27 .cpu cortex-m3 28 .fpu softvfp 29 .thumb 30 31.global g_apm32_Vectors 32.global Default_Handler 33 34.word _start_address_init_data 35.word _start_address_data 36.word _end_address_data 37.word _start_address_bss 38.word _end_address_bss 39 40 .section .text.Reset_Handler 41 .weak Reset_Handler 42 .type Reset_Handler, %function 43// Reset handler routine 44Reset_Handler: 45 46 ldr r0, =_start_address_data 47 ldr r1, =_end_address_data 48 ldr r2, =_start_address_init_data 49 movs r3, #0 50 b L_loop0_0 51 52L_loop0: 53 ldr r4, [r2, r3] 54 str r4, [r0, r3] 55 adds r3, r3, #4 56 57L_loop0_0: 58 adds r4, r0, r3 59 cmp r4, r1 60 bcc L_loop0 61 62 ldr r2, =_start_address_bss 63 ldr r4, =_end_address_bss 64 movs r3, #0 65 b L_loop1 66 67L_loop2: 68 str r3, [r2] 69 adds r2, r2, #4 70 71L_loop1: 72 cmp r2, r4 73 bcc L_loop2 74 75 bl SystemInit 76 bl __libc_init_array 77 bl entry 78 bx lr 79.size Reset_Handler, .-Reset_Handler 80 81// This is the code that gets called when the processor receives an unexpected interrupt. 82 .section .text.Default_Handler,"ax",%progbits 83Default_Handler: 84L_Loop_infinite: 85 b L_Loop_infinite 86 .size Default_Handler, .-Default_Handler 87 88// The minimal vector table for a Cortex M3. 89 .section .isr_vector,"a",%progbits 90 .type g_apm32_Vectors, %object 91 .size g_apm32_Vectors, .-g_apm32_Vectors 92 93// Vector Table Mapped to Address 0 at Reset 94g_apm32_Vectors: 95 96 .word _end_stack // Top of Stack 97 .word Reset_Handler // Reset Handler 98 .word NMI_Handler // NMI Handler 99 .word HardFault_Handler // Hard Fault Handler 100 .word MemManage_Handler // MPU Fault Handler 101 .word BusFault_Handler // Bus Fault Handler 102 .word UsageFault_Handler // Usage Fault Handler 103 .word 0 // Reserved 104 .word 0 // Reserved 105 .word 0 // Reserved 106 .word 0 // Reserved 107 .word SVC_Handler // SVCall Handler 108 .word DebugMon_Handler // Debug Monitor Handler 109 .word 0 // Reserved 110 .word PendSV_Handler // PendSV Handler 111 .word SysTick_Handler // SysTick Handler 112 .word WWDT_IRQHandler // Window Watchdog 113 .word PVD_IRQHandler // PVD through EINT Line detect 114 .word TAMPER_IRQHandler // Tamper 115 .word RTC_IRQHandler // RTC 116 .word FLASH_IRQHandler // Flash 117 .word RCM_IRQHandler // RCM 118 .word EINT0_IRQHandler // EINT Line 0 119 .word EINT1_IRQHandler // EINT Line 1 120 .word EINT2_IRQHandler // EINT Line 2 121 .word EINT3_IRQHandler // EINT Line 3 122 .word EINT4_IRQHandler // EINT Line 4 123 .word DMA1_Channel1_IRQHandler // DMA1 Channel 1 124 .word DMA1_Channel2_IRQHandler // DMA1 Channel 2 125 .word DMA1_Channel3_IRQHandler // DMA1 Channel 3 126 .word DMA1_Channel4_IRQHandler // DMA1 Channel 4 127 .word DMA1_Channel5_IRQHandler // DMA1 Channel 5 128 .word DMA1_Channel6_IRQHandler // DMA1 Channel 6 129 .word DMA1_Channel7_IRQHandler // DMA1 Channel 7 130 .word ADC1_2_IRQHandler // ADC1 & ADC2 131 .word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX 132 .word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0 133 .word CAN1_RX1_IRQHandler // CAN1 RX1 134 .word CAN1_SCE_IRQHandler // CAN1 SCE 135 .word EINT9_5_IRQHandler // EINT Line 9..5 136 .word TMR1_BRK_IRQHandler // TMR1 Break 137 .word TMR1_UP_IRQHandler // TMR1 Update 138 .word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation 139 .word TMR1_CC_IRQHandler // TMR1 Capture Compare 140 .word TMR2_IRQHandler // TMR2 141 .word TMR3_IRQHandler // TMR3 142 .word TMR4_IRQHandler // TMR4 143 .word I2C1_EV_IRQHandler // I2C1 Event 144 .word I2C1_ER_IRQHandler // I2C1 Error 145 .word I2C2_EV_IRQHandler // I2C2 Event 146 .word I2C2_ER_IRQHandler // I2C2 Error 147 .word SPI1_IRQHandler // SPI1 148 .word SPI2_IRQHandler // SPI2 149 .word USART1_IRQHandler // USART1 150 .word USART2_IRQHandler // USART2 151 .word USART3_IRQHandler // USART3 152 .word EINT15_10_IRQHandler // EINT Line 15..10 153 .word RTCAlarm_IRQHandler // RTC Alarm through EINT Line 154 .word USBDWakeUp_IRQHandler // USBD Wakeup from suspend 155 .word FPU_IRQHandler // FPU 156 .word QSPI_IRQHandler // QSPI 157 .word USBD2_HP_CAN2_TX_IRQHandler // USBD2 High Priority or CAN2 TX 158 .word USBD2_LP_CAN2_RX0_IRQHandler // USBD2 Low Priority or CAN2 RX0 159 .word CAN2_RX1_IRQHandler // CAN2 RX1 160 .word CAN2_SCE_IRQHandler // CAN2 SCE 161 162// Default exception/interrupt handler 163 164 .weak NMI_Handler 165 .thumb_set NMI_Handler,Default_Handler 166 167 .weak HardFault_Handler 168 .thumb_set HardFault_Handler,Default_Handler 169 170 .weak MemManage_Handler 171 .thumb_set MemManage_Handler,Default_Handler 172 173 .weak BusFault_Handler 174 .thumb_set BusFault_Handler,Default_Handler 175 176 .weak UsageFault_Handler 177 .thumb_set UsageFault_Handler,Default_Handler 178 179 .weak SVC_Handler 180 .thumb_set SVC_Handler,Default_Handler 181 182 .weak DebugMon_Handler 183 .thumb_set DebugMon_Handler,Default_Handler 184 185 .weak PendSV_Handler 186 .thumb_set PendSV_Handler,Default_Handler 187 188 .weak SysTick_Handler 189 .thumb_set SysTick_Handler,Default_Handler 190 191 .weak WWDT_IRQHandler 192 .thumb_set WWDT_IRQHandler,Default_Handler 193 194 .weak PVD_IRQHandler 195 .thumb_set PVD_IRQHandler,Default_Handler 196 197 .weak TAMPER_IRQHandler 198 .thumb_set TAMPER_IRQHandler,Default_Handler 199 200 .weak RTC_IRQHandler 201 .thumb_set RTC_IRQHandler,Default_Handler 202 203 .weak FLASH_IRQHandler 204 .thumb_set FLASH_IRQHandler,Default_Handler 205 206 .weak RCM_IRQHandler 207 .thumb_set RCM_IRQHandler,Default_Handler 208 209 .weak EINT0_IRQHandler 210 .thumb_set EINT0_IRQHandler,Default_Handler 211 212 .weak EINT1_IRQHandler 213 .thumb_set EINT1_IRQHandler,Default_Handler 214 215 .weak EINT2_IRQHandler 216 .thumb_set EINT2_IRQHandler,Default_Handler 217 218 .weak EINT3_IRQHandler 219 .thumb_set EINT3_IRQHandler,Default_Handler 220 221 .weak EINT4_IRQHandler 222 .thumb_set EINT4_IRQHandler,Default_Handler 223 224 .weak DMA1_Channel1_IRQHandler 225 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 226 227 .weak DMA1_Channel2_IRQHandler 228 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 229 230 .weak DMA1_Channel3_IRQHandler 231 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 232 233 .weak DMA1_Channel4_IRQHandler 234 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 235 236 .weak DMA1_Channel5_IRQHandler 237 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 238 239 .weak DMA1_Channel6_IRQHandler 240 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 241 242 .weak DMA1_Channel7_IRQHandler 243 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 244 245 .weak ADC1_2_IRQHandler 246 .thumb_set ADC1_2_IRQHandler,Default_Handler 247 248 .weak USBD1_HP_CAN1_TX_IRQHandler 249 .thumb_set USBD1_HP_CAN1_TX_IRQHandler,Default_Handler 250 251 .weak USBD1_LP_CAN1_RX0_IRQHandler 252 .thumb_set USBD1_LP_CAN1_RX0_IRQHandler,Default_Handler 253 254 .weak CAN1_RX1_IRQHandler 255 .thumb_set CAN1_RX1_IRQHandler,Default_Handler 256 257 .weak CAN1_SCE_IRQHandler 258 .thumb_set CAN1_SCE_IRQHandler,Default_Handler 259 260 .weak EINT9_5_IRQHandler 261 .thumb_set EINT9_5_IRQHandler,Default_Handler 262 263 .weak TMR1_BRK_IRQHandler 264 .thumb_set TMR1_BRK_IRQHandler,Default_Handler 265 266 .weak TMR1_UP_IRQHandler 267 .thumb_set TMR1_UP_IRQHandler,Default_Handler 268 269 .weak TMR1_TRG_COM_IRQHandler 270 .thumb_set TMR1_TRG_COM_IRQHandler,Default_Handler 271 272 .weak TMR1_CC_IRQHandler 273 .thumb_set TMR1_CC_IRQHandler,Default_Handler 274 275 .weak TMR2_IRQHandler 276 .thumb_set TMR2_IRQHandler,Default_Handler 277 278 .weak TMR3_IRQHandler 279 .thumb_set TMR3_IRQHandler,Default_Handler 280 281 .weak TMR4_IRQHandler 282 .thumb_set TMR4_IRQHandler,Default_Handler 283 284 .weak I2C1_EV_IRQHandler 285 .thumb_set I2C1_EV_IRQHandler,Default_Handler 286 287 .weak I2C1_ER_IRQHandler 288 .thumb_set I2C1_ER_IRQHandler,Default_Handler 289 290 .weak I2C2_EV_IRQHandler 291 .thumb_set I2C2_EV_IRQHandler,Default_Handler 292 293 .weak I2C2_ER_IRQHandler 294 .thumb_set I2C2_ER_IRQHandler,Default_Handler 295 296 .weak SPI1_IRQHandler 297 .thumb_set SPI1_IRQHandler,Default_Handler 298 299 .weak SPI2_IRQHandler 300 .thumb_set SPI2_IRQHandler,Default_Handler 301 302 .weak USART1_IRQHandler 303 .thumb_set USART1_IRQHandler,Default_Handler 304 305 .weak USART2_IRQHandler 306 .thumb_set USART2_IRQHandler,Default_Handler 307 308 .weak USART3_IRQHandler 309 .thumb_set USART3_IRQHandler,Default_Handler 310 311 .weak EINT15_10_IRQHandler 312 .thumb_set EINT15_10_IRQHandler,Default_Handler 313 314 .weak RTCAlarm_IRQHandler 315 .thumb_set RTCAlarm_IRQHandler,Default_Handler 316 317 .weak USBDWakeUp_IRQHandler 318 .thumb_set USBDWakeUp_IRQHandler,Default_Handler 319 320 .weak FPU_IRQHandler 321 .thumb_set FPU_IRQHandler,Default_Handler 322 323 .weak QSPI_IRQHandler 324 .thumb_set QSPI_IRQHandler,Default_Handler 325 326 .weak USBD2_HP_CAN2_TX_IRQHandler 327 .thumb_set USBD2_HP_CAN2_TX_IRQHandler,Default_Handler 328 329 .weak USBD2_LP_CAN2_RX0_IRQHandler 330 .thumb_set USBD2_LP_CAN2_RX0_IRQHandler,Default_Handler 331 332 .weak CAN2_RX1_IRQHandler 333 .thumb_set CAN2_RX1_IRQHandler,Default_Handler 334 335 .weak CAN2_SCE_IRQHandler 336 .thumb_set CAN2_SCE_IRQHandler,Default_Handler 337