1;/**
2;* @file    startup_target.s
3;* @author  Application Team
4;* @version V1.1.0
5;* @date    2019-10-28
6;* @brief   Target Devices vector table.
7;******************************************************************************/
8
9  .syntax unified
10  .cpu cortex-m0
11  .fpu softvfp
12  .thumb
13
14.equ __CHIPINITIAL, 1
15
16.global g_pfnVectors
17.global Default_Handler
18
19/* start address for the initialization values of the .data section.
20defined in linker script */
21.word _sidata
22/* start address for the .data section. defined in linker script */
23.word _sdata
24/* end address for the .data section. defined in linker script */
25.word _edata
26/* start address for the .bss section. defined in linker script */
27.word _sbss
28/* end address for the .bss section. defined in linker script */
29.word _ebss
30
31/*************************************************************************
32* Chip init.
33*      1. Load flash configuration
34*      2. Load ANA_REG(B/C/D/E) information
35*      3. Load ANA_REG10 information
36
37**************************************************************************/
38.if (__CHIPINITIAL != 0)
39  .section .chipinit_section.__CHIP_INIT
40__CHIP_INIT:
41CONFIG1_START:
42        /*-------------------------------*/
43        /* 1. Load flash configuration */
44        /* Unlock flash */
45        LDR     R0, =0x000FFFE0
46        LDR     R1, =0x55AAAA55
47        STR     R1, [R0]
48        /* Load configure word 0 to 7
49           Compare bit[7:0] */
50        LDR     R0, =0x00080E00
51        LDR     R1, =0x20
52        LDR     R2, =0x000FFFE8
53        LDR     R3, =0x000FFFF0
54        LDR     R4, =0x0
55        LDR     R7, =0x0FF
56FLASH_CONF_START_1:
57        LDR     R5, [R0]
58        STR     R4, [R2]
59        STR     R5, [R3]
60        LDR     R6, [R3]
61        ANDS    R5, R7
62        ANDS    R6, R7
63        CMP     R5, R6
64        BNE     FLASH_CONF_AGAIN_1
65        ADDS    R4, #4
66        ADDS    R0, #4
67        CMP     R1, R4
68        BEQ     FLASH_CONF_END_1
69        B       FLASH_CONF_START_1
70FLASH_CONF_AGAIN_1:
71        LDR     R5, [R0]
72        STR     R4, [R2]
73        STR     R5, [R3]
74        LDR     R6, [R3]
75        ANDS    R5, R7
76        ANDS    R6, R7
77        CMP     R5, R6
78FLASH_CONF_WHILELOOP_1:
79        BNE     FLASH_CONF_WHILELOOP_1
80        ADDS    R4, #4
81        ADDS    R0, #4
82        CMP     R1, R4
83        BEQ     FLASH_CONF_END_1
84        B       FLASH_CONF_START_1
85FLASH_CONF_END_1:
86        /* Load configure word 8 to 11
87           Compare bit 31,24,23:16,8,7:0 */
88        LDR     R1, =0x30
89        LDR     R7, =0x81FF81FF
90FLASH_CONF_START_2:
91        LDR     R5, [R0]
92        STR     R4, [R2]
93        STR     R5, [R3]
94        LDR     R6, [R3]
95        ANDS    R5, R7
96        ANDS    R6, R7
97        CMP     R5, R6
98        BNE     FLASH_CONF_AGAIN_1
99        ADDS    R4, #4
100        ADDS    R0, #4
101        CMP     R1, R4
102        BEQ     FLASH_CONF_END_2
103        B       FLASH_CONF_START_2
104FLASH_CONF_AGAIN_2:
105        LDR     R5, [R0]
106        STR     R4, [R2]
107        STR     R5, [R3]
108        LDR     R6, [R3]
109        ANDS    R5, R7
110        ANDS    R6, R7
111        CMP     R5, R6
112FLASH_CONF_WHILELOOP_2:
113        BNE     FLASH_CONF_WHILELOOP_2
114        ADDS    R4, #4
115        ADDS    R0, #4
116        CMP     R1, R4
117        BEQ     FLASH_CONF_END_2
118        B       FLASH_CONF_START_2
119FLASH_CONF_END_2:
120        /* Lock flash */
121        LDR     R0, =0x000FFFE0
122        LDR     R1, =0x0
123        STR     R1, [R0]
124        /*-------------------------------*/
125        /* 2. Load ANA_REG(B/C/D/E) information */
126CONFIG2_START:
127        LDR     R4, =0x4001422C
128        LDR     R5, =0x40014230
129        LDR     R6, =0x40014234
130        LDR     R7, =0x40014238
131        LDR     R0, =0x80DC0
132        LDR     R0, [R0]
133        LDR     R1, =0x80DC4
134        LDR     R1, [R1]
135        ADDS    R2, R0, R1
136        ADDS    R2, #0x0FFFFFFFF
137        MVNS    R2, R2
138        LDR     R3, =0x80DCC
139        LDR     R3, [R3]
140        CMP     R3, R2
141        BEQ     ANADAT_CHECKSUM1_OK
142        B       ANADAT_CHECKSUM1_ERR
143ANADAT_CHECKSUM1_OK:
144        /* ANA_REGB */
145        LDR     R1, =0x0FF
146        ANDS    R1, R0
147        STR     R1, [R4]
148        /* ANA_REGC */
149        LDR     R1, =0x0FF00
150        ANDS    R1, R0
151        LSRS    R1, R1, #8
152        STR     R1, [R5]
153        /* ANA_REGD */
154        LDR     R1, =0x0FF0000
155        ANDS    R1, R0
156        LSRS    R1, R1, #16
157        STR     R1, [R6]
158        /* ANA_REGE */
159        LDR     R1, =0x0FF000000
160        ANDS    R1, R0
161        LSRS    R1, R1, #24
162        STR     R1, [R7]
163        B       CONFIG3_START
164ANADAT_CHECKSUM1_ERR:
165        LDR     R0, =0x80DD0
166        LDR     R0, [R0]
167        LDR     R1, =0x80DD4
168        LDR     R1, [R1]
169        ADDS    R2, R0, R1
170        ADDS    R2, #0x0FFFFFFFF
171        MVNS    R2, R2
172        LDR     R3, =0x80DDC
173        LDR     R3, [R3]
174        CMP     R3, R2
175        BEQ     ANADAT_CHECKSUM2_OK
176        B       ANADAT_CHECKSUM2_ERR
177ANADAT_CHECKSUM2_OK:
178        /* ANA_REGB */
179        LDR     R1, =0x0FF
180        ANDS    R1, R0
181        STR     R1, [R4]
182        /* ANA_REGC */
183        LDR     R1, =0x0FF00
184        ANDS    R1, R0
185        LSRS    R1, R1, #8
186        STR     R1, [R5]
187        /* ANA_REGD */
188        LDR     R1, =0x0FF0000
189        ANDS    R1, R0
190        LSRS    R1, R1, #16
191        STR     R1, [R6]
192        /* ANA_REGE */
193        LDR     R1, =0x0FF000000
194        ANDS    R1, R0
195        LSRS    R1, R1, #24
196        STR     R1, [R7]
197        B       CONFIG3_START
198ANADAT_CHECKSUM2_ERR:
199        B       ANADAT_CHECKSUM2_ERR
200        /*-------------------------------*/
201        /* 3. Load ANA_REG10 information */
202CONFIG3_START:
203        LDR     R7, =0x40014240
204        LDR     R0, =0x80DE0
205        LDR     R0, [R0]
206        LDR     R1, =0x80DE4
207        LDR     R1, [R1]
208        MVNS    R1, R1
209        CMP     R1, R0
210        BEQ     ANADAT10_CHECKSUM1_OK
211        B       ANADAT10_CHECKSUM1_ERR
212ANADAT10_CHECKSUM1_OK:
213        /* ANA_REG10 */
214        LDR     R1, =0x0FF
215        ANDS    R1, R0
216        STR     R1, [R7]
217        BX      LR
218ANADAT10_CHECKSUM1_ERR:
219        LDR     R0, =0x80DE8
220        LDR     R0, [R0]
221        LDR     R1, =0x80DEC
222        LDR     R1, [R1]
223        MVNS    R1, R1
224        CMP     R1, R0
225        BEQ     ANADAT10_CHECKSUM2_OK
226        B       ANADAT10_CHECKSUM2_ERR
227ANADAT10_CHECKSUM2_OK:
228        /* ANA_REG10 */
229        LDR     R1, =0x0FF
230        ANDS    R1, R0
231        STR     R1, [R7]
232        BX      LR
233ANADAT10_CHECKSUM2_ERR:
234        B       ANADAT10_CHECKSUM2_ERR
235.size __CHIP_INIT, .-__CHIP_INIT
236.endif
237
238
239.if (__CHIPINITIAL != 0)
240  .global __CHIP_INIT
241  .section .chipinit_section.Reset_Handler
242.else
243  .section .text.Reset_Handler
244.endif
245  .weak Reset_Handler
246  .type Reset_Handler, %function
247Reset_Handler:
248
249.if (__CHIPINITIAL != 0)
250/* Chip Initiliazation */
251  bl    __CHIP_INIT
252/* System Initiliazation */
253  bl SystemInit
254.endif
255
256/* set stack pointer */
257  ldr   r0, =_estack
258  mov   sp, r0
259
260/* Copy the data segment initializers from flash to SRAM */
261  movs r1, #0
262  b LoopCopyDataInit
263
264CopyDataInit:
265  ldr r3, =_sidata
266  ldr r3, [r3, r1]
267  str r3, [r0, r1]
268  adds r1, r1, #4
269
270LoopCopyDataInit:
271  ldr r0, =_sdata
272  ldr r3, =_edata
273  adds r2, r0, r1
274  cmp r2, r3
275  bcc CopyDataInit
276  ldr r2, =_sbss
277  b LoopFillZerobss
278/* Zero fill the bss segment. */
279FillZerobss:
280  movs r3, #0
281  str  r3, [r2]
282  adds r2, r2, #4
283
284LoopFillZerobss:
285  ldr r3, = _ebss
286  cmp r2, r3
287  bcc FillZerobss
288
289/* Call static constructors */
290  bl __libc_init_array
291/* Call the application's entry point.*/
292  bl main
293
294LoopForever:
295    b LoopForever
296
297.size Reset_Handler, .-Reset_Handler
298
299/**
300 * @brief  This is the code that gets called when the processor receives an
301 *         unexpected interrupt.  This simply enters an infinite loop, preserving
302 *         the system state for examination by a debugger.
303 *
304 * @param  None
305 * @retval : None
306*/
307    .section .text.Default_Handler,"ax",%progbits
308Default_Handler:
309Infinite_Loop:
310  b Infinite_Loop
311  .size Default_Handler, .-Default_Handler
312/******************************************************************************
313*
314* The minimal vector table for a Cortex M0.  Note that the proper constructs
315* must be placed on this to ensure that it ends up at physical address
316* 0x0000.0000.
317*
318******************************************************************************/
319   .section .isr_vector,"a",%progbits
320  .type g_pfnVectors, %object
321  .size g_pfnVectors, .-g_pfnVectors
322
323
324g_pfnVectors:
325  .word  _estack
326  .word  Reset_Handler
327  .word  NMI_Handler
328  .word  HardFault_Handler
329  .word  0
330  .word  0
331  .word  0
332  .word  0
333  .word  0
334  .word  0
335  .word  0
336  .word  SVC_Handler
337  .word  0
338  .word  0
339  .word  PendSV_Handler
340  .word  SysTick_Handler
341
342  /* External Interrupts */
343  .word  PMU_IRQHandler                    /*  0: PMU       */
344  .word  RTC_IRQHandler                    /*  1: RTC       */
345  .word  U32K0_IRQHandler                  /*  2: U32K0     */
346  .word  U32K1_IRQHandler                  /*  3: U32K1     */
347  .word  I2C_IRQHandler                    /*  4: I2C       */
348  .word  SPI1_IRQHandler                   /*  5: SPI1      */
349  .word  UART0_IRQHandler                  /*  6: UART0     */
350  .word  UART1_IRQHandler                  /*  7: UART1     */
351  .word  UART2_IRQHandler                  /*  8: UART2     */
352  .word  UART3_IRQHandler                  /*  9: UART3     */
353  .word  UART4_IRQHandler                  /* 10: UART4     */
354  .word  UART5_IRQHandler                  /* 11: UART5     */
355  .word  ISO78160_IRQHandler               /* 12: ISO78160  */
356  .word  ISO78161_IRQHandler               /* 13: ISO78161  */
357  .word  TMR0_IRQHandler                   /* 14: TMR0      */
358  .word  TMR1_IRQHandler                   /* 15: TMR1      */
359  .word  TMR2_IRQHandler                   /* 16: TMR2      */
360  .word  TMR3_IRQHandler                   /* 17: TMR3      */
361  .word  PWM0_IRQHandler                   /* 18: PWM0      */
362  .word  PWM1_IRQHandler                   /* 19: PWM1      */
363  .word  PWM2_IRQHandler                   /* 20: PWM2      */
364  .word  PWM3_IRQHandler                   /* 21: PWM3      */
365  .word  DMA_IRQHandler                    /* 22: DMA       */
366  .word  FLASH_IRQHandler                  /* 23: FLASH     */
367  .word  ANA_IRQHandler                    /* 24: ANA       */
368  .word  0                                 /* 25: Reserved  */
369  .word  0                                 /* 26: Reserved  */
370  .word  SPI2_IRQHandler                   /* 27: SPI2      */
371  .word  SPI3_IRQHandler                   /* 28: SPI3      */
372  .word  0                                 /* 29: Reserved  */
373  .word  0                                 /* 30: Reserved  */
374  .word  0                                 /* 31: Reserved  */
375
376/*******************************************************************************
377*
378* Provide weak aliases for each Exception handler to the Default_Handler.
379* As they are weak aliases, any function with the same name will override
380* this definition.
381*
382*******************************************************************************/
383
384  .weak      NMI_Handler
385  .thumb_set NMI_Handler,Default_Handler
386
387  .weak      HardFault_Handler
388  .thumb_set HardFault_Handler,Default_Handler
389
390  .weak      SVC_Handler
391  .thumb_set SVC_Handler,Default_Handler
392
393  .weak      PendSV_Handler
394  .thumb_set PendSV_Handler,Default_Handler
395
396  .weak      SysTick_Handler
397  .thumb_set SysTick_Handler,Default_Handler
398
399  .weak      PMU_IRQHandler
400  .thumb_set PMU_IRQHandler,Default_Handler
401
402  .weak      RTC_IRQHandler
403  .thumb_set RTC_IRQHandler,Default_Handler
404
405  .weak      U32K0_IRQHandler
406  .thumb_set U32K0_IRQHandler,Default_Handler
407
408  .weak      U32K1_IRQHandler
409  .thumb_set U32K1_IRQHandler,Default_Handler
410
411  .weak      I2C_IRQHandler
412  .thumb_set I2C_IRQHandler,Default_Handler
413
414  .weak      SPI1_IRQHandler
415  .thumb_set SPI1_IRQHandler,Default_Handler
416
417  .weak      UART0_IRQHandler
418  .thumb_set UART0_IRQHandler,Default_Handler
419
420  .weak      UART1_IRQHandler
421  .thumb_set UART1_IRQHandler,Default_Handler
422
423  .weak      UART2_IRQHandler
424  .thumb_set UART2_IRQHandler,Default_Handler
425
426  .weak      UART3_IRQHandler
427  .thumb_set UART3_IRQHandler,Default_Handler
428
429  .weak      UART4_IRQHandler
430  .thumb_set UART4_IRQHandler,Default_Handler
431
432  .weak      UART5_IRQHandler
433  .thumb_set UART5_IRQHandler,Default_Handler
434
435  .weak      ISO78160_IRQHandler
436  .thumb_set ISO78160_IRQHandler,Default_Handler
437
438  .weak      ISO78161_IRQHandler
439  .thumb_set ISO78161_IRQHandler,Default_Handler
440
441  .weak      TMR0_IRQHandler
442  .thumb_set TMR0_IRQHandler,Default_Handler
443
444  .weak      TMR1_IRQHandler
445  .thumb_set TMR1_IRQHandler,Default_Handler
446
447  .weak      TMR2_IRQHandler
448  .thumb_set TMR2_IRQHandler,Default_Handler
449
450  .weak      TMR3_IRQHandler
451  .thumb_set TMR3_IRQHandler,Default_Handler
452
453  .weak      PWM0_IRQHandler
454  .thumb_set PWM0_IRQHandler,Default_Handler
455
456  .weak      PWM1_IRQHandler
457  .thumb_set PWM1_IRQHandler,Default_Handler
458
459  .weak      PWM2_IRQHandler
460  .thumb_set PWM2_IRQHandler,Default_Handler
461
462  .weak      PWM3_IRQHandler
463  .thumb_set PWM3_IRQHandler,Default_Handler
464
465  .weak      DMA_IRQHandler
466  .thumb_set DMA_IRQHandler,Default_Handler
467
468  .weak      FLASH_IRQHandler
469  .thumb_set FLASH_IRQHandler,Default_Handler
470
471  .weak      ANA_IRQHandler
472  .thumb_set ANA_IRQHandler,Default_Handler
473
474  .weak      SPI2_IRQHandler
475  .thumb_set SPI2_IRQHandler,Default_Handler
476
477  .weak      SPI3_IRQHandler
478  .thumb_set SPI3_IRQHandler,Default_Handler
479