1 /**
2   ******************************************************************************
3   * @file    lib_cortex.c
4   * @author  Application Team
5   * @version V4.4.0
6   * @date    2018-09-27
7   * @brief   Cortex module driver.
8   ******************************************************************************
9   * @attention
10   *
11   ******************************************************************************
12   */
13 
14 /* Includes ------------------------------------------------------------------*/
15 #include "lib_cortex.h"
16 #include "core_cm0.h"
17 
18 /**
19   * @brief  1. Clears Pending of a device specific External Interrupt.
20   *         2. Sets Priority of a device specific External Interrupt.
21   *         3. Enables a device specific External Interrupt.
22   * @param  IRQn: External interrupt number .
23   *         This parameter can be an enumerator of IRQn_Type enumeration
24   *         (For the complete target Devices IRQ Channels list, please refer to target.h file)
25   * @param  Priority: The preemption priority for the IRQn channel.
26   *         This parameter can be a value between 0 and 3.
27   *         A lower priority value indicates a higher priority
28   * @retval None
29   */
CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn,uint32_t Priority)30 void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority)
31 {
32   /* Check parameters */
33   assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
34   assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
35 
36   /* Clear Pending Interrupt */
37   NVIC_ClearPendingIRQ(IRQn);
38   /* Set Interrupt Priority */
39   NVIC_SetPriority(IRQn, Priority);
40   /* Enable Interrupt in NVIC */
41   NVIC_EnableIRQ(IRQn);
42 }
43 
44 /**
45   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
46   * @note   To configure interrupts priority correctly before calling it.
47   * @param  IRQn External interrupt number.
48   *         This parameter can be an enumerator of IRQn_Type enumeration
49   *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
50   * @retval None
51   */
CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn)52 void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn)
53 {
54   /* Check parameters */
55   assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
56   /* Enable interrupt in NVIC */
57   NVIC_EnableIRQ(IRQn);
58 }
59 
60 /**
61   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
62   * @param  IRQn External interrupt number.
63   *         This parameter can be an enumerator of IRQn_Type enumeration
64   *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
65   * @retval None
66   */
CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn)67 void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn)
68 {
69   /* Check parameters */
70   assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
71   /* Disable interrupt in NVIC */
72   NVIC_DisableIRQ(IRQn);
73 }
74 
75 /**
76   * @brief  Initiates a system reset request to reset the MCU.
77   * @retval None
78   */
CORTEX_NVIC_SystemReset(void)79 void CORTEX_NVIC_SystemReset(void)
80 {
81   /* System Reset */
82   NVIC_SystemReset();
83 }
84 
85 /**
86   * @brief  Gets the Pending bit of an interrupt.
87   * @param  IRQn: External interrupt number.
88   *         This parameter can be an enumerator of IRQn_Type enumeration
89   *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
90   * @retval 0  Interrupt status is not pending.
91             1  Interrupt status is pending.
92   */
CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn)93 uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn)
94 {
95   /* Check parameters */
96   assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
97   /* Get priority for Cortex-M0 system or device specific interrupts */
98   return NVIC_GetPendingIRQ(IRQn);
99 }
100 
101 /**
102   * @brief  Sets Pending bit of an external interrupt.
103   * @param  IRQn External interrupt number
104   *         This parameter can be an enumerator of IRQn_Type enumeration
105   *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
106   * @retval None
107   */
CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn)108 void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn)
109 {
110   /* Check parameters */
111   assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
112   /* Set interrupt pending */
113   NVIC_SetPendingIRQ(IRQn);
114 }
115 
116 /**
117   * @brief  Clears the pending bit of an external interrupt.
118   * @param  IRQn External interrupt number.
119   *         This parameter can be an enumerator of IRQn_Type enumeration
120   *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
121   * @retval None
122   */
CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn)123 void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
124 {
125   /* Check parameters */
126   assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
127   /* Clear interrupt pending */
128   NVIC_ClearPendingIRQ(IRQn);
129 }
130 
131 /**
132   * @brief  Gets the priority of an interrupt.
133   * @param  IRQn: External interrupt number.
134   *         This parameter can be an enumerator of IRQn_Type enumeration
135   *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
136   * @retval Interrupt Priority. Value is aligned automatically to the implemented
137   *         priority bits of the microcontroller.
138   */
CORTEX_NVIC_GetPriority(IRQn_Type IRQn)139 uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn)
140 {
141   /* Get priority for Cortex-M0 system or device specific interrupts */
142   return NVIC_GetPriority(IRQn);
143 }
144 
145 /**
146   * @brief  Sets the priority of an interrupt.
147   * @param  IRQn: External interrupt number .
148   *         This parameter can be an enumerator of IRQn_Type enumeration
149   *         (For the complete target Devices IRQ Channels list, please refer to target.h file)
150   * @param  Priority: The preemption priority for the IRQn channel.
151   *         This parameter can be a value between 0 and 3.
152   *         A lower priority value indicates a higher priority
153   * @retval None
154   */
CORTEX_NVIC_SetPriority(IRQn_Type IRQn,uint32_t Priority)155 void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority)
156 {
157   /* Check parameters */
158   assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
159   /* Get priority for Cortex-M0 system or device specific interrupts */
160   NVIC_SetPriority(IRQn, Priority);
161 }
162 
163 /**
164   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
165   *         Counter is in free running mode to generate periodic interrupts.
166   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
167   * @retval status:  - 0  Function succeeded.
168   *                  - 1  Function failed.
169   */
CORTEX_SystemTick_Config(uint32_t TicksNum)170 uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum)
171 {
172   return SysTick_Config(TicksNum);
173 }
174 
175 /*********************************** END OF FILE ******************************/
176