1 /*
2 * drivers/video/sunxi/disp2/disp/lcd/WilliamLcd.c
3 *
4 * Allwinner SoCs display driver.
5 *
6 * WilliamLcd panel driver
7 *
8 * Copyright (C) 2016 Allwinner.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include "WilliamLcd.h"
16
17 #define panel_reset(val) sunxi_lcd_gpio_set_value(sel, 0, val)
18 #define panel_power_en(val) sunxi_lcd_gpio_set_value(sel, 1, val)
19
20 static void LCD_power_on(u32 sel);
21 static void LCD_power_off(u32 sel);
22 static void LCD_bl_open(u32 sel);
23 static void LCD_bl_close(u32 sel);
24
25 static void LCD_panel_init(u32 sel);
26 static void LCD_panel_exit(u32 sel);
27
28
LCD_cfg_panel_info(struct panel_extend_para * info)29 static void LCD_cfg_panel_info(struct panel_extend_para *info)
30 {
31 u32 i = 0, j = 0;
32 u32 items;
33 u8 lcd_gamma_tbl[][2] = {
34 /* {input value, corrected value} */
35 {0, 0},
36 {15, 15},
37 {30, 30},
38 {45, 45},
39 {60, 60},
40 {75, 75},
41 {90, 90},
42 {105, 105},
43 {120, 120},
44 {135, 135},
45 {150, 150},
46 {165, 165},
47 {180, 180},
48 {195, 195},
49 {210, 210},
50 {225, 225},
51 {240, 240},
52 {255, 255},
53 };
54
55
56 u32 lcd_cmap_tbl[2][3][4] = {
57 {
58 {LCD_CMAP_G0, LCD_CMAP_B1, LCD_CMAP_G2, LCD_CMAP_B3},
59 {LCD_CMAP_B0, LCD_CMAP_R1, LCD_CMAP_B2, LCD_CMAP_R3},
60 {LCD_CMAP_R0, LCD_CMAP_G1, LCD_CMAP_R2, LCD_CMAP_G3},
61 },
62 {
63 {LCD_CMAP_B3, LCD_CMAP_G2, LCD_CMAP_B1, LCD_CMAP_G0},
64 {LCD_CMAP_R3, LCD_CMAP_B2, LCD_CMAP_R1, LCD_CMAP_B0},
65 {LCD_CMAP_G3, LCD_CMAP_R2, LCD_CMAP_G1, LCD_CMAP_R0},
66 },
67 };
68
69
70 items = sizeof(lcd_gamma_tbl)/2;
71 for (i = 0; i < items - 1; i++) {
72 u32 num = lcd_gamma_tbl[i+1][0] - lcd_gamma_tbl[i][0];
73
74 for (j = 0; j < num; j++) {
75 u32 value = 0;
76
77 value = lcd_gamma_tbl[i][1] + ((lcd_gamma_tbl[i+1][1] - lcd_gamma_tbl[i][1]) * j)/num;
78 info->lcd_gamma_tbl[lcd_gamma_tbl[i][0] + j] = (value<<16) + (value<<8) + value;
79 }
80 }
81 info->lcd_gamma_tbl[255] = (lcd_gamma_tbl[items-1][1]<<16)
82 + (lcd_gamma_tbl[items-1][1]<<8) + lcd_gamma_tbl[items-1][1];
83
84
85 memcpy(info->lcd_cmap_tbl, lcd_cmap_tbl, sizeof(lcd_cmap_tbl));
86
87 }
88
LCD_open_flow(u32 sel)89 static __s32 LCD_open_flow(u32 sel)
90 {
91 /* open lcd power, and delay 50ms */
92 LCD_OPEN_FUNC(sel, LCD_power_on, 50);
93 /* open lcd power, than delay 200ms */
94 LCD_OPEN_FUNC(sel, LCD_panel_init, 200);
95 /* open lcd controller, and delay 100ms */
96 LCD_OPEN_FUNC(sel, sunxi_lcd_tcon_enable, 100);
97 /* open lcd backlight, and delay 0ms */
98 LCD_OPEN_FUNC(sel, LCD_bl_open, 0);
99
100 return 0;
101 }
102
LCD_close_flow(u32 sel)103 static __s32 LCD_close_flow(u32 sel)
104 {
105 /* close lcd backlight, and delay 0ms */
106 LCD_CLOSE_FUNC(sel, LCD_bl_close, 0);
107 /* close lcd controller, and delay 0ms */
108 LCD_CLOSE_FUNC(sel, sunxi_lcd_tcon_disable, 0);
109 /* open lcd power, than delay 200ms */
110 LCD_CLOSE_FUNC(sel, LCD_panel_exit, 20);
111 /* cose lcd power, and delay 500ms */
112 LCD_CLOSE_FUNC(sel, LCD_power_off, 50);
113
114 return 0;
115 }
116
LCD_power_on(u32 sel)117 static void LCD_power_on(u32 sel)
118 {
119 /* config lcd_power pin to open lcd power0 */
120 sunxi_lcd_power_enable(sel, 1);
121 sunxi_lcd_delay_ms(5);
122 /* config lcd_power pin to open lcd power1 */
123 sunxi_lcd_power_enable(sel, 0);
124 sunxi_lcd_delay_ms(5);
125 panel_power_en(1);
126 sunxi_lcd_pin_cfg(sel, 1);
127 sunxi_lcd_delay_ms(10);
128 panel_reset(1);
129 sunxi_lcd_delay_ms(10);
130 panel_reset(0);
131 sunxi_lcd_delay_ms(20);
132 panel_reset(1);
133 }
134
LCD_power_off(u32 sel)135 static void LCD_power_off(u32 sel)
136 {
137 sunxi_lcd_pin_cfg(sel, 0);
138 panel_power_en(0);
139 /* config lcd_power pin to close lcd power1 */
140 sunxi_lcd_power_disable(sel, 0);
141 /* config lcd_power pin to close lcd power0 */
142 sunxi_lcd_power_disable(sel, 1);
143 sunxi_lcd_pwm_disable(sel); /*close pwm module */
144 }
145
LCD_bl_open(u32 sel)146 static void LCD_bl_open(u32 sel)
147 {
148 /* open pwm module */
149 sunxi_lcd_pwm_enable(sel);
150 /* config lcd_bl_en pin to open lcd backlight */
151 sunxi_lcd_backlight_enable(sel);
152 }
153
LCD_bl_close(u32 sel)154 static void LCD_bl_close(u32 sel)
155 {
156 /* config lcd_bl_en pin to close lcd backlight */
157 sunxi_lcd_backlight_disable(sel);
158 /* close pwm module */
159 sunxi_lcd_pwm_disable(sel);
160 }
161 #if 1
162
163 #define REGFLAG_DELAY 0XFF
164 #define REGFLAG_END_OF_TABLE 0xFE /* END OF REGISTERS MARKER */
165
166 struct LCM_setting_table {
167 u8 cmd;
168 u32 count;
169 u8 para_list[64];
170 };
171
172
173 static struct LCM_setting_table lcm_initialization_setting[] = {
174 {0xE0, 1, {0x00} },
175 {0xE1, 1, {0x93} },
176 {0xE2, 1, {0x65} },
177 {0xE3, 1, {0xF8} },
178 {0x80, 1, {0x03} }, /* 4Lanes */
179 {0xE0, 1, {0x04} },
180 {0x2D, 1, {0x03} }, /* 4Lanes */
181 {0xE0, 1, {0x01} },
182 {0x00, 1, {0x00} },
183 {0x01, 1, {0x6F} },
184 {0x03, 1, {0x00} },
185 {0x04, 1, {0x6F} },
186 {0x17, 1, {0x00} },
187 {0x18, 1, {0xD7} }, /* VGMP=4.8V */
188 {0x19, 1, {0x05} },
189 {0x1A, 1, {0x00} },
190 {0x1B, 1, {0xD7} }, /* VGMN=-4.8V */
191 {0x1C, 1, {0x05} },
192 {0x1F, 1, {0x79} }, /* VGH_REG=18V */
193 {0x20, 1, {0x2D} }, /* VGL_REG=-12V */
194 {0x21, 1, {0x2D} }, /* VGL_REG2=-12V */
195 {0x22, 1, {0x4F} },
196 {0x26, 1, {0xF1} }, /* VDDD from IOVCC */
197 {0x37, 1, {0x09} }, /* SS=1, 1, {BGR=1 */
198 {0x38, 1, {0x04} }, /* JDT=100 column inversion */
199 {0x39, 1, {0x08} }, /* RGB_N_EQ1, 1, { modify 20140806 */
200 {0x3A, 1, {0x12} }, /* RGB_N_EQ2, 1, { modify 20140806 */
201 {0x3C, 1, {0x78} }, /* SET EQ3 for TE_H */
202 {0x3E, 1, {0x80} }, /* SET CHGEN_OFF, 1, { modify 20140806 */
203 {0x3F, 1, {0x80} }, /* SET CHGEN_OFF2, 1, { modify 20140806 */
204 {0x40, 1, {0x06} }, /* RSO=800 RGB */
205 {0x41, 1, {0xA0} }, /* LN=640->1280 line */
206 {0x55, 1, {0x0F} }, /* DCDCM=1111, 1, { no output */
207 {0x56, 1, {0x01} },
208 {0x57, 1, {0xA8} }, /*[7:5]VGH_RT, 1, {[4:2]=VGL_RT, 1, {[1:0]=VCL_RT*/
209 {0x58, 1, {0x0A} }, /* AVDD_S */
210 {0x59, 1, {0x2A} }, /* VCL = -2.7V */
211 {0x5A, 1, {0x37} }, /* VGH = 19V */
212 {0x5B, 1, {0x19} },/* VGL = -12V */
213 {0x5D, 1, {0x70} },
214 {0x5E, 1, {0x50} },
215 {0x5F, 1, {0x3F} },
216 {0x60, 1, {0x31} },
217 {0x61, 1, {0x2D} },
218 {0x62, 1, {0x1D} },
219 {0x63, 1, {0x22} },
220 {0x64, 1, {0x0C} },
221 {0x65, 1, {0x25} },
222 {0x66, 1, {0x24} },
223 {0x67, 1, {0x24} },
224 {0x68, 1, {0x41} },
225 {0x69, 1, {0x2F} },
226 {0x6A, 1, {0x36} },
227 {0x6B, 1, {0x28} },
228 {0x6C, 1, {0x26} },
229 {0x6D, 1, {0x1C} },
230 {0x6E, 1, {0x08} },
231 {0x6F, 1, {0x02} },
232 {0x70, 1, {0x70} },
233 {0x71, 1, {0x50} },
234 {0x72, 1, {0x3F} },
235 {0x73, 1, {0x31} },
236 {0x74, 1, {0x2D} },
237 {0x75, 1, {0x1D} },
238 {0x76, 1, {0x22} },
239 {0x77, 1, {0x0C} },
240 {0x78, 1, {0x25} },
241 {0x79, 1, {0x24} },
242 {0x7A, 1, {0x24} },
243 {0x7B, 1, {0x41} },
244 {0x7C, 1, {0x2F} },
245 {0x7D, 1, {0x36} },
246 {0x7E, 1, {0x28} },
247 {0x7F, 1, {0x26} },
248 {0x80, 1, {0x1C} },
249 {0x81, 1, {0x08} },
250 {0x82, 1, {0x02} },
251 {0xE0, 1, {0x02} },
252 {0x00, 1, {0x00} },
253 {0x01, 1, {0x04} },
254 {0x02, 1, {0x06} },
255 {0x03, 1, {0x08} },
256 {0x04, 1, {0x0A} },
257 {0x05, 1, {0x0C} },
258 {0x06, 1, {0x0E} },
259 {0x07, 1, {0x17} },
260 {0x08, 1, {0x37} },
261 {0x09, 1, {0x1F} },
262 {0x0A, 1, {0x10} },
263 {0x0B, 1, {0x1F} },
264 {0x0C, 1, {0x1F} },
265 {0x0D, 1, {0x1F} },
266 {0x0E, 1, {0x1F} },
267 {0x0F, 1, {0x1F} },
268 {0x10, 1, {0x1F} },
269 {0x11, 1, {0x1F} },
270 {0x12, 1, {0x1F} },
271 {0x13, 1, {0x12} },
272 {0x14, 1, {0x1F} },
273 {0x15, 1, {0x1F} },
274 {0x16, 1, {0x01} },
275 {0x17, 1, {0x05} },
276 {0x18, 1, {0x07} },
277 {0x19, 1, {0x09} },
278 {0x1A, 1, {0x0B} },
279 {0x1B, 1, {0x0D} },
280 {0x1C, 1, {0x0F} },
281 {0x1D, 1, {0x17} },
282 {0x1E, 1, {0x37} },
283 {0x1F, 1, {0x1F} },
284 {0x20, 1, {0x11} },
285 {0x21, 1, {0x1F} },
286 {0x22, 1, {0x1F} },
287 {0x23, 1, {0x1F} },
288 {0x24, 1, {0x1F} },
289 {0x25, 1, {0x1F} },
290 {0x26, 1, {0x1F} },
291 {0x27, 1, {0x1F} },
292 {0x28, 1, {0x1F} },
293 {0x29, 1, {0x13} },
294 {0x2A, 1, {0x1F} },
295 {0x2B, 1, {0x1F} },
296 {0x2C, 1, {0x11} },
297 {0x2D, 1, {0x0F} },
298 {0x2E, 1, {0x0D} },
299 {0x2F, 1, {0x0B} },
300 {0x30, 1, {0x09} },
301 {0x31, 1, {0x07} },
302 {0x32, 1, {0x05} },
303 {0x33, 1, {0x37} },
304 {0x34, 1, {0x17} },
305 {0x35, 1, {0x1F} },
306 {0x36, 1, {0x01} },
307 {0x37, 1, {0x1F} },
308 {0x38, 1, {0x1F} },
309 {0x39, 1, {0x1F} },
310 {0x3A, 1, {0x1F} },
311 {0x3B, 1, {0x1F} },
312 {0x3C, 1, {0x1F} },
313 {0x3D, 1, {0x1F} },
314 {0x3E, 1, {0x1F} },
315 {0x3F, 1, {0x13} },
316 {0x40, 1, {0x1F} },
317 {0x41, 1, {0x1F} },
318 {0x42, 1, {0x10} },
319 {0x43, 1, {0x0E} },
320 {0x44, 1, {0x0C} },
321 {0x45, 1, {0x0A} },
322 {0x46, 1, {0x08} },
323 {0x47, 1, {0x06} },
324 {0x48, 1, {0x04} },
325 {0x49, 1, {0x37} },
326 {0x4A, 1, {0x17} },
327 {0x4B, 1, {0x1F} },
328 {0x4C, 1, {0x00} },
329 {0x4D, 1, {0x1F} },
330 {0x4E, 1, {0x1F} },
331 {0x4F, 1, {0x1F} },
332 {0x50, 1, {0x1F} },
333 {0x51, 1, {0x1F} },
334 {0x52, 1, {0x1F} },
335 {0x53, 1, {0x1F} },
336 {0x54, 1, {0x1F} },
337 {0x55, 1, {0x12} },
338 {0x56, 1, {0x1F} },
339 {0x57, 1, {0x1F} },
340 {0x58, 1, {0x10} },
341 {0x59, 1, {0x00} },
342 {0x5A, 1, {0x00} },
343 {0x5B, 1, {0x10} },
344 {0x5C, 1, {0x07} },
345 {0x5D, 1, {0x30} },
346 {0x5E, 1, {0x00} },
347 {0x5F, 1, {0x00} },
348 {0x60, 1, {0x30} },
349 {0x61, 1, {0x03} },
350 {0x62, 1, {0x04} },
351 {0x63, 1, {0x03} },
352 {0x64, 1, {0x6A} }, /* SETV_OFF, 1, { modify 20140806 */
353 {0x65, 1, {0x75} },
354 {0x66, 1, {0x0D} },
355 {0x67, 1, {0xB3} },
356 {0x68, 1, {0x09} },
357 {0x69, 1, {0x06} },
358 {0x6A, 1, {0x6A} }, /* CKV_OFF, 1, { modify 20140806 */
359 {0x6B, 1, {0x04} },
360 {0x6C, 1, {0x00} },
361 {0x6D, 1, {0x04} },
362 {0x6E, 1, {0x04} },
363 {0x6F, 1, {0x88} },
364 {0x70, 1, {0x00} },
365 {0x71, 1, {0x00} },
366 {0x72, 1, {0x06} },
367 {0x73, 1, {0x7B} },
368 {0x74, 1, {0x00} },
369 {0x75, 1, {0xBC} },
370 {0x76, 1, {0x00} },
371 {0x77, 1, {0x0D} },
372 {0x78, 1, {0x2C} },
373 {0x79, 1, {0x00} },
374 {0x7A, 1, {0x00} },
375 {0x7B, 1, {0x00} },
376 {0x7C, 1, {0x00} },
377 {0x7D, 1, {0x03} },
378 {0x7E, 1, {0x7B} },
379 {0xE0, 1, {0x04} },
380 {0x2B, 1, {0x2B} },
381 {0x2E, 1, {0x44} },
382 {0xE0, 1, {0x00} },
383 {0xE6, 1, {0x02} }, /* Watch dog */
384 {0xE7, 1, {0x02} }, /* Watch dog */
385 {0x11, 1, {0x00} }, /* SLPOUT */
386 {REGFLAG_DELAY, 120, {} },
387 {0x29, 1, {0x00} }, /* DSPON */
388 {REGFLAG_DELAY, 5, {} },
389 {REGFLAG_END_OF_TABLE, 0x00, {} }
390 };
391 #endif
392
393
LCD_panel_init(u32 sel)394 static void LCD_panel_init(u32 sel)
395 {
396 u32 i;
397
398 for (i = 0; ; i++) {
399 if (lcm_initialization_setting[i].cmd == REGFLAG_END_OF_TABLE)
400 break;
401 else if (lcm_initialization_setting[i].cmd == REGFLAG_DELAY)
402 sunxi_lcd_delay_ms(lcm_initialization_setting[i].count);
403 else {
404 #ifdef SUPPORT_DSI
405 dsi_dcs_wr(0, lcm_initialization_setting[i].cmd,
406 lcm_initialization_setting[i].para_list,
407 lcm_initialization_setting[i].count);
408 #endif
409 }
410 }
411 /* Begin to translate data */
412 sunxi_lcd_dsi_clk_enable(sel);
413
414 return;
415 }
416
LCD_panel_exit(u32 sel)417 static void LCD_panel_exit(u32 sel)
418 {
419 sunxi_lcd_dsi_clk_disable(sel);
420 /* panel_reset(0); */
421 return;
422 }
423
424 /* sel: 0:lcd0; 1:lcd1 */
LCD_user_defined_func(u32 sel,u32 para1,u32 para2,u32 para3)425 static __s32 LCD_user_defined_func(u32 sel, u32 para1, u32 para2, u32 para3)
426 {
427 return 0;
428 }
429
430 struct __lcd_panel WilliamLcd_panel = {
431 /* panel driver name, must mach the name of lcd_drv_name in sys_config.fex */
432 .name = "WilliamLcd",
433 .func = {
434 .cfg_panel_info = LCD_cfg_panel_info,
435 .cfg_open_flow = LCD_open_flow,
436 .cfg_close_flow = LCD_close_flow,
437 .lcd_user_defined_func = LCD_user_defined_func,
438 },
439 };
440