1 /* 2 File Name : yc3121.h 3 Author : Yichip 4 Version : V1.0 5 Date : 2018/03/27 6 Description : Register and hardware information. 7 */ 8 9 #ifndef __YC3121_H__ 10 #define __YC3121_H__ 11 12 #include "type.h" 13 #include "system.h" 14 #include <string.h> 15 #include "rom_api.h" 16 17 #define NO_BT 0 18 #define EXIST_BT 1 19 #define NO_XTAL 2 20 21 #define VERSIONS EXIST_BT 22 23 #define M0_FPGA 1 24 #define POS_FPGA 2 25 #define POS_CHIP 3 26 27 #define HARDWAER POS_CHIP 28 29 #if (HARDWAER == M0_FPGA) 30 #define CPU_MHZ (24*1000000) 31 #elif (HARDWAER == POS_CHIP) 32 #define CRYSTAL_CLK (192*1000000) 33 #define CPU_MHZ ((CRYSTAL_CLK)/((SYSCTRL_HCLK_CON&0x0f)+2)) 34 #endif 35 36 #define noinline __attribute__((noinline)) 37 38 #define IPC_HOLD_BT *(volatile byte*)0xC4FEF 39 #define IPC_RX_START_ADDR (volatile byte*)0xc4ff0 40 #define IPC_RX_END_ADDR (volatile byte*)0xc4ff2 41 #define IPC_RX_READ_PTR (volatile byte*)0xc4ff4 42 #define IPC_RX_WRITE_PTR (volatile byte*)0xc4ff6 43 #define IPC_TX_START_ADDR (volatile byte*)0xc4ff8 44 #define IPC_TX_END_ADDR (volatile byte*)0xc4ffa 45 #define IPC_TX_READ_PTR (volatile byte*)0xc4ffc 46 #define IPC_TX_WRITE_PTR (volatile byte*)0xc4ffe 47 48 #define BT_REV *(volatile byte*)0xc8000 49 #define BT_STEP *(volatile byte*)0xc8001 50 #define BT_PC *(volatile word*)0xc800e 51 #define BT_RESET *(volatile byte*)0xc8010 52 #define BT_UCODE_HI *(volatile byte*)0xc8022 53 #define BT_UCODE_CTRL *(volatile byte*)0xc8023 54 #define BT_UCODE_LO *(volatile byte*)0xc8024 55 #define BT_UCODE_DATA *(volatile byte*)0xc8025 56 #define BT_RHALFSLOT_LOW *(volatile byte*)0xc8040 57 #define BT_CONTRU *(volatile byte*)0xc812c 58 #define BT_CONTWU *(volatile byte*)0xc812e 59 #define BT_CONFIG *(volatile byte*)0xc8043 60 #define BT_CLKPLL_EN *(volatile byte*)0xc8905 61 #define BT_CHGPUMP_EN *(volatile byte*)0xc8973 62 #define WAKEUP_BT *(volatile byte*)0xF853C 63 64 #define BT_INIT_FLAG 7 65 #define WAKEUP_BT_FLAG 2 66 67 //register base address 68 69 #define WDT_BASEADDR 0xf0000 70 #define SCI7816_BASEADDR 0xf0400 71 72 #define TIMER_BASEADDR 0xf0c00 73 #define SM4_BASEADDR 0xf5200 74 #define RSA_BASEADDR 0xf5800 75 #define USB_BASEADDR 0xf6000 76 #define DES_BASEADDR 0xf8000 77 #define CRC_BASEADDR 0xf8200 78 #define AES_BASEADDR 0xf8300 79 #define LPM_BASEADDR 0xf8400 80 #define SYSCTRL_BASEADDR 0xf8500 81 #define SECURE_BASEADDR 0xf8540 82 #define CLKGEN_BASEADDR 0xf8560 83 #define MPU_BASEADDR 0xf8580 84 #define SHA_BASEADDR 0xf8600 85 #define GPIO_BASEADDR 0xf8700 86 #define DMA_BASEADDR 0xf8800 87 #define QSPI_BASEADDR DMA_BASEADDR 88 #define ISO7811_BASEADDR 0xf8f00 89 90 #define WD_CONFIG *(volatile int*)(WDT_BASEADDR + 0x00) 91 #define WD_STATUS *(volatile int*)(WDT_BASEADDR + 0x04) 92 #define WD_KICK *(volatile int*)(WDT_BASEADDR + 0x08) 93 #define WD_CLEAR *(volatile int*)(WDT_BASEADDR + 0x0c) 94 95 #define SCI7816_MODE *(volatile int*)(SCI7816_BASEADDR + 0x00) 96 #define SCI7816_CTRL *(volatile int*)(SCI7816_BASEADDR + 0x08) 97 #define SCI7816_STAT *(volatile int*)(SCI7816_BASEADDR + 0x0c) 98 #define SCI7816_INT *(volatile int*)(SCI7816_BASEADDR + 0x10) 99 #define SCI7816_DATA *(volatile int*)(SCI7816_BASEADDR + 0x20) 100 #define SCI7816_ETU *(volatile int*)(SCI7816_BASEADDR + 0x28) 101 #define SCI7816_BGT *(volatile int*)(SCI7816_BASEADDR + 0x2c) 102 #define SCI7816_CWT *(volatile int*)(SCI7816_BASEADDR + 0x30) 103 #define SCI7816_EDC *(volatile int*)(SCI7816_BASEADDR + 0x34) 104 105 #define PWM_TOTAL 9 106 107 #define TIM_PCNT(x) *(volatile int*)(TIMER_BASEADDR + x*8) 108 #define TIM_NCNT(x) *(volatile int*)(TIMER_BASEADDR + 4 + x*8) 109 #define TIM_CTRL *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8) 110 #define TIM_CTRL1 *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8 + 4) 111 #define TIM_CNT(x) *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8 + (PWM_TOTAL*4 + 31)/32*4 + x*4) 112 113 #define SHA_DATA(x) *(volatile int*)(SHA_BASEADDR + 0x00 + x*4) 114 #define SHA_BDATA(x) *(volatile uint8_t*)(SHA_BASEADDR + 0x00 + x) 115 #define SHA_RESULT(x) *(volatile int*)(SHA_BASEADDR + 0x80 + x*4) 116 #define SHA_CTRL *(volatile int*)(SHA_BASEADDR + 0xc0) 117 118 #define SYSCTRL_PRIV_CTRL *(volatile int*)(SYSCTRL_BASEADDR + 0x0) 119 #define SYSCTRL_STATUS *(volatile int*)(SYSCTRL_BASEADDR + 0x4) 120 #define OTP_ADDR *(volatile short*)(SYSCTRL_BASEADDR + 0x8) 121 #define OTP_CTRL *(volatile short*)(SYSCTRL_BASEADDR + 0xa) 122 #define OTP_RDATA *(volatile byte*)(SYSCTRL_BASEADDR + 0xc) 123 #define OTP_STATUS *(volatile int*)(SYSCTRL_BASEADDR + 0xc) 124 125 #define SYSCTRL_LPM_RDATA *(volatile int*)(SYSCTRL_BASEADDR + 0x10) 126 #define SYSCTRL_LPM_SCB *(volatile int*)(SYSCTRL_BASEADDR + 0x14) 127 #define SYSCTRL_HWCTRL(x) *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x18 + x) 128 #define SYSCTRL_RNG_CTRL *(volatile int*)(SYSCTRL_BASEADDR + 0x28) 129 #define SYSCTRL_RNG_DATAB(x) *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x2c+x) 130 131 #define SYSCTRL_RNG_DATA(x) *(volatile int*)(SYSCTRL_BASEADDR + 0x2c+x*4) 132 133 #define SYSCTRL_ROM_SWITCH *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3c) 134 #define SYSCTRL_LPM_STATUS *(volatile byte *)(SYSCTRL_BASEADDR + 0x3d) 135 #define SYSCTRL_OTPN_ADDR *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3e) 136 #define SYSCTRL_OTPU_ADDR *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3f) 137 138 #define SECURE_CTRL *(volatile int*)(SECURE_BASEADDR + 0x0) 139 #define SECURE_STATUS *(volatile int*)(SECURE_BASEADDR + 0x4) 140 #define SECURE_MEDCON *(volatile int*)(SECURE_BASEADDR + 0x8) 141 #define SECURE_RAMKEY *(volatile int*)(SECURE_BASEADDR + 0xc) 142 143 #define SYSCTRL_HCLK_CON *(volatile int*)(CLKGEN_BASEADDR + 0x00) 144 #define SYSCTRL_RSACLK *(volatile int*)(CLKGEN_BASEADDR + 0x08) 145 #define SYSCTRL_CLK_CLS *(volatile int*)(CLKGEN_BASEADDR + 0x0c) 146 #define SYSCTRL_RST_EN *(volatile int*)(CLKGEN_BASEADDR + 0x14) 147 #define SYSCTRL_RST_TYPE *(volatile int*)(CLKGEN_BASEADDR + 0x18) 148 #define SYSCTRL_RESET *(volatile int*)(CLKGEN_BASEADDR + 0x1c) 149 150 #define MPUCTRL_ID *(volatile int*)(MPU_BASEADDR + 0x00) 151 #define MPUCTRL_CTRL *(volatile int*)(MPU_BASEADDR + 0x04) 152 #define MPUCTRL_FSR *(volatile int*)(MPU_BASEADDR + 0x0c) 153 #define MPUCTRL_FAR *(volatile int*)(MPU_BASEADDR + 0x10) 154 155 #define MPUCTRL_PROTECTION *(volatile int*)(MPU_BASEADDR + 0x14) 156 #define MPUCTRL_USER_START *(volatile int*)(MPU_BASEADDR + 0x18) 157 #define MPUCTRL_REGION_BASE(x) *(volatile int*)(MPU_BASEADDR + 0x40 + x*4) 158 #define MPUCTRL_REGION_LIMIT(x) *(volatile int*)(MPU_BASEADDR + 0x60 + x*4) 159 160 #define LPM_CTRL (volatile int*)(LPM_BASEADDR + 0x00) 161 #define LPM_SENSOR (volatile int*)(LPM_BASEADDR + 0x04) 162 #define LPM_WKUP_TIMER (volatile int*)(LPM_BASEADDR + 0x08) 163 #define LPM_SECMAX (volatile int*)(LPM_BASEADDR+0x0c) 164 #define LPM_GPIO_WKUP (volatile int*)(LPM_BASEADDR + 0x10) 165 #define LPM_GPIO_WKHI (volatile int*)(LPM_BASEADDR + 0x14) 166 #define LPM_SLEEP (volatile int*)(LPM_BASEADDR + 0x20) 167 #define LPM_CLR_INTR (volatile int*)(LPM_BASEADDR + 0x24) 168 #define LPM_STATUS (volatile int*)(LPM_BASEADDR + 0x78) 169 #define LPM_RTC_CNT (volatile int*)(LPM_BASEADDR + 0x7c) 170 #define LPM_KEY(x) (volatile int*)(LPM_BASEADDR + 0x80 + x*4) 171 172 #define GPIO_GROUP_NUM 3 173 #define GPIO_PIN_NUM 16 174 175 #define GPIO_CONFIG(x) *((volatile uint8_t*)(GPIO_BASEADDR + x)) 176 #define GPIO_INTR_EN(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+GPIO_GROUP_NUM*GPIO_PIN_NUM) + groupx) 177 #define GPIO_TRIG_MODE(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+(GPIO_GROUP_NUM*GPIO_PIN_NUM) +GPIO_GROUP_NUM*2) +groupx) 178 #define GPIO_IN(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+(GPIO_GROUP_NUM*GPIO_PIN_NUM) +GPIO_GROUP_NUM*4)+groupx) 179 180 #define DMA_SRC_ADDR(x) *(volatile int*)(DMA_BASEADDR + 0x00 + x*0x100) 181 #define DMA_DEST_ADDR(x) *(volatile int*)(DMA_BASEADDR + 0x04 + x*0x100) 182 #define DMA_LEN(x) *(volatile int*)(DMA_BASEADDR + 0x08 + x*0x100) 183 #define DMA_CONFIG(x) *(volatile uint8_t*)(DMA_BASEADDR + 0x0c + x*0x100) 184 #define DMA_START(x) *(volatile uint8_t*)(DMA_BASEADDR + 0x0f + x*0x100) 185 #define DMA_STATUS(x) *(volatile int*)(DMA_BASEADDR + 0x10 + x*0x100) 186 #define DMA_RPTR(x) *(volatile int*)(DMA_BASEADDR + 0x14 + x*0x100) 187 #define DMA_WPTR(x) *(volatile int*)(DMA_BASEADDR + 0x18 + x*0x100) 188 189 #define QSPI_CTRL *(volatile int*)(QSPI_BASEADDR + 0x1c) 190 #define QAES_ADDRKEY *(volatile int*)(QSPI_BASEADDR + 0x20) 191 #define QAES_CTRL *(volatile int*)(QSPI_BASEADDR + 0x24) 192 #define QAES_RAND(x) *(volatile int*)(QSPI_BASEADDR + 0x28 + x*4) 193 #define QAES_KEY(x) *(volatile int*)(QSPI_BASEADDR + 0x30 + x*4) 194 #define QAES_DATA(x) *(volatile int*)(QSPI_BASEADDR + 0x40 + x*4) 195 #define QAES_KEYB(x) *(volatile byte*)(QSPI_BASEADDR + 0x30 + x) 196 #define SPID0_CTRL *(volatile int*)0xf891c 197 #define SPID1_CTRL *(volatile int*)0xf8a1c 198 #define UART0_CTRL *(volatile int*)0xf8b1c 199 #define UART0_INTR *(volatile int*)0xf8b20 200 #define UART0_RDATA *(volatile byte*)0xf8b24 201 #define UART0_STATUS *(volatile int*)0xf8b28 202 #define UART1_CTRL *(volatile int*)0xf8c1c 203 #define UART1_INTR *(volatile int*)0xf8c20 204 #define UART1_RDATA *(volatile byte*)0xf8c24 205 #define UART1_STATUS *(volatile int*)0xf8c28 206 #define IICD_DELAY *(volatile int*)0xf8d1c 207 #define IICD_CTRL *(volatile int*)0xf8d20 208 209 #define USB_CONFIG *(volatile byte*)USB_BASEADDR 210 #define USB_INT_MASK(x) *(volatile byte*)(USB_BASEADDR + 1 + x) 211 #define USB_ADDR *(volatile byte*)(USB_BASEADDR + 4) 212 #define USB_TRG *(volatile byte*)(USB_BASEADDR + 0x10) 213 #define USB_STALL *(volatile byte*)(USB_BASEADDR + 0x11) 214 #define USB_CLEAR *(volatile byte*)(USB_BASEADDR + 0x12) 215 #define USB_EP(x) *(volatile byte*)(USB_BASEADDR + 0x18 + x) 216 #define USB_EP_LEN(x) *(volatile byte*)(USB_BASEADDR + 0x20 + x) 217 #define USB_STATUS *(volatile byte*)(USB_BASEADDR + 0x26) 218 #define USB_FIFO_EMPTY *(volatile byte*)(USB_BASEADDR + 0x27) 219 #define USB_FIFO_FULL *(volatile byte*)(USB_BASEADDR + 0x28) 220 221 222 #define AES_CNTRL_REG *((volatile uint32_t *)(AES_BASEADDR)) 223 #define AES_DATA_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x10)) 224 #define AES_DATA_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x14)) 225 #define AES_DATA_REG2 ((volatile uint32_t *)(AES_BASEADDR+0x18)) 226 #define AES_DATA_REG3 ((volatile uint32_t *)(AES_BASEADDR+0x1C)) 227 #define AES_KEY_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x20)) 228 #define AES_KEY_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x24)) 229 #define AES_KEY_REG2 ((volatile uint32_t *)(AES_BASEADDR+0x28)) 230 #define AES_KEY_REG3 ((volatile uint32_t *)(AES_BASEADDR+0x2C)) 231 #define AES_KEY_REG4 ((volatile uint32_t *)(AES_BASEADDR+0x30)) 232 #define AES_KEY_REG5 ((volatile uint32_t *)(AES_BASEADDR+0x34)) 233 #define AES_KEY_REG6 ((volatile uint32_t *)(AES_BASEADDR+0x38)) 234 #define AES_KEY_REG7 ((volatile uint32_t *)(AES_BASEADDR+0x3C)) 235 #define AES_RAND_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x40)) 236 #define AES_RAND_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x44)) 237 #define AES_FKEY_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x50)) 238 239 #define AES_DATAB(x) *(volatile byte*)(AES_BASEADDR + 0x10 + (x)) 240 #define AES_KEYB(x) *(volatile byte*)(AES_BASEADDR + 0x20 + (x)) 241 242 #define DESCNTRL_REG *((volatile uint32_t *)(DES_BASEADDR+0x00)) 243 #define DESRAND_REG ((volatile uint32_t *)(DES_BASEADDR+0x0c)) 244 #define DESFAKE_KEY ((volatile uint32_t *)(DES_BASEADDR+0x10)) 245 #define DESIV_REG ((volatile uint32_t *)(DES_BASEADDR+0x18)) 246 #define DESDATA_REG ((volatile uint32_t *)(DES_BASEADDR+0x20)) 247 #define DESKEY1_REG ((volatile uint32_t *)(DES_BASEADDR+0x28)) 248 #define DESKEY2_REG ((volatile uint32_t *)(DES_BASEADDR+0x30)) 249 #define DESKEY3_REG ((volatile uint32_t *)(DES_BASEADDR+0x38)) 250 #define DES_KEYB(x) *(volatile byte *)(DES_BASEADDR+0x28 + x) 251 #define DES_DATAB(x) *(volatile byte *)(DES_BASEADDR+0x20 + x) 252 253 #define SM4_REG0 (*(volatile uint32_t *)(SM4_BASEADDR + 0x0)) 254 #define SM4_REG1 (*(volatile uint32_t *)(SM4_BASEADDR + 0x4)) 255 #define SM4_IER (*(volatile uint32_t *)(SM4_BASEADDR + 0x8)) 256 #define SM4_MR (*(volatile uint32_t *)(SM4_BASEADDR + 0xc)) 257 #define SM4_KEY0 ((volatile uint32_t *)(SM4_BASEADDR + 0x10)) 258 #define SM4_KEY1 ((volatile uint32_t *)(SM4_BASEADDR + 0x14)) 259 #define SM4_KEY2 ((volatile uint32_t *)(SM4_BASEADDR + 0x18)) 260 #define SM4_KEY3 ((volatile uint32_t *)(SM4_BASEADDR + 0x1c)) 261 #define SM4_IV0 ((volatile uint32_t *)(SM4_BASEADDR + 0x20)) 262 #define SM4_IV1 ((volatile uint32_t *)(SM4_BASEADDR + 0x24)) 263 #define SM4_IV2 ((volatile uint32_t *)(SM4_BASEADDR + 0x28)) 264 #define SM4_IV3 ((volatile uint32_t *)(SM4_BASEADDR + 0x2c)) 265 #define SM4_DATA0 ((volatile uint32_t *)(SM4_BASEADDR + 0x30)) 266 #define SM4_DATA1 ((volatile uint32_t *)(SM4_BASEADDR + 0x34)) 267 #define SM4_DATA2 ((volatile uint32_t *)(SM4_BASEADDR + 0x38)) 268 #define SM4_DATA3 ((volatile uint32_t *)(SM4_BASEADDR + 0x3c)) 269 270 271 #define RECR (*((volatile uint32_t *)(RSA_BASEADDR+0x00))) 272 #define RESR (*((volatile uint32_t *)(RSA_BASEADDR+0x04))) 273 #define REFR (*((volatile uint32_t *)(RSA_BASEADDR+0x08))) 274 #define RESCR (*((volatile uint32_t *)(RSA_BASEADDR+0x0c))) 275 #define REDQR (*((volatile uint32_t *)(RSA_BASEADDR+0x10))) 276 #define REINT (*((volatile uint32_t *)(RSA_BASEADDR+0x14))) 277 #define RECFR (*((volatile uint32_t *)(RSA_BASEADDR+0x18))) 278 #define REBKR ((volatile uint32_t *)(RSA_BASEADDR+0x1c)) 279 #define REDRR (*((volatile uint32_t *)(RSA_BASEADDR+0x24))) 280 #define REDAR ((volatile uint32_t *)(RSA_BASEADDR+0x100)) 281 #define REDAR1 ((volatile uint32_t *)(RSA_BASEADDR+0x120)) 282 #define REDAR2 ((volatile uint32_t *)(RSA_BASEADDR+0x140)) 283 #define REDAR3 ((volatile uint32_t *)(RSA_BASEADDR+0x160)) 284 #define REDXR ((volatile uint32_t *)(RSA_BASEADDR+0x200)) 285 #define REDXR1 ((volatile uint32_t *)(RSA_BASEADDR+0x220)) 286 #define REDXR2 ((volatile uint32_t *)(RSA_BASEADDR+0x240)) 287 #define REDXR3 ((volatile uint32_t *)(RSA_BASEADDR+0x260)) 288 #define REDYR ((volatile uint32_t *)(RSA_BASEADDR+0x280)) 289 #define REDYR1 ((volatile uint32_t *)(RSA_BASEADDR+0x2a0)) 290 #define REDYR2 ((volatile uint32_t *)(RSA_BASEADDR+0x2c0)) 291 #define REDYR3 ((volatile uint32_t *)(RSA_BASEADDR+0x2e0)) 292 #define REDBR ((volatile uint32_t *)(RSA_BASEADDR+0x300)) 293 #define REDBR1 ((volatile uint32_t *)(RSA_BASEADDR+0x320)) 294 #define REDBR2 ((volatile uint32_t *)(RSA_BASEADDR+0x340)) 295 #define REDBR3 ((volatile uint32_t *)(RSA_BASEADDR+0x360)) 296 #define REDBRH ((volatile uint32_t *)(RSA_BASEADDR+0x380)) 297 #define REDCR ((volatile uint32_t *)(RSA_BASEADDR+0x500)) 298 #define REDCR1 ((volatile uint32_t *)(RSA_BASEADDR+0x520)) 299 #define REDCR2 ((volatile uint32_t *)(RSA_BASEADDR+0x540)) 300 #define REDCR3 ((volatile uint32_t *)(RSA_BASEADDR+0x560)) 301 #define REDCRH ((volatile uint32_t *)(RSA_BASEADDR+0x580)) 302 #define REDUR ((volatile uint32_t *)(RSA_BASEADDR+0x600)) 303 #define REDVR ((volatile uint32_t *)(RSA_BASEADDR+0x680)) 304 #define REDVR2 ((volatile uint32_t *)(RSA_BASEADDR+0x6c0)) 305 #define REDPR ((volatile uint32_t *)(RSA_BASEADDR+0x700)) 306 #define REDPR1 ((volatile uint32_t *)(RSA_BASEADDR+0x720)) 307 #define REDPR2 ((volatile uint32_t *)(RSA_BASEADDR+0x740)) 308 #define REDPR3 ((volatile uint32_t *)(RSA_BASEADDR+0x760)) 309 #define REDPRH ((volatile uint32_t *)(RSA_BASEADDR+0x780)) 310 311 #define ISO7811_BASE_ADDR_T1 *((volatile uint32_t *)(ISO7811_BASEADDR+0x00)) 312 #define ISO7811_BASE_ADDR_T2 *((volatile uint32_t *)(ISO7811_BASEADDR+0x04)) 313 #define ISO7811_BASE_ADDR_T3 *((volatile uint32_t *)(ISO7811_BASEADDR+0x08)) 314 #define ISO7811_CTRL *((volatile uint32_t *)(ISO7811_BASEADDR+0x0C)) 315 316 #define ISO7811_T1_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x10)) 317 #define ISO7811_T1_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x14)) 318 #define ISO7811_T1_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x18)) 319 #define ISO7811_T1_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x1c)) 320 321 #define ISO7811_T2_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x20)) 322 #define ISO7811_T2_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x24)) 323 #define ISO7811_T2_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x28)) 324 #define ISO7811_T2_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x2c)) 325 326 #define ISO7811_T3_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x30)) 327 #define ISO7811_T3_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x34)) 328 #define ISO7811_T3_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x38)) 329 #define ISO7811_T3_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x3c)) 330 331 #define ISO7811_STATUS *((volatile uint32_t *)(ISO7811_BASEADDR+0x40)) 332 #define ISO7811_CHAR_NUM *((volatile uint32_t *)(ISO7811_BASEADDR+0x44)) 333 #define ISO7811_INTERFER_CHAR_NUM *((volatile uint32_t *)(ISO7811_BASEADDR+0x48)) 334 #define ISO7811_DC_EST *((volatile uint32_t *)(ISO7811_BASEADDR+0x4c)) 335 #define ISO7811_INTF_PEAK *((volatile uint32_t *)(ISO7811_BASEADDR+0x50)) 336 #define ISO7811_AGC_PEAK_VAL *((volatile uint32_t *)(ISO7811_BASEADDR +0x54)) 337 338 #define SYST_CSR *(volatile int*)0xE000E010 339 #define SYST_RVR *(volatile int*)0xE000E014 340 #define SYST_CVR *(volatile int*)0xE000E018 341 342 #define TRACE_FIFO *(volatile int*)0xe0002020 343 #define NVIC_ISER *(volatile int*)0xe000e100 344 #define NVIC_ICER *(volatile int*)0xe000e180 345 #define NVIC_ISPR *(volatile int*)0xe000e200 346 #define NVIC_ICPR *(volatile int*)0xe000e280 347 348 #define CRC_RESULT_REG *(volatile uint32_t *)(CRC_BASEADDR+0X04) 349 #define CRC_MASK_REG *(volatile uint32_t *)(CRC_BASEADDR+0X08) 350 #define CRC_DATAB_REG *(volatile byte *)(CRC_BASEADDR+0X80) 351 #define CRC_DATAS_REG *(volatile short int *)(CRC_BASEADDR+0X80) 352 #define CRC_DATA_REG *(volatile int *)(CRC_BASEADDR+0X80) 353 354 #define ADC_CTRL0 *(volatile uint8_t*)0xC8970 355 #define ADC_CTRL1 *(volatile uint8_t*)0xC8971 356 #define ADC_CTRL2 *(volatile uint8_t*)0xC8972 357 #define ADC_CTRL3 *(volatile uint8_t*)0xC8973 358 #define ADC_ENBLE *(volatile uint8_t*)0xC8906 359 #define ADC_RDATA *(volatile uint16_t*)0xf850e 360 361 /* SysTick registers */ 362 /* SysTick control & status */ 363 #define SYSTICK_CSR ((volatile unsigned int *)0xE000E010) 364 /* SysTick Reload value */ 365 #define SYSTICK_RVR ((volatile unsigned int *)0xE000E014) 366 /* SysTick Current value */ 367 #define SYSTICK_CVR ((volatile unsigned int *)0xE000E018) 368 /* SysTick CSR register bits */ 369 #define SYSTICK_CSR_COUNTFLAG 16 370 #define SYSTICK_CSR_CLKSOURCE 2 371 #define SYSTICK_CSR_TICKINT 1 372 #define SYSTICK_CSR_ENABLE 0 373 374 //================ bit definitions ==================== 375 #define OTBIT_DIN 1<<0 376 #define OTBIT_DLE 1<<1 377 #define OTBIT_CEB 1<<2 378 #define OTBIT_RSTB 1<<3 379 #define OTBIT_CLE 1<<4 380 #define OTBIT_PGMEN 1<<5 381 #define OTBIT_PGMVFY 1<<6 382 #define OTBIT_READEN 1<<7 383 #define OTBIT_VPPEN 1<<8 384 #define OTBIT_WEB 1<<9 385 386 #define AES_CNTRL_REG_START 0x1 387 388 #define AES_CNTRL_KEY_SEL_128 0X00 389 #define AES_CNTRL_KEY_SEL_192 0X08 390 #define AES_CNTRL_KEY_SEL_256 0X10 391 392 #define AES_CNTRL_ENC 0X00 393 #define AES_CNTRL_DEC 0X02 394 395 #define AES_CNTRL_ENABLE_RAND 0X20 396 397 #define DMACH_QSPI 0 398 #define DMACH_SPID0 1 399 #define DMACH_SPID1 2 400 #define DMACH_UART0 3 401 #define DMACH_UART1 4 402 #define DMACH_IICD 5 403 #define DMACH_MEMCP 6 404 405 #define DMA_START_BIT 7 406 #define DMA_CLR_INTR_BIT 6 407 #define DMA_RESET_BIT 5 408 409 //==DES== 410 #define DESCNTRL_REG_START 0x1 411 #define DESCNTRL_REG_ENCRYPT 0x2 412 #define DESCNTRL_REG_KEY_SEL 0xc 413 #define DESCNTRL_REG_DES_MODE 0x10 414 #define DESCNTRL_REG_OP_MODE 0x60 415 #define DESCNTRL_REG_RAND_EN 0x80 416 417 #define DESCNTRL_REG_ENCRYPT_ENC 0X00 418 #define DESCNTRL_REG_ENCRYPT_DEC 0X02 419 420 #define DESCNTRL_REG_KEY_SEL_DES1 0x00 421 #define DESCNTRL_REG_KEY_SEL_DES2 0x04 422 #define DESCNTRL_REG_KEY_SEL_DES3 0x08 423 424 #define DESCNTRL_REG_KEY_SEL_TDES2 0x00 425 #define DESCNTRL_REG_KEY_SEL_TDES3 0x04 426 427 #define DESCNTRL_REG_DES_MODE_DES 0X00 428 #define DESCNTRL_REG_DES_MODE_TDES 0X10 429 430 #define DESCNTRL_REG_OP_MODE_ECB 0x00 431 #define DESCNTRL_REG_OP_MODE_CBC 0x20 432 //==DES==END== 433 434 //==RSA== 435 //sfr bit 436 // RECR register 437 #define RECR_start 0x01 438 #define RECR_idle_run 0x02 439 #define RECR_bus_crypt_en 0x04 440 // RESR register 441 #define RESR_error_flag 0x01 442 #define RESR_opdata_error 0x02 443 //REINT register 444 #define REINT_rsa_int 0x01 445 //==RSA==END== 446 447 #define CLKCLS_INT 1 448 #define CLKCLS_SHA 2 449 #define CLKCLS_CRC 3 450 #define CLKCLS_TIM 4 451 #define CLKCLS_WDT 5 452 #define CLKCLS_USB 6 453 #define CLKCLS_SPI 7 454 #define CLKCLS_DES 8 455 #define CLKCLS_RSA 9 456 #define CLKCLS_AES 10 457 #define CLKCLS_GPIO 11 458 #define CLKCLS_7816 12 459 #define CLKCLS_BT 13 460 #define CLKCLS_SM4 14 461 #define CLKCLS_UART 15 462 #define CLKCLS_7811 16 463 #define CLKCLS_ADC7811 17 464 #define CLKCLS_CP 18 465 466 #define INTR_USB 0 467 #define INTR_IIC 1 468 #define INTR_QSPI 2 469 #define INTR_SPI0 3 470 #define INTR_SPI1 4 471 #define INTR_UART0 5 472 #define INTR_UART1 6 473 #define INTR_MEMCP 7 474 #define INTR_RSA 8 475 #define INTR_SCI0 9 476 #define INTR_SCI1 10 477 #define INTR_BT 11 478 #define INTR_GPIO 12 479 #define INTR_TMR0 13 480 #define INTR_TMR1 14 481 #define INTR_TMR2 15 482 #define INTR_TMR3 16 483 #define INTR_TMR4 17 484 #define INTR_TMR5 18 485 #define INTR_TMR6 19 486 #define INTR_TMR7 20 487 #define INTR_TMR8 21 488 #define INTR_SM4 22 489 #define INTR_SEC 23 490 #define INTR_ISO7811 24 491 #define INTR_TRNG 25 492 #define INTR_WDT 26 493 494 #define SCICFG_TMODE 0 495 #define SCICFG_BIT_ORDER 1 496 #define SCICFG_PAD_TYPE 2 497 #define SCICFG_ETU_SEL 3 498 #define SCICFG_RETRY 5 499 #define SCICFG_RETRY_EN 8 500 #define SCICFG_IO_EN 9 501 #define SCICFG_BGTEN 10 502 #define SCICFG_CWTEN 11 503 #define SCICFG_MCLK_SEL 12 504 #define SCICFG_MASTER 15 505 #define SCICFG_EDCEN 16 506 507 #define KCFG_COL 3 508 #define KCFG_MDDBC 8 509 #define KCFG_MUDBC 12 510 #define KCFG_UDBC 16 511 #define KCFG_CYLE 20 512 513 #define SM4_CNTRL_ECB 0X00 514 #define SM4_CNTRL_CBC 0X02 515 #define SM4_CNTRL_ENC 0X01 516 #define SM4_CNTRL_DEC 0X00 517 518 /* =============== qspi flash command =================== */ 519 #define W25X_WRITE_ENABLE 0x06 520 #define W25X_WRITE_DISABLE 0x04 521 #define W25X_READ_STATUS1 0x05 522 #define W25X_READ_STATUS2 0x35 523 #define W25X_WRITE_STATUS 0x01 524 #define W25X_READ_DATA 0x03 525 #define W25X_FASTREAD_DATA 0x0B 526 #define W25X_FASTREAD_DUAL1 0x3B 527 #define W25X_FASTREAD_DUAL2 0xBB 528 529 #define W25X_FASTREAD_QUAD1 0x6B 530 #define W25X_FASTREAD_QUAD2 0xEB 531 #define W25X_FASTREAD_QUAD3 0xE7 532 533 #define W25X_PAGE_PROGRAM 0x02 534 #define W25X_SECTOR_ERASE 0x20 535 #define W25X_BLOCK_ERASE32K 0x52 536 #define W25X_BLOCK_ERASE64K 0xD8 537 #define W25X_CHIP_ERASE 0xC7 538 #define W25X_POWER_DOWN 0xB9 539 #define W25X_RELEASE_POWERDOWN 0xAB 540 #define W25X_DEVICEID 0xAB 541 #define W25X_MANUFACT_DEVICEID 0x90 542 #define W25X_JEDEC_DEVICEID 0x9F 543 544 #define QSPICFG_XIPEN 1 << 12 545 #define QSPICFG_DECEN 1 << 13 546 #define QSPICFG_DUAL_MODE 1 << 0 547 #define QSPICFG_QUAD_MODE 2 << 0 548 #define QSPICFG_MBYTE 1 << 2 549 #define QSPICFG_MBYTE_CONT 1 << 3 550 #define QSPICFG_RETRY 3 << 24 551 552 #define QCSFT_DUMMY 8 553 #define QCSFT_CMD 16 554 555 #define QSPICFG_MODE_3B QSPICFG_DUAL_MODE | W25X_FASTREAD_DUAL1 << QCSFT_CMD | 8 << QCSFT_DUMMY 556 #define QSPICFG_MODE_6B QSPICFG_QUAD_MODE | W25X_FASTREAD_QUAD1 << QCSFT_CMD | 8 << QCSFT_DUMMY 557 #define QSPICFG_MODE_BB QSPICFG_DUAL_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_DUAL2 << QCSFT_CMD 558 #define QSPICFG_MODE_EB QSPICFG_QUAD_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_QUAD2 << QCSFT_CMD | 4 << QCSFT_DUMMY 559 #define QSPICFG_MODE_E7 QSPICFG_QUAD_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_QUAD3 << QCSFT_CMD | 2 << QCSFT_DUMMY 560 561 #define LPMCFG_BUCK_EN 1 << 25 562 #define LPMCFG_TIMER_EN 1 << 28 563 #define LPMCFG_KRST_EN 1 << 29 564 #define LPMCFG_SENSOR_DUR 1 << 30 565 566 #define LPMSEN_SENSOR_DLY 5 567 #define LPMSEN_SENSOR_LOCK 7 568 #define LPMSEN_SHIELD_IO_EN 8 569 #define LPMSEN_SHIELD_IO_TYPE 12 570 #define LPMSEN_SHIELD_IO_PU 16 571 #define LPMSEN_SHIELD_INTERVAL 24 572 #define LPMSEN_SHIELD_ENABLE 27 573 #define LPMSEN_SHIELD_PU_DLY 28 574 #define LPMSEN_SHIELD_A_DLY 30 575 #define LPMCFG_SENSOR_LOCK 31 576 577 //gpio ctrl bit define 578 #define GPCFG_INPUT 0 579 #define GPCFG_QSPI_NCS 2 580 #define GPCFG_QSPI_SCK 3 581 #define GPCFG_QSPI_IO0 4 582 #define GPCFG_QSPI_IO1 5 583 #define GPCFG_QSPI_IO2 6 584 #define GPCFG_QSPI_IO3 7 585 #define GPCFG_UART0_TXD 8 586 #define GPCFG_UART0_RXD 9 587 #define GPCFG_UART0_RTS 10 588 #define GPCFG_UART0_CTS 11 589 #define GPCFG_UART1_TXD 12 590 #define GPCFG_UART1_RXD 13 591 #define GPCFG_UART1_RTS 14 592 #define GPCFG_UART1_CTS 15 593 #define GPCFG_PWM_OUT0 16 594 #define GPCFG_PWM_OUT1 17 595 #define GPCFG_PWM_OUT2 18 596 #define GPCFG_PWM_OUT3 19 597 #define GPCFG_PWM_OUT4 20 598 #define GPCFG_PWM_OUT5 21 599 #define GPCFG_PWM_OUT6 22 600 #define GPCFG_PWM_OUT7 23 601 #define GPCFG_SPID0_NCS 24 602 #define GPCFG_SPID0_SCK 25 603 #define GPCFG_SPID0_MOSI 26 604 #define GPCFG_SPID0_SDIO 27 605 #define GPCFG_SPID0_MISO 28 606 #define GPCFG_SPID0_NCSIN 29 607 #define GPCFG_SPID0_SCKIN 30 608 #define GPCFG_PWM_OUT8 31 609 610 #define GPCFG_SPID1_NCS 48 611 #define GPCFG_SPID1_SCK 49 612 #define GPCFG_SPID1_MOSI 50 613 #define GPCFG_SPID1_SDIO 51 614 #define GPCFG_SPID1_MISO 52 615 #define GPCFG_SPID1_NCSIN 53 616 #define GPCFG_SPID1_SCKIN 54 617 #define GPCFG_NFC_CLK_OUT 55 618 #define GPCFG_SCI7816_IO 56 619 620 #define GPCFG_ICE 57 621 #define GPCFG_IIC_SCL 58 622 #define GPCFG_IIC_SDA 59 623 #define GPCFG_JTAG_SWCLK 60 624 #define GPCFG_JTAG_SWDAT 61 625 #define GPCFG_OUTPUT_LOW 62 626 #define GPCFG_OUTPUT_HIGH 63 627 #define GPCFG_PU 64 628 #define GPCFG_PD 128 629 #define GPCFG_ANALOG 192 630 631 #define TIM_CTRL_ENABLE ((uint32_t)0) 632 #define TIM_CTRL_START_LEVEL ((uint32_t)1) 633 #define TIM_CTRL_MODE ((uint32_t)2) 634 #define TIM_CTRL_AUTO_RELOAD ((uint32_t)3) 635 636 /* =============== macros =================== */ 637 #define PREFETCH_LINE(addr) *(volatile int*)addr = 0 638 #define GETWORD(p) ((uint16_t)((*(volatile uint8_t *)((uint32_t)p)) |((((uint16_t)(*(volatile uint8_t *)((uint32_t)(p+1))))<<8) & 0xff00))) enable_clock(int id)639static inline void enable_clock(int id) 640 { 641 SYSCTRL_CLK_CLS &= ~(1 << id); 642 } disable_clock(int id)643static inline void disable_clock(int id) 644 { 645 SYSCTRL_CLK_CLS |= 1 << id; 646 } enable_intr(int intid)647static inline void enable_intr(int intid) 648 { 649 NVIC_ISER |= 1 << intid; 650 } disable_intr(int intid)651static inline void disable_intr(int intid) 652 { 653 NVIC_ICER = 1 << intid; 654 } 655 656 extern void delay(int);//delay(x)=delay(x*110+450ns) 657 extern void invalidate_icache(int addr, int len); 658 659 //#define SCY_FALSE seesim1() 660 661 /*********************************************/ 662 #define SYSCTRL_PCLK_CON *(volatile int*)0xf7208 663 #define SYSCTRL_POWERMODE *(volatile int*)0xf7218 664 665 //#define debug 666 #endif /* __YC3121_H__ */ 667