1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef _DISP_SYS_INTF_ 12 #define _DISP_SYS_INTF_ 13 14 #include "de/include.h" 15 #include <sunxi_hal_regulator.h> 16 17 #ifdef CONFIG_PLAN_SPRITE 18 #define RTTHREAD_KERNEL 1 19 #else 20 #define RTTHREAD_KERNEL 0 21 #endif 22 23 struct disp_gpio_set_t { 24 char gpio_name[32]; 25 u32 port; 26 u32 port_num; 27 u32 mul_sel; 28 u32 pull; 29 u32 drv_level; 30 u32 data; 31 u32 gpio; 32 }; 33 34 struct disp_pwm_dev { 35 u32 pwm_channel_id; 36 struct pwm_config cfg; 37 bool enable; 38 }; 39 40 /** 41 * disp_power_t 42 */ 43 struct disp_power_t { 44 char power_name[32]; 45 /*see sunxi_hal_regulator.h */ 46 enum REGULATOR_TYPE_ENUM power_type; 47 enum REGULATOR_ID_ENUM power_id; 48 /*unit:uV, 1V=1000000uV */ 49 u32 power_vol; 50 bool always_on; 51 }; 52 53 #define DISP_PIN_STATE_ACTIVE "active" 54 #define DISP_PIN_STATE_SLEEP "sleep" 55 56 #define DISP_BYTE_ALIGN(x) (((x + (4*1024-1)) >> 12) << 12) 57 58 void disp_sys_cache_flush(void *address, u32 length, u32 flags); 59 60 int disp_sys_register_irq(u32 IrqNo, u32 Flags, void *Handler, void *pArg, 61 u32 DataSize, u32 Prio); 62 void disp_sys_unregister_irq(u32 IrqNo, void *Handler, void *pArg); 63 void disp_sys_disable_irq(u32 IrqNo); 64 void disp_sys_enable_irq(u32 IrqNo); 65 66 /* returns: 0:invalid, 1: int; 2:str, 3: gpio */ 67 s32 disp_sys_script_get_item(char *main_name, char *sub_name, s32 value[], 68 s32 type); 69 70 int disp_sys_get_ic_ver(void); 71 72 int disp_sys_gpio_request(struct disp_gpio_set_t *gpio_list, 73 u32 group_count_max); 74 int disp_sys_gpio_request_simple(struct disp_gpio_set_t *gpio_list, 75 u32 group_count_max); 76 int disp_sys_gpio_release(int p_handler, s32 if_release_to_default_status); 77 78 /* direction: 0:input, 1:output */ 79 int disp_sys_gpio_set_direction(u32 p_handler, u32 direction, 80 const char *gpio_name); 81 int disp_sys_gpio_get_value(u32 p_handler, const char *gpio_name); 82 int disp_sys_gpio_set_value(u32 p_handler, u32 value_to_gpio, 83 const char *gpio_name); 84 int disp_sys_pin_set_state(char *dev_name, char *name); 85 86 s32 disp_sys_power_enable(void *p_power); 87 s32 disp_sys_power_disable(void *p_power); 88 void *disp_sys_malloc(u32 size); 89 90 uintptr_t disp_sys_pwm_request(u32 pwm_id); 91 int disp_sys_pwm_free(uintptr_t p_handler); 92 int disp_sys_pwm_enable(uintptr_t p_handler); 93 int disp_sys_pwm_disable(uintptr_t p_handler); 94 int disp_sys_pwm_config(uintptr_t p_handler, int duty_ns, int period_ns); 95 int disp_sys_pwm_set_polarity(uintptr_t p_handler, int polarity); 96 s32 disp_delay_us(u32 us); 97 s32 disp_delay_ms(u32 ms); 98 u32 disp_getprop_regbase(char *main_name, u32 index); 99 u32 disp_getprop_irq(char *main_name, u32 index); 100 u32 disp_getprop_clk(char *main_name); 101 struct reset_control *disp_get_rst_by_name(char *main_name); 102 void disp_sys_free(void *ptr); 103 int disp_sys_mutex_init(hal_sem_t *lock); 104 int disp_sys_mutex_unlock(hal_sem_t *sem); 105 int disp_sys_mutex_lock(hal_sem_t *sem); 106 void *disp_dma_malloc(u32 num_bytes, void *phys_addr); 107 void disp_dma_free(void *virt_addr, void *phys_addr, u32 num_bytes); 108 s32 disp_sys_clk_set_rate(hal_clk_id_t p_clk, u32 rate); 109 u32 disp_sys_clk_get_rate(hal_clk_id_t p_clk); 110 s32 disp_sys_clk_set_parent(hal_clk_id_t clk, hal_clk_id_t parent); 111 hal_clk_id_t disp_sys_clk_get_parent(hal_clk_id_t clk); 112 s32 disp_sys_clk_enable(hal_clk_id_t clk); 113 s32 disp_sys_clk_disable(hal_clk_id_t clk); 114 bool disp_clock_is_enabled(hal_clk_id_t clk); 115 116 #endif 117