1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * 1. Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * 2. Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 12 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 15 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 16 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 17 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 /* 27 * Copyright (c) 2006-2025, RT-Thread Development Team 28 * 29 * SPDX-License-Identifier: Apache-2.0 30 */ 31 32 #ifndef DRV_TIMER_H__ 33 #define DRV_TIMER_H__ 34 #include <stdint.h> 35 #include <drivers/hwtimer.h> 36 #include "sysctl_clk.h" 37 #include "board.h" 38 39 #define MHz 1000000 40 /* TIMER Control Register */ 41 #define TIMER_CR_ENABLE 0x00000001 42 #define TIMER_CR_MODE_MASK 0x00000002 43 #define TIMER_CR_FREE_MODE 0x00000000 44 #define TIMER_CR_USER_MODE 0x00000002 45 #define TIMER_CR_INTERRUPT_MASK 0x00000004 46 #define TIMER_CR_PWM_ENABLE 0x00000008 47 48 #define IRQN_TIMER_0_INTERRUPT K230_IRQ_TIMER0 49 #define IRQN_TIMER_1_INTERRUPT K230_IRQ_TIMER1 50 #define IRQN_TIMER_2_INTERRUPT K230_IRQ_TIMER2 51 #define IRQN_TIMER_3_INTERRUPT K230_IRQ_TIMER3 52 #define IRQN_TIMER_4_INTERRUPT K230_IRQ_TIMER4 53 #define IRQN_TIMER_5_INTERRUPT K230_IRQ_TIMER5 54 55 typedef struct _timer_regs_channel 56 { 57 /* TIMER_N Load Count Register (0x00+(N-1)*0x14) */ 58 volatile uint32_t load_count; 59 /* TIMER_N Current Value Register (0x04+(N-1)*0x14) */ 60 volatile uint32_t current_value; 61 /* TIMER_N Control Register (0x08+(N-1)*0x14) */ 62 volatile uint32_t control; 63 /* TIMER_N Interrupt Clear Register (0x0c+(N-1)*0x14) */ 64 volatile uint32_t eoi; 65 /* TIMER_N Interrupt Status Register (0x10+(N-1)*0x14) */ 66 volatile uint32_t intr_stat; 67 } __attribute__((packed, aligned(4))) k230_timer_regs_channel_t; 68 69 typedef struct _k230_timer_regs 70 { 71 /* TIMER_N Register (0x00-0x4c) */ 72 volatile k230_timer_regs_channel_t channel[5]; 73 /* reserverd (0x50-0x9c) */ 74 volatile uint32_t resv1[20]; 75 /* TIMER Interrupt Status Register (0xa0) */ 76 volatile uint32_t intr_stat; 77 /* TIMER Interrupt Clear Register (0xa4) */ 78 volatile uint32_t eoi; 79 /* TIMER Raw Interrupt Status Register (0xa8) */ 80 volatile uint32_t raw_intr_stat; 81 /* TIMER Component Version Register (0xac) */ 82 volatile uint32_t comp_version; 83 /* TIMER_N Load Count2 Register (0xb0-0xbc) */ 84 volatile uint32_t load_count2[4]; 85 } __attribute__((packed, aligned(4))) k230_timer_regs_t; 86 87 struct k230_timer { 88 struct rt_hwtimer_device device; 89 const char *name; 90 rt_ubase_t base; 91 uint32_t id; 92 sysctl_clk_node_e clk; 93 sysctl_clk_node_e clk_src; 94 int irq_num; 95 }; 96 97 #endif