1 /*!
2 * @file apm32e10x_rcm.c
3 *
4 * @brief This file provides all the RCM firmware functions
5 *
6 * @version V1.0.2
7 *
8 * @date 2022-12-31
9 *
10 * @attention
11 *
12 * Copyright (C) 2021-2023 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be useful and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 #include "apm32e10x_rcm.h"
27
28 /** @addtogroup APM32E10x_StdPeriphDriver
29 @{
30 */
31
32 /** @addtogroup RCM_Driver
33 * @brief RCM driver modules
34 @{
35 */
36
37 /** @defgroup RCM_Functions Functions
38 @{
39 */
40
41 /*!
42 * @brief Resets the clock configuration to the default state
43 *
44 * @param None
45 *
46 * @retval None
47 */
RCM_Reset(void)48 void RCM_Reset(void)
49 {
50 /* Open HSI clock */
51 RCM->CTRL_B.HSIEN = BIT_SET;
52 /* Config HSI to system clock and Reset AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
53 RCM->CFG &= (uint32_t)0xF8FF0000;
54 /* Reset HSEEN, CSSEN and PLLEN bits */
55 RCM->CTRL &= (uint32_t)0xFEF6FFFF;
56 /* Reset HSEBCFG bit */
57 RCM->CTRL_B.HSEBCFG = BIT_RESET;
58 /* Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
59 RCM->CFG &= (uint32_t)0xFF00FFFF;
60 /* Disable all interrupts and clear pending bits */
61 RCM->INT = 0x009F0000;
62 }
63
64 /*!
65 * @brief Configs the HSE oscillator
66 *
67 * @param state: state of the HSE
68 * This parameter can be one of the following values:
69 * @arg RCM_HSE_CLOSE: Turn off the HSE oscillator
70 * @arg RCM_HSE_OPEN: Turn on the HSE oscillator
71 * @arg RCM_HSE_BYPASS: HSE oscillator bypassed with external clock
72 *
73 * @retval None
74 *
75 * @note When HSE is not used directly or through the PLL as system clock, it can be stopped.
76 */
RCM_ConfigHSE(RCM_HSE_T state)77 void RCM_ConfigHSE(RCM_HSE_T state)
78 {
79 /* Reset HSEEN bit */
80 RCM->CTRL_B.HSEEN = BIT_RESET;
81
82 /* Reset HSEBCFG bit */
83 RCM->CTRL_B.HSEBCFG = BIT_RESET;
84
85 if (state == RCM_HSE_OPEN)
86 {
87 RCM->CTRL_B.HSEEN = BIT_SET;
88 }
89 else if (state == RCM_HSE_BYPASS)
90 {
91 RCM->CTRL_B.HSEBCFG = BIT_SET;
92 RCM->CTRL_B.HSEEN = BIT_SET;
93 }
94 }
95
96 /*!
97 * @brief Waits for HSE to be ready
98 *
99 * @param None
100 *
101 * @retval SUCCESS: HSE oscillator is ready
102 * ERROR : HSE oscillator is not ready
103 */
RCM_WaitHSEReady(void)104 uint8_t RCM_WaitHSEReady(void)
105 {
106 __IO uint32_t cnt;
107
108 for (cnt = 0; cnt < HSE_STARTUP_TIMEOUT; cnt++)
109 {
110 if (RCM->CTRL_B.HSERDYFLG == BIT_SET)
111 {
112 return SUCCESS;
113 }
114 }
115
116 return ERROR;
117 }
118
119 /*!
120 * @brief Config HSI trimming value
121 *
122 * @param HSITrim: HSI trimming value
123 * This parameter must be a number between 0 and 0x1F.
124 *
125 * @retval None
126 */
RCM_ConfigHSITrim(uint8_t HSITrim)127 void RCM_ConfigHSITrim(uint8_t HSITrim)
128 {
129 RCM->CTRL_B.HSITRIM = HSITrim;
130 }
131
132 /*!
133 * @brief Enable the HSI
134 *
135 * @param None
136 *
137 * @retval None
138 */
RCM_EnableHSI(void)139 void RCM_EnableHSI(void)
140 {
141 RCM->CTRL_B.HSIEN = BIT_SET;
142 }
143
144 /*!
145 * @brief Disable the HSI
146 *
147 * @param None
148 *
149 * @retval None
150 *
151 * @note When HSI is not used directly or through the PLL as system clock, it can be stopped.
152 */
153
RCM_DisableHSI(void)154 void RCM_DisableHSI(void)
155 {
156 RCM->CTRL_B.HSIEN = BIT_RESET;
157 }
158
159 /*!
160 * @brief Configures the External Low Speed oscillator (LSE)
161 *
162 * @param state : Specifies the new state of the LSE
163 * This parameter can be one of the following values:
164 * @arg RCM_LSE_CLOSE : Close the LSE
165 * @arg RCM_LSE_OPEN : Open the LSE
166 * @arg RCM_LSE_BYPASS : LSE bypass
167 *
168 * @retval None
169 *
170 * @note
171 */
RCM_ConfigLSE(RCM_LSE_T state)172 void RCM_ConfigLSE(RCM_LSE_T state)
173 {
174 RCM->BDCTRL_B.LSEEN = BIT_RESET;
175 RCM->BDCTRL_B.LSEBCFG = BIT_RESET;
176
177 if (state == RCM_LSE_OPEN)
178 {
179 RCM->BDCTRL_B.LSEEN = BIT_SET;
180 }
181 else if (state == RCM_LSE_BYPASS)
182 {
183 RCM->BDCTRL_B.LSEBCFG = BIT_SET;
184 RCM->BDCTRL_B.LSEEN = BIT_SET;
185 }
186 }
187
188 /*!
189 * @brief Enables the Internal Low Speed oscillator (LSI)
190 *
191 * @param None
192 *
193 * @retval None
194 *
195 * @note
196 */
RCM_EnableLSI(void)197 void RCM_EnableLSI(void)
198 {
199 RCM->CSTS_B.LSIEN = BIT_SET;
200 }
201
202 /*!
203 * @brief Disables the Internal Low Speed oscillator (LSI)
204 *
205 * @param None
206 *
207 * @retval None
208 *
209 * @note
210 */
RCM_DisableLSI(void)211 void RCM_DisableLSI(void)
212 {
213 RCM->CSTS_B.LSIEN = BIT_RESET;
214 }
215
216 /*!
217 * @brief Configs the PLL clock source and multiplication factor
218 *
219 * @param pllSelect: PLL entry clock source select
220 * This parameter can be one of the following values:
221 * @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source
222 * @arg RCM_PLLSEL_HSE: HSE clock selected as PLL clock source
223 * @arg RCM_PLLSEL_HSE_DIV2: HSE clock divided by 2 selected as PLL clock source
224 *
225 * @param pllMf: PLL multiplication factor
226 * This parameter can be RCM_PLLMF_x where x can be a value from 2 to 16.
227 *
228 * @retval None
229 *
230 * @note PLL should be disabled while use this function.
231 */
RCM_ConfigPLL(RCM_PLLSEL_T pllSelect,RCM_PLLMF_T pllMf)232 void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf)
233 {
234 RCM->CFG_B.PLLMULCFG = pllMf;
235 RCM->CFG_B.PLLSRCSEL = pllSelect & 0x01;
236 RCM->CFG_B.PLLHSEPSC = (pllSelect >> 1) & 0x01;
237 }
238
239 /*!
240 * @brief Enables the PLL
241 *
242 * @param None
243 *
244 * @retval None
245 */
RCM_EnablePLL(void)246 void RCM_EnablePLL(void)
247 {
248 RCM->CTRL_B.PLLEN = BIT_SET;
249 }
250
251 /*!
252 * @brief Disable the PLL
253 *
254 * @param None
255 *
256 * @retval None
257 *
258 * @note When PLL is not used as system clock, it can be stopped.
259 */
RCM_DisablePLL(void)260 void RCM_DisablePLL(void)
261 {
262 RCM->CTRL_B.PLLEN = BIT_RESET;
263 }
264
265 /*!
266 * @brief Enable the Clock Security System
267 *
268 * @param None
269 *
270 * @retval None
271 */
RCM_EnableCSS(void)272 void RCM_EnableCSS(void)
273 {
274 RCM->CTRL_B.CSSEN = BIT_SET;
275 }
276
277 /*!
278 * @brief Disable the Clock Security System
279 *
280 * @param None
281 *
282 * @retval None
283 */
RCM_DisableCSS(void)284 void RCM_DisableCSS(void)
285 {
286 RCM->CTRL_B.CSSEN = BIT_RESET;
287 }
288
289 /*!
290 * @brief Selects the MCO pin clock ouput source
291 *
292 * @param mcoClock: specifies the clock source to output
293 * This parameter can be one of the following values:
294 * @arg RCM_MCOCLK_NO_CLOCK : No clock selected.
295 * @arg RCM_MCOCLK_SYSCLK : System clock selected.
296 * @arg RCM_MCOCLK_HSI : HSI oscillator clock selected.
297 * @arg RCM_MCOCLK_HSE : HSE oscillator clock selected.
298 * @arg RCM_MCOCLK_PLLCLK_DIV_2 : PLL clock divided by 2 selected.
299 *
300 * @retval None
301 *
302 * @note
303 */
RCM_ConfigMCO(RCM_MCOCLK_T mcoClock)304 void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock)
305 {
306 RCM->CFG_B.MCOSEL = mcoClock;
307 }
308
309 /*!
310 * @brief Configures the system clock source
311 *
312 * @param sysClkSelect: specifies the clock source used as system clock
313 * This parameter can be one of the following values:
314 * @arg RCM_SYSCLK_SEL_HSI: HSI is selected as system clock source
315 * @arg RCM_SYSCLK_SEL_HSE: HSE is selected as system clock source
316 * @arg RCM_SYSCLK_SEL_PLL: PLL is selected as system clock source
317 *
318 * @retva None
319 */
RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect)320 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect)
321 {
322 RCM->CFG_B.SCLKSW = sysClkSelect;
323 }
324
325 /*!
326 * @brief Returns the clock source which is used as system clock
327 *
328 * @param None
329 *
330 * @retval The clock source used as system clock
331 */
RCM_ReadSYSCLKSource(void)332 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void)
333 {
334 RCM_SYSCLK_SEL_T sysClock;
335
336 sysClock = (RCM_SYSCLK_SEL_T)RCM->CFG_B.SCLKSWSTS;
337
338 return sysClock;
339 }
340
341 /*!
342 * @brief Configs the AHB clock prescaler.
343 *
344 * @param AHBDiv : Specifies the AHB clock prescaler from the system clock.
345 * This parameter can be one of the following values:
346 * @arg RCM_AHB_DIV_1 : HCLK = SYSCLK
347 * @arg RCM_AHB_DIV_2 : HCLK = SYSCLK / 2
348 * @arg RCM_AHB_DIV_4 : HCLK = SYSCLK / 4
349 * @arg RCM_AHB_DIV_8 : HCLK = SYSCLK / 8
350 * @arg RCM_AHB_DIV_16 : HCLK = SYSCLK / 16
351 * @arg RCM_AHB_DIV_64 : HCLK = SYSCLK / 64
352 * @arg RCM_AHB_DIV_128 : HCLK = SYSCLK / 128
353 * @arg RCM_AHB_DIV_256 : HCLK = SYSCLK / 256
354 * @arg RCM_AHB_DIV_512 : HCLK = SYSCLK / 512
355 *
356 * @retval None
357 *
358 * @note
359 */
RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv)360 void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv)
361 {
362 RCM->CFG_B.AHBPSC = AHBDiv;
363 }
364
365 /*!
366 * @brief Configs the APB1 clock prescaler.
367 *
368 * @param APB1Div: Specifies the APB1 clock prescaler from the AHB clock.
369 * This parameter can be one of the following values:
370 * @arg RCM_APB_DIV_1 : PCLK1 = HCLK
371 * @arg RCM_APB_DIV_2 : PCLK1 = HCLK / 2
372 * @arg RCM_APB_DIV_4 : PCLK1 = HCLK / 4
373 * @arg RCM_APB_DIV_8 : PCLK1 = HCLK / 8
374 * @arg RCM_APB_DIV_16 : PCLK1 = HCLK / 16
375 *
376 * @retval None
377 */
RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div)378 void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div)
379 {
380 RCM->CFG_B.APB1PSC = APB1Div;
381 }
382
383 /*!
384 * @brief Configs the APB2 clock prescaler
385 *
386 * @param APB2Div: Specifies the APB2 clock prescaler from the AHB clock.
387 * This parameter can be one of the following values:
388 * @arg RCM_APB_DIV_1 : PCLK2 = HCLK
389 * @arg RCM_APB_DIV_2 : PCLK2 = HCLK / 2
390 * @arg RCM_APB_DIV_4 : PCLK2 = HCLK / 4
391 * @arg RCM_APB_DIV_8 : PCLK2 = HCLK / 8
392 * @arg RCM_APB_DIV_16 : PCLK2 = HCLK / 16
393 *
394 * @retval None
395 */
RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div)396 void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div)
397 {
398 RCM->CFG_B.APB2PSC = APB2Div;
399 }
400
401 /*!
402 * @brief Configs the USB clock prescaler
403 *
404 * @param USBDiv: Specifies the USB clock prescaler from the PLL clock.
405 * This parameter can be one of the following values:
406 * @arg RCM_USB_DIV_1_5 : USBCLK = PLL clock /1.5
407 * @arg RCM_USB_DIV_1 : USBCLK = PLL clock
408 * @arg RCM_USB_DIV_2 : USBCLK = PLL clock / 2
409 * @arg RCM_USB_DIV_2_5 : USBCLK = PLL clock / 2.5
410 *
411 * @retval None
412 */
RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv)413 void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv)
414 {
415 RCM->CFG_B.USBDPSC = USBDiv;
416 }
417
418 /*!
419 * @brief Configs the FPU clock prescaler
420 *
421 * @param FPUDiv: Specifies the FPU clock prescaler from the AHB clock.
422 * This parameter can be one of the following values:
423 * @arg RCM_FPU_DIV_1 : FPUCLK = HCLK
424 * @arg RCM_FPU_DIV_2 : FPUCLK = HCLK /2
425 *
426 * @retval None
427 */
RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv)428 void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv)
429 {
430 RCM->CFG_B.FPUPSC = FPUDiv;
431 }
432
433 /*!
434 * @brief Configs the ADC clock prescaler
435 *
436 * @param ADCDiv : Specifies the ADC clock prescaler from the APB2 clock.
437 * This parameter can be one of the following values:
438 * @arg RCM_PCLK2_DIV_2: ADCCLK = PCLK2 / 2
439 * @arg RCM_PCLK2_DIV_4: ADCCLK = PCLK2 / 4
440 * @arg RCM_PCLK2_DIV_6: ADCCLK = PCLK2 / 6
441 * @arg RCM_PCLK2_DIV_8: ADCCLK = PCLK2 / 8
442 *
443 * @retval None
444 */
RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv)445 void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv)
446 {
447 RCM->CFG_B.ADCPSC = ADCDiv;
448 }
449
450 /*!
451 * @brief Configures the RTC clock source
452 *
453 * @param rtcClkSelect : specifies the RTC clock source.
454 * This parameter can be one of the following values:
455 * @arg RCM_RTCCLK_LSE : RTCCLK = LSE clock
456 * @arg RCM_RTCCLK_LSI : RTCCLK = LSI clock
457 * @arg RCM_RTCCLK_HSE_DIV_128: RTCCLK = HSE clock / 128
458 *
459 * @retval None
460 *
461 * @note Once the RTC clock is configed it can't be changed unless reset the Backup domain.
462 */
RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect)463 void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect)
464 {
465 RCM->BDCTRL_B.RTCSRCSEL = rtcClkSelect;
466 }
467
468 /*!
469 * @brief Enables the RTC clock
470 *
471 * @param None
472 *
473 * @retval None
474 */
RCM_EnableRTCCLK(void)475 void RCM_EnableRTCCLK(void)
476 {
477 RCM->BDCTRL_B.RTCCLKEN = BIT_SET;
478 }
479
480 /*!
481 * @brief Disables the RTC clock
482 *
483 * @param None
484 *
485 * @retval None
486 */
RCM_DisableRTCCLK(void)487 void RCM_DisableRTCCLK(void)
488 {
489 RCM->BDCTRL_B.RTCCLKEN = BIT_RESET;
490 }
491
492 /*!
493 * @brief Reads the frequency of SYSCLK
494 *
495 * @param None
496 *
497 * @retval Return the frequency of SYSCLK
498 */
RCM_ReadSYSCLKFreq(void)499 uint32_t RCM_ReadSYSCLKFreq(void)
500 {
501 uint32_t sysClock, pllMull, pllSource;
502
503 /** get sys clock */
504 sysClock = RCM->CFG_B.SCLKSW;
505
506 switch (sysClock)
507 {
508 /** sys clock is HSI */
509 case RCM_SYSCLK_SEL_HSI:
510 sysClock = HSI_VALUE;
511 break;
512
513 /** sys clock is HSE */
514 case RCM_SYSCLK_SEL_HSE:
515 sysClock = HSE_VALUE;
516 break;
517
518 /** sys clock is PLL */
519 case RCM_SYSCLK_SEL_PLL:
520 pllMull = RCM->CFG_B.PLLMULCFG + 2;
521 pllSource = RCM->CFG_B.PLLSRCSEL;
522
523 /** PLL entry clock source is HSE */
524 if (pllSource == BIT_SET)
525 {
526 sysClock = HSE_VALUE * pllMull;
527
528 /** HSE clock divided by 2 */
529 if (pllSource == RCM->CFG_B.PLLHSEPSC)
530 {
531 sysClock >>= 1;
532 }
533 }
534 /** PLL entry clock source is HSI/2 */
535 else
536 {
537 sysClock = (HSI_VALUE >> 1) * pllMull;
538 }
539
540 break;
541
542 default:
543 sysClock = HSI_VALUE;
544 break;
545 }
546
547 return sysClock;
548 }
549
550 /*!
551 * @brief Reads the frequency of HCLK(AHB)
552 *
553 * @param None
554 *
555 * @retval Return the frequency of HCLK
556 */
RCM_ReadHCLKFreq(void)557 uint32_t RCM_ReadHCLKFreq(void)
558 {
559 uint32_t divider;
560 uint32_t sysClk, hclk;
561 uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
562
563 sysClk = RCM_ReadSYSCLKFreq();
564 divider = AHBPrescTable[RCM->CFG_B.AHBPSC];
565 hclk = sysClk >> divider;
566
567 return hclk;
568 }
569
570 /*!
571 * @brief Reads the frequency of PCLK1 And PCLK2
572 *
573 * @param PCLK1 : Return the frequency of PCLK1
574 *
575 * @param PCLK1 : Return the frequency of PCLK2
576 *
577 * @retval None
578 */
RCM_ReadPCLKFreq(uint32_t * PCLK1,uint32_t * PCLK2)579 void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2)
580 {
581 uint32_t hclk, divider;
582 uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
583
584 hclk = RCM_ReadHCLKFreq();
585
586 if (PCLK1)
587 {
588 divider = APBPrescTable[RCM->CFG_B.APB1PSC];
589 *PCLK1 = hclk >> divider;
590 }
591
592 if (PCLK2)
593 {
594 divider = APBPrescTable[RCM->CFG_B.APB2PSC];
595 *PCLK2 = hclk >> divider;
596 }
597 }
598
599 /*!
600 * @brief Reads the frequency of ADCCLK
601 *
602 * @param None
603 *
604 * @retval Return the frequency of ADCCLK
605 */
RCM_ReadADCCLKFreq(void)606 uint32_t RCM_ReadADCCLKFreq(void)
607 {
608 uint32_t adcClk, pclk2, divider;
609 uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
610
611 RCM_ReadPCLKFreq(NULL, &pclk2);
612
613 /** Get ADC CLK */
614 divider = ADCPrescTable[RCM->CFG_B.ADCPSC];
615 adcClk = pclk2 / divider;
616
617 return adcClk;
618 }
619
620 /*!
621 * @brief Enables AHB peripheral clock.
622 *
623 * @param AHBPeriph : Enable the specifies clock of AHB peripheral.
624 * This parameter can be any combination of the following values:
625 * @arg RCM_AHB_PERIPH_DMA1 : Enable DMA1 clock
626 * @arg RCM_AHB_PERIPH_DMA2 : Enable DMA2 clock
627 * @arg RCM_AHB_PERIPH_SRAM : Enable SRAM clock
628 * @arg RCM_AHB_PERIPH_FPU : Enable FPU clock
629 * @arg RCM_AHB_PERIPH_FMC : Enable FMC clock
630 * @arg RCM_AHB_PERIPH_QSPI : Enable QSPI clock
631 * @arg RCM_AHB_PERIPH_CRC : Enable CRC clock
632 * @arg RCM_AHB_PERIPH_EMMC : Enable EMMC clock
633 * @arg RCM_AHB_PERIPH_SDIO : Enable SDIO clock
634 *
635 * @retval None
636 */
RCM_EnableAHBPeriphClock(uint32_t AHBPeriph)637 void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph)
638 {
639 RCM->AHBCLKEN |= AHBPeriph;
640 }
641
642 /*!
643 * @brief Disable AHB peripheral clock.
644 *
645 * @param AHBPeriph : Disable the specifies clock of AHB peripheral.
646 * This parameter can be any combination of the following values:
647 * @arg RCM_AHB_PERIPH_DMA1 : Disable DMA1 clock
648 * @arg RCM_AHB_PERIPH_DMA2 : Disable DMA2 clock
649 * @arg RCM_AHB_PERIPH_SRAM : Disable SRAM clock
650 * @arg RCM_AHB_PERIPH_FPU : Disable FPU clock
651 * @arg RCM_AHB_PERIPH_FMC : Disable FMC clock
652 * @arg RCM_AHB_PERIPH_QSPI : Disable QSPI clock
653 * @arg RCM_AHB_PERIPH_CRC : Disable CRC clock
654 * @arg RCM_AHB_PERIPH_EMMC : Disable EMMC clock
655 * @arg RCM_AHB_PERIPH_SDIO : Disable SDIO clock
656 *
657 * @retval None
658 */
RCM_DisableAHBPeriphClock(uint32_t AHBPeriph)659 void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph)
660 {
661 RCM->AHBCLKEN &= (uint32_t)~AHBPeriph;
662 }
663
664 /*!
665 * @brief Enable the High Speed APB (APB2) peripheral clock
666 *
667 * @param APB2Periph : Enable specifies clock of the APB2 peripheral.
668 * This parameter can be any combination of the following values:
669 * @arg RCM_APB2_PERIPH_AFIO : Enable AFIO clock
670 * @arg RCM_APB2_PERIPH_GPIOA : Enable GPIOA clock
671 * @arg RCM_APB2_PERIPH_GPIOB : Enable GPIOB clock
672 * @arg RCM_APB2_PERIPH_GPIOC : Enable GPIOC clock
673 * @arg RCM_APB2_PERIPH_GPIOD : Enable GPIOD clock
674 * @arg RCM_APB2_PERIPH_GPIOE : Enable GPIOE clock
675 * @arg RCM_APB2_PERIPH_GPIOF : Enable GPIOF clock
676 * @arg RCM_APB2_PERIPH_GPIOG : Enable GPIOG clock
677 * @arg RCM_APB2_PERIPH_ADC1 : Enable ADC1 clock
678 * @arg RCM_APB2_PERIPH_ADC2 : Enable ADC2 clock
679 * @arg RCM_APB2_PERIPH_TMR1 : Enable TMR1 clock
680 * @arg RCM_APB2_PERIPH_SPI1 : Enable SPI1 clock
681 * @arg RCM_APB2_PERIPH_TMR8 : Enable TMR8 clock
682 * @arg RCM_APB2_PERIPH_USART1 : Enable USART1 clock
683 * @arg RCM_APB2_PERIPH_ADC3 : Enable ADC3 clock
684 *
685 * @retval None
686 */
RCM_EnableAPB2PeriphClock(uint32_t APB2Periph)687 void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph)
688 {
689 RCM->APB2CLKEN |= APB2Periph;
690 }
691
692 /*!
693 * @brief Disable the High Speed APB (APB2) peripheral clock
694 *
695 * @param APB2Periph : Disable specifies clock of the APB2 peripheral.
696 * This parameter can be any combination of the following values:
697 * @arg RCM_APB2_PERIPH_AFIO : Disable AFIO clock
698 * @arg RCM_APB2_PERIPH_GPIOA : Disable GPIOA clock
699 * @arg RCM_APB2_PERIPH_GPIOB : Disable GPIOB clock
700 * @arg RCM_APB2_PERIPH_GPIOC : Disable GPIOC clock
701 * @arg RCM_APB2_PERIPH_GPIOD : Disable GPIOD clock
702 * @arg RCM_APB2_PERIPH_GPIOE : Disable GPIOE clock
703 * @arg RCM_APB2_PERIPH_GPIOF : Disable GPIOF clock
704 * @arg RCM_APB2_PERIPH_GPIOG : Disable GPIOG clock
705 * @arg RCM_APB2_PERIPH_ADC1 : Disable ADC1 clock
706 * @arg RCM_APB2_PERIPH_ADC2 : Disable ADC2 clock
707 * @arg RCM_APB2_PERIPH_TMR1 : Disable TMR1 clock
708 * @arg RCM_APB2_PERIPH_SPI1 : Disable SPI1 clock
709 * @arg RCM_APB2_PERIPH_TMR8 : Disable TMR8 clock
710 * @arg RCM_APB2_PERIPH_USART1 : Disable USART1 clock
711 * @arg RCM_APB2_PERIPH_ADC3 : Disable ADC3 clock
712 *
713 * @retval None
714 */
RCM_DisableAPB2PeriphClock(uint32_t APB2Periph)715 void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph)
716 {
717 RCM->APB2CLKEN &= (uint32_t)~APB2Periph;
718 }
719
720 /*!
721 * @brief Enable the Low Speed APB (APB1) peripheral clock
722 *
723 * @param APB1Periph : Enable specifies clock of the APB1 peripheral.
724 * This parameter can be any combination of the following values:
725 * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 clock
726 * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 clock
727 * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 clock
728 * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 clock
729 * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 clock
730 * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 clock
731 * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT clock
732 * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 clock
733 * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 clock
734 * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 clock
735 * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 clock
736 * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 clock
737 * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 clock
738 * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 clock
739 * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 clock
740 * @arg RCM_APB1_PERIPH_USB : Enable USB clock
741 * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 clock
742 * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 clock
743 * @arg RCM_APB1_PERIPH_BAKR : Enable BAKR clock
744 * @arg RCM_APB1_PERIPH_PMU : Enable PMU clock
745 * @arg RCM_APB1_PERIPH_DAC : Enable DAC clock
746 *
747 * @retval None
748 */
RCM_EnableAPB1PeriphClock(uint32_t APB1Periph)749 void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph)
750 {
751 RCM->APB1CLKEN |= APB1Periph;
752 }
753
754 /*!
755 * @brief Disable the Low Speed APB (APB1) peripheral clock
756 *
757 * @param APB1Periph : Disable specifies clock of the APB1 peripheral.
758 * This parameter can be any combination of the following values:
759 * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 clock
760 * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 clock
761 * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 clock
762 * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 clock
763 * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 clock
764 * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 clock
765 * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT clock
766 * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 clock
767 * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 clock
768 * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 clock
769 * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 clock
770 * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 clock
771 * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 clock
772 * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 clock
773 * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 clock
774 * @arg RCM_APB1_PERIPH_USB : Disable USB clock
775 * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 clock
776 * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 clock
777 * @arg RCM_APB1_PERIPH_BAKR : Disable BAKR clock
778 * @arg RCM_APB1_PERIPH_PMU : Disable PMU clock
779 * @arg RCM_APB1_PERIPH_DAC : Disable DAC clock
780 *
781 * @retval None
782 */
RCM_DisableAPB1PeriphClock(uint32_t APB1Periph)783 void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph)
784 {
785 RCM->APB1CLKEN &= (uint32_t)~APB1Periph;
786 }
787
788 /*!
789 * @brief Enable High Speed APB (APB2) peripheral reset
790 *
791 * @param APB2Periph : Enable specifies APB2 peripheral reset.
792 * This parameter can be any combination of the following values:
793 * @arg RCM_APB2_PERIPH_AFIO : Enable AFIO reset
794 * @arg RCM_APB2_PERIPH_GPIOA : Enable GPIOA reset
795 * @arg RCM_APB2_PERIPH_GPIOB : Enable GPIOB reset
796 * @arg RCM_APB2_PERIPH_GPIOC : Enable GPIOC reset
797 * @arg RCM_APB2_PERIPH_GPIOD : Enable GPIOD reset
798 * @arg RCM_APB2_PERIPH_GPIOE : Enable GPIOE reset
799 * @arg RCM_APB2_PERIPH_GPIOF : Enable GPIOF reset
800 * @arg RCM_APB2_PERIPH_GPIOG : Enable GPIOG reset
801 * @arg RCM_APB2_PERIPH_ADC1 : Enable ADC1 reset
802 * @arg RCM_APB2_PERIPH_ADC2 : Enable ADC2 reset
803 * @arg RCM_APB2_PERIPH_TMR1 : Enable TMR1 reset
804 * @arg RCM_APB2_PERIPH_SPI1 : Enable SPI1 reset
805 * @arg RCM_APB2_PERIPH_TMR8 : Enable TMR8 reset
806 * @arg RCM_APB2_PERIPH_USART1 : Enable USART1 reset
807 * @arg RCM_APB2_PERIPH_ADC3 : Enable ADC3 reset
808 *
809 * @retval None
810 */
RCM_EnableAPB2PeriphReset(uint32_t APB2Periph)811 void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph)
812 {
813 RCM->APB2RST |= APB2Periph;
814 }
815
816 /*!
817 * @brief Disable High Speed APB (APB2) peripheral reset
818 *
819 * @param APB2Periph : Disable specifies APB2 peripheral reset.
820 * This parameter can be any combination of the following values:
821 * @arg RCM_APB2_PERIPH_AFIO : Disable AFIO reset
822 * @arg RCM_APB2_PERIPH_GPIOA : Disable GPIOA reset
823 * @arg RCM_APB2_PERIPH_GPIOB : Disable GPIOB reset
824 * @arg RCM_APB2_PERIPH_GPIOC : Disable GPIOC reset
825 * @arg RCM_APB2_PERIPH_GPIOD : Disable GPIOD reset
826 * @arg RCM_APB2_PERIPH_GPIOE : Disable GPIOE reset
827 * @arg RCM_APB2_PERIPH_GPIOF : Disable GPIOF reset
828 * @arg RCM_APB2_PERIPH_GPIOG : Disable GPIOG reset
829 * @arg RCM_APB2_PERIPH_ADC1 : Disable ADC1 reset
830 * @arg RCM_APB2_PERIPH_ADC2 : Disable ADC2 reset
831 * @arg RCM_APB2_PERIPH_TMR1 : Disable TMR1 reset
832 * @arg RCM_APB2_PERIPH_SPI1 : Disable SPI1 reset
833 * @arg RCM_APB2_PERIPH_TMR8 : Disable TMR8 reset
834 * @arg RCM_APB2_PERIPH_USART1 : Disable USART1 reset
835 * @arg RCM_APB2_PERIPH_ADC3 : Disable ADC3 reset
836 *
837 * @retval None
838 */
RCM_DisableAPB2PeriphReset(uint32_t APB2Periph)839 void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph)
840 {
841 RCM->APB2RST &= (uint32_t)~APB2Periph;
842 }
843
844 /*!
845 * @brief Enable Low Speed APB (APB1) peripheral reset
846 *
847 * @param APB1Periph : Enable specifies APB1 peripheral reset.
848 * This parameter can be any combination of the following values:
849 * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 reset
850 * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 reset
851 * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 reset
852 * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 reset
853 * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 reset
854 * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 reset
855 * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT reset
856 * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 reset
857 * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 reset
858 * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 reset
859 * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 reset
860 * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 reset
861 * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 reset
862 * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 reset
863 * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 reset
864 * @arg RCM_APB1_PERIPH_USB : Enable USB reset
865 * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 reset
866 * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 reset
867 * @arg RCM_APB1_PERIPH_BAKR : Enable BAKR reset
868 * @arg RCM_APB1_PERIPH_PMU : Enable PMU reset
869 * @arg RCM_APB1_PERIPH_DAC : Enable DAC reset
870 *
871 * @retval None
872 */
RCM_EnableAPB1PeriphReset(uint32_t APB1Periph)873 void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph)
874 {
875 RCM->APB1RST |= APB1Periph;
876 }
877
878 /*!
879 * @brief Disable Low Speed APB (APB1) peripheral reset
880 *
881 * @param APB1Periph : Disable specifies APB1 peripheral reset.
882 * This parameter can be any combination of the following values:
883 * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 reset
884 * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 reset
885 * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 reset
886 * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 reset
887 * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 reset
888 * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 reset
889 * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT reset
890 * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 reset
891 * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 reset
892 * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 reset
893 * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 reset
894 * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 reset
895 * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 reset
896 * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 reset
897 * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 reset
898 * @arg RCM_APB1_PERIPH_USB : Disable USB reset
899 * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 reset
900 * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 reset
901 * @arg RCM_APB1_PERIPH_BAKR : Disable BAKR reset
902 * @arg RCM_APB1_PERIPH_PMU : Disable PMU reset
903 * @arg RCM_APB1_PERIPH_DAC : Disable DAC reset
904 *
905 * @retval None
906 */
RCM_DisableAPB1PeriphReset(uint32_t APB1Periph)907 void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph)
908 {
909 RCM->APB1RST &= (uint32_t)~APB1Periph;
910 }
911
912 /*!
913 * @brief Enable the Backup domain reset
914 *
915 * @param None
916 *
917 * @retval None
918 *
919 * @note
920 */
RCM_EnableBackupReset(void)921 void RCM_EnableBackupReset(void)
922 {
923 RCM->BDCTRL_B.BDRST = BIT_SET;
924 }
925
926 /*!
927 * @brief Disable the Backup domain reset
928 *
929 * @param None
930 *
931 * @retval None
932 */
RCM_DisableBackupReset(void)933 void RCM_DisableBackupReset(void)
934 {
935 RCM->BDCTRL_B.BDRST = BIT_RESET;
936 }
937
938 /*!
939 * @brief Enable RCM interrupts
940 *
941 * @param interrupt : Enable specifies RCM interrupt sources.
942 * This parameter can be any combination of the following values:
943 * @arg RCM_INT_LSIRDY : LSI ready interrupt
944 * @arg RCM_INT_LSERDY : LSE ready interrupt
945 * @arg RCM_INT_HSIRDY : HSI ready interrupt
946 * @arg RCM_INT_HSERDY : HSE ready interrupt
947 * @arg RCM_INT_PLLRDY : PLL ready interrupt
948 *
949 * @retval None
950 */
RCM_EnableInterrupt(uint32_t interrupt)951 void RCM_EnableInterrupt(uint32_t interrupt)
952 {
953 uint32_t temp;
954
955 temp = interrupt << 8;
956
957 RCM->INT |= temp;
958 }
959
960 /*!
961 * @brief Disable RCM interrupts
962 *
963 * @param interrupt : Disable specifies RCM interrupt sources.
964 * This parameter can be any combination of the following values:
965 * @arg RCM_INT_LSIRDY : LSI ready interrupt
966 * @arg RCM_INT_LSERDY : LSE ready interrupt
967 * @arg RCM_INT_HSIRDY : HSI ready interrupt
968 * @arg RCM_INT_HSERDY : HSE ready interrupt
969 * @arg RCM_INT_PLLRDY : PLL ready interrupt
970 *
971 * @retval None
972 */
RCM_DisableInterrupt(uint32_t interrupt)973 void RCM_DisableInterrupt(uint32_t interrupt)
974 {
975 uint32_t temp;
976
977 temp = interrupt << 8;
978
979 RCM->INT &= (uint32_t)~temp;
980 }
981
982 /*!
983 * @brief Read the specified RCM flag status
984 *
985 * @param flag : Returns specifies the flag status.
986 * This parameter can be one of the following values:
987 * @arg RCM_FLAG_HSIRDY : HSI ready flag
988 * @arg RCM_FLAG_HSERDY : HSE ready flag
989 * @arg RCM_FLAG_PLLRDY : PLL ready flag
990 * @arg RCM_FLAG_LSERDY : LSE ready flag
991 * @arg RCM_FLAG_LSIRDY : LSI ready flag
992 * @arg RCM_FLAG_PINRST : NRST PIN Reset Occur Flag
993 * @arg RCM_FLAG_PORRST : POR/PDR Reset Occur Flag
994 * @arg RCM_FLAG_SWRST : Software Reset Occur Flag
995 * @arg RCM_FLAG_IWDTRST : Independent Watchdog Reset Occur Flag
996 * @arg RCM_FLAG_WWDTRST : Window Watchdog Reset Occur Flag
997 * @arg RCM_FLAG_LPRRST : Low Power Reset Occur Flag
998 *
999 * @retval The new state of flag (SET or RESET)
1000 */
RCM_ReadStatusFlag(RCM_FLAG_T flag)1001 uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag)
1002 {
1003 uint32_t reg, bit;
1004
1005 bit = (uint32_t)(1 << (flag & 0xff));
1006
1007 reg = (flag >> 8) & 0xff;
1008
1009 switch (reg)
1010 {
1011 case 0:
1012 reg = RCM->CTRL;
1013 break;
1014
1015 case 1:
1016 reg = RCM->BDCTRL;
1017 break;
1018
1019 case 2:
1020 reg = RCM->CSTS;
1021 break;
1022
1023 default:
1024 break;
1025 }
1026
1027 if (reg & bit)
1028 {
1029 return SET;
1030 }
1031
1032 return RESET;
1033 }
1034
1035 /*!
1036 * @brief Clears all the RCM reset flags
1037 *
1038 * @param None
1039 *
1040 * @retval None
1041 *
1042 * @note The reset flags are:
1043 * RCM_FLAG_PINRST, RCM_FLAG_PWRST, RCM_FLAG_SWRST
1044 * RCM_FLAG_IWDTRST, RCM_FLAG_WWDTRST, RCM_FLAG_LPRRST
1045 */
RCM_ClearStatusFlag(void)1046 void RCM_ClearStatusFlag(void)
1047 {
1048 RCM->CSTS_B.RSTFLGCLR = BIT_SET;
1049 }
1050
1051 /*!
1052 * @brief Reads the specified RCM interrupt Flag
1053 *
1054 * @param flag : Reads specifies RCM interrupt flag.
1055 * This parameter can be one of the following values:
1056 * @arg RCM_INT_LSIRDY : LSI ready interrupt flag
1057 * @arg RCM_INT_LSERDY : LSE ready interrupt flag
1058 * @arg RCM_INT_HSIRDY : HSI ready interrupt flag
1059 * @arg RCM_INT_HSERDY : HSE ready interrupt flag
1060 * @arg RCM_INT_PLLRDY : PLL ready interrupt flag
1061 * @arg RCM_INT_CSS : Clock Security System interrupt flag
1062 *
1063 * @retval The new state of intFlag (SET or RESET)
1064 */
RCM_ReadIntFlag(RCM_INT_T flag)1065 uint8_t RCM_ReadIntFlag(RCM_INT_T flag)
1066 {
1067 uint8_t ret;
1068
1069 ret = (RCM->INT& flag) ? SET : RESET;
1070
1071 return ret;
1072 }
1073
1074 /*!
1075 * @brief Clears the interrupt flag
1076 *
1077 * @param flag : Clears specifies interrupt flag.
1078 * @arg RCM_INT_LSIRDY : Clear LSI ready interrupt flag
1079 * @arg RCM_INT_LSERDY : Clear LSE ready interrupt flag
1080 * @arg RCM_INT_HSIRDY : Clear HSI ready interrupt flag
1081 * @arg RCM_INT_HSERDY : Clear HSE ready interrupt flag
1082 * @arg RCM_INT_PLLRDY : Clear PLL ready interrupt flag
1083 * @arg RCM_INT_CSS : Clear Clock Security System interrupt flag
1084 *
1085 * @retval None
1086 */
RCM_ClearIntFlag(uint32_t flag)1087 void RCM_ClearIntFlag(uint32_t flag)
1088 {
1089 uint32_t temp;
1090
1091 temp = flag << 16;
1092 RCM->INT |= temp;
1093 }
1094
1095 /**@} end of group RCM_Functions */
1096 /**@} end of group RCM_Driver */
1097 /**@} end of group APM32E10x_StdPeriphDriver */
1098