1 /* 2 * File : at91sam7x.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2006, RT-Thread Develop Team 5 * 6 * The license and distribution terms for this file may be 7 * found in the file LICENSE in this distribution or at 8 * http://openlab.rt-thread.com/license/LICENSE 9 * 10 * Change Logs: 11 * Date Author Notes 12 * 2006-08-23 Bernard first version 13 */ 14 15 #ifndef __AT91SAM7S_H__ 16 #define __AT91SAM7S_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ 23 24 /* ========== Register definition for TC0 peripheral ========== */ 25 #define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ 26 #define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ 27 #define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ 28 #define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ 29 #define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ 30 #define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ 31 #define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ 32 #define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ 33 #define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ 34 #define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ 35 36 /* ========== Register definition for TC1 peripheral ========== */ 37 #define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ 38 #define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ 39 #define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ 40 #define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ 41 #define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ 42 #define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ 43 #define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ 44 #define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ 45 #define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ 46 #define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ 47 48 /* ========== Register definition for TC2 peripheral ========== */ 49 #define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ 50 #define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ 51 #define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ 52 #define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ 53 #define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ 54 #define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ 55 #define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ 56 #define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ 57 #define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ 58 #define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ 59 60 /* ========== Register definition for PITC peripheral ========== */ 61 #define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ 62 #define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ 63 #define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ 64 #define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ 65 66 /* ========== Register definition for UDP peripheral ========== */ 67 #define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ 68 #define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ 69 #define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ 70 #define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ 71 #define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ 72 #define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ 73 #define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ 74 #define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ 75 #define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ 76 #define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ 77 #define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) 78 #define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ 79 #define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) 80 #define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ 81 82 /* ========== Register definition for US0 peripheral ========== */ 83 #define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ 84 #define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ 85 #define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ 86 #define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ 87 #define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ 88 #define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ 89 #define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ 90 #define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ 91 #define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ 92 #define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ 93 #define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ 94 #define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ 95 #define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ 96 #define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ 97 98 /* ========== Register definition for AIC peripheral ========== */ 99 #define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ 100 #define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) 101 #define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ 102 #define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) 103 #define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ 104 #define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ 105 #define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ 106 #define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ 107 #define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ 108 #define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ 109 #define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ 110 #define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ 111 #define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ 112 #define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ 113 #define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ 114 #define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ 115 #define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ 116 #define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ 117 #define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ 118 #define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ 119 120 121 /* ========== Register definition for DBGU peripheral ========== */ 122 #define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ 123 #define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ 124 #define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ 125 #define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ 126 #define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ 127 #define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ 128 #define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ 129 #define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ 130 #define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ 131 #define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ 132 #define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ 133 #define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ 134 135 /* ========== Register definition for PIO peripheral ========== */ 136 #define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ 137 #define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ 138 #define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ 139 #define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ 140 #define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ 141 #define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ 142 #define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ 143 #define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ 144 #define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ 145 #define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ 146 #define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ 147 #define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ 148 #define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ 149 #define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ 150 #define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ 151 #define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ 152 #define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ 153 #define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ 154 #define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ 155 #define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ 156 #define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ 157 #define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ 158 #define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ 159 #define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ 160 #define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ 161 #define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ 162 #define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ 163 #define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ 164 #define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ 165 166 // ========== Register definition for PIOA peripheral ========== 167 #define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register 168 #define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register 169 #define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register 170 #define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register 171 #define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register 172 #define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register 173 #define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register 174 #define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register 175 #define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register 176 #define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register 177 #define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register 178 #define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register 179 #define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register 180 #define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register 181 #define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr 182 #define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register 183 #define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register 184 #define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register 185 #define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register 186 #define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register 187 #define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register 188 #define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register 189 #define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register 190 #define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register 191 #define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register 192 #define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register 193 #define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register 194 #define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register 195 #define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register 196 // ========== Register definition for PIOB peripheral ========== 197 #define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register 198 #define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register 199 #define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register 200 #define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register 201 #define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register 202 #define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register 203 #define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register 204 #define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register 205 #define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register 206 #define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register 207 #define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register 208 #define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register 209 #define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register 210 #define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr 211 #define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register 212 #define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register 213 #define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register 214 #define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register 215 #define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register 216 #define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register 217 #define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register 218 #define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register 219 #define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register 220 #define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register 221 #define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register 222 #define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register 223 #define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register 224 #define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register 225 #define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register 226 227 /* ========== Register definition for PMC peripheral ========== */ 228 #define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ 229 #define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ 230 #define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ 231 #define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ 232 #define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ 233 #define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ 234 #define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ 235 #define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ 236 #define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ 237 #define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ 238 #define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ 239 #define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ 240 #define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ 241 #define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ 242 #define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ 243 244 // ========== Register definition for PDC_SPI1 peripheral ========== 245 #define AT91C_SPI1_RNPR (AT91_REG(0xFFFE4110)) // (PDC_SPI1) Receive Next Pointer Register 246 #define AT91C_SPI1_TPR (AT91_REG(0xFFFE4108)) // (PDC_SPI1) Transmit Pointer Register 247 #define AT91C_SPI1_RPR (AT91_REG(0xFFFE4100)) // (PDC_SPI1) Receive Pointer Register 248 #define AT91C_SPI1_PTSR (AT91_REG(0xFFFE4124)) // (PDC_SPI1) PDC Transfer Status Register 249 #define AT91C_SPI1_RCR (AT91_REG(0xFFFE4104)) // (PDC_SPI1) Receive Counter Register 250 #define AT91C_SPI1_TCR (AT91_REG(0xFFFE410C)) // (PDC_SPI1) Transmit Counter Register 251 #define AT91C_SPI1_RNCR (AT91_REG(0xFFFE4114)) // (PDC_SPI1) Receive Next Counter Register 252 #define AT91C_SPI1_TNCR (AT91_REG(0xFFFE411C)) // (PDC_SPI1) Transmit Next Counter Register 253 #define AT91C_SPI1_TNPR (AT91_REG(0xFFFE4118)) // (PDC_SPI1) Transmit Next Pointer Register 254 #define AT91C_SPI1_PTCR (AT91_REG(0xFFFE4120)) // (PDC_SPI1) PDC Transfer Control Register 255 // ========== Register definition for SPI1 peripheral ========== 256 #define AT91C_SPI1_CSR (AT91_REG(0xFFFE4030)) // (SPI1) Chip Select Register 257 #define AT91C_SPI1_IDR (AT91_REG(0xFFFE4018)) // (SPI1) Interrupt Disable Register 258 #define AT91C_SPI1_SR (AT91_REG(0xFFFE4010)) // (SPI1) Status Register 259 #define AT91C_SPI1_RDR (AT91_REG(0xFFFE4008)) // (SPI1) Receive Data Register 260 #define AT91C_SPI1_CR (AT91_REG(0xFFFE4000)) // (SPI1) Control Register 261 #define AT91C_SPI1_IMR (AT91_REG(0xFFFE401C)) // (SPI1) Interrupt Mask Register 262 #define AT91C_SPI1_IER (AT91_REG(0xFFFE4014)) // (SPI1) Interrupt Enable Register 263 #define AT91C_SPI1_TDR (AT91_REG(0xFFFE400C)) // (SPI1) Transmit Data Register 264 #define AT91C_SPI1_MR (AT91_REG(0xFFFE4004)) // (SPI1) Mode Register 265 // ========== Register definition for PDC_SPI0 peripheral ========== 266 #define AT91C_SPI0_PTCR (AT91_REG(0xFFFE0120)) // (PDC_SPI0) PDC Transfer Control Register 267 #define AT91C_SPI0_TNPR (AT91_REG(0xFFFE0118)) // (PDC_SPI0) Transmit Next Pointer Register 268 #define AT91C_SPI0_RNPR (AT91_REG(0xFFFE0110)) // (PDC_SPI0) Receive Next Pointer Register 269 #define AT91C_SPI0_TPR (AT91_REG(0xFFFE0108)) // (PDC_SPI0) Transmit Pointer Register 270 #define AT91C_SPI0_RPR (AT91_REG(0xFFFE0100)) // (PDC_SPI0) Receive Pointer Register 271 #define AT91C_SPI0_PTSR (AT91_REG(0xFFFE0124)) // (PDC_SPI0) PDC Transfer Status Register 272 #define AT91C_SPI0_TNCR (AT91_REG(0xFFFE011C)) // (PDC_SPI0) Transmit Next Counter Register 273 #define AT91C_SPI0_RNCR (AT91_REG(0xFFFE0114)) // (PDC_SPI0) Receive Next Counter Register 274 #define AT91C_SPI0_TCR (AT91_REG(0xFFFE010C)) // (PDC_SPI0) Transmit Counter Register 275 #define AT91C_SPI0_RCR (AT91_REG(0xFFFE0104)) // (PDC_SPI0) Receive Counter Register 276 // ========== Register definition for SPI0 peripheral ========== 277 #define AT91C_SPI0_CSR (AT91_REG(0xFFFE0030)) // (SPI0) Chip Select Register 278 #define AT91C_SPI0_IDR (AT91_REG(0xFFFE0018)) // (SPI0) Interrupt Disable Register 279 #define AT91C_SPI0_SR (AT91_REG(0xFFFE0010)) // (SPI0) Status Register 280 #define AT91C_SPI0_RDR (AT91_REG(0xFFFE0008)) // (SPI0) Receive Data Register 281 #define AT91C_SPI0_CR (AT91_REG(0xFFFE0000)) // (SPI0) Control Register 282 #define AT91C_SPI0_IMR (AT91_REG(0xFFFE001C)) // (SPI0) Interrupt Mask Register 283 #define AT91C_SPI0_IER (AT91_REG(0xFFFE0014)) // (SPI0) Interrupt Enable Register 284 #define AT91C_SPI0_TDR (AT91_REG(0xFFFE000C)) // (SPI0) Transmit Data Register 285 #define AT91C_SPI0_MR (AT91_REG(0xFFFE0004)) // (SPI0) Mode Register 286 287 /******************************************************************************/ 288 /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ 289 /******************************************************************************/ 290 #define AT91C_ID_FIQ ( 0) /* Advanced Interrupt Controller (FIQ) */ 291 #define AT91C_ID_SYS ( 1) /* System Peripheral */ 292 #define AT91C_ID_PIOA ( 2) /* Parallel IO Controller A */ 293 #define AT91C_ID_PIOB ( 3) /* Parallel IO Controller B */ 294 #define AT91C_ID_SPI0 ( 4) /* Serial Peripheral Interface 0 */ 295 #define AT91C_ID_SPI1 ( 5) /* Serial Peripheral Interface 1 */ 296 #define AT91C_ID_US0 ( 6) /* USART 0 */ 297 #define AT91C_ID_US1 ( 7) /* USART 1 */ 298 #define AT91C_ID_SSC ( 8) /* Serial Synchronous Controller */ 299 #define AT91C_ID_TWI ( 9) /* Two-Wire Interface */ 300 #define AT91C_ID_PWMC (10) /* PWM Controller */ 301 #define AT91C_ID_UDP (11) /* USB Device Port */ 302 #define AT91C_ID_TC0 (12) /* Timer Counter 0 */ 303 #define AT91C_ID_TC1 (13) /* Timer Counter 1 */ 304 #define AT91C_ID_TC2 (14) /* Timer Counter 2 */ 305 #define AT91C_ID_CAN (15) /* Control Area Network Controller */ 306 #define AT91C_ID_EMAC (16) /* Ethernet MAC */ 307 #define AT91C_ID_ADC (17) /* Analog-to-Digital Converter */ 308 #define AT91C_ID_AES (18) /* Advanced Encryption Standard 128-bit */ 309 #define AT91C_ID_TDES (19) /* Triple Data Encryption Standard */ 310 #define AT91C_ID_20_Reserved (20) /* Reserved */ 311 #define AT91C_ID_21_Reserved (21) /* Reserved */ 312 #define AT91C_ID_22_Reserved (22) /* Reserved */ 313 #define AT91C_ID_23_Reserved (23) /* Reserved */ 314 #define AT91C_ID_24_Reserved (24) /* Reserved */ 315 #define AT91C_ID_25_Reserved (25) /* Reserved */ 316 #define AT91C_ID_26_Reserved (26) /* Reserved */ 317 #define AT91C_ID_27_Reserved (27) /* Reserved */ 318 #define AT91C_ID_28_Reserved (28) /* Reserved */ 319 #define AT91C_ID_29_Reserved (29) /* Reserved */ 320 #define AT91C_ID_IRQ0 (30) /* Advanced Interrupt Controller (IRQ0) */ 321 #define AT91C_ID_IRQ1 (31) /* Advanced Interrupt Controller (IRQ1) */ 322 #define AT91C_ALL_INT (0xC00FFFFF) /* ALL VALID INTERRUPTS */ 323 324 #define MCK 48054857 325 326 /*****************************/ 327 /* CPU Mode */ 328 /*****************************/ 329 #define USERMODE 0x10 330 #define FIQMODE 0x11 331 #define IRQMODE 0x12 332 #define SVCMODE 0x13 333 #define ABORTMODE 0x17 334 #define UNDEFMODE 0x1b 335 #define MODEMASK 0x1f 336 #define NOINT 0xc0 337 338 #ifdef __cplusplus 339 } 340 #endif 341 342 #endif 343