1 /* 2 ******************************************************************************* 3 * Copyright(C) NEC Electronics Corporation 2010 4 * All rights reserved by NEC Electronics Corporation. 5 * This program should be used on your own responsibility. 6 * NEC Electronics Corporation assumes no responsibility for any losses 7 * incurred by customers or third parties arising from the use of this file. 8 * 9 * This device driver was created by Applilet3 for V850ES/Jx3 10 * 32-Bit Single-Chip Microcontrollers 11 * Filename: CG_system.h 12 * Abstract: This file implements device driver for System module. 13 * APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] 14 * Device: uPD70F3746 15 * Compiler: IAR Systems ICCV850 16 * Creation date: 6/26/2010 17 ******************************************************************************* 18 */ 19 20 #ifndef _MDSYSTEM_ 21 #define _MDSYSTEM_ 22 /* 23 ******************************************************************************* 24 ** Register bit define 25 ******************************************************************************* 26 */ 27 /* 28 Processor clock control register (PCC) 29 */ 30 #define _03_CG_PCC_INITIALVALUE 0x03U 31 /* Use of subclock on-chip feedback resistor (FRC) */ 32 #define _00_CG_SUBCLK_FEEDBACK_USE 0x00U /* subclock on-chip feedback resistor connected */ 33 #define _08_CG_SUBCLK_FEEDBACK_UNUSE 0x80U /* subclock on-chip feedback resistor not connected */ 34 /* Main clock osillator control (MCK) */ 35 #define _00_CG_MAINCLK_ENABLE 0x00U /* main clock oscillation enabled */ 36 #define _04_CG_MAINCLK_STOP 0x40U /* main clock oscillation stopped */ 37 /* Use of main clock on-chip feedback resistor (MFRC) */ 38 #define _00_CG_MAINCLK_FEEDBACK_USE 0x00U /* main clock feedback resistor connected */ 39 #define _20_CG_MAINCLK_FEEDBACK_UNUSE 0x20U /* main clock feedback resistor not connected */ 40 /* Status of CPU clock fCPU (CLS) */ 41 #define _00_CG_CPUCLK_MAINCLK 0x00U /* main clock operation */ 42 #define _10_CG_CPUCLK_SUBCLK 0x10U /* subclock operation */ 43 /* Clock(fCLK/fCPU) selection (CK3 - CK0) */ 44 #define _0F_CG_CPUCLK 0x0FU 45 #define _00_CG_CPUCLK_MAIN0 0x00U /* fCPU = fXX */ 46 #define _01_CG_CPUCLK_MAIN1 0x01U /* fCPU = fXX/2 */ 47 #define _02_CG_CPUCLK_MAIN2 0x02U /* fCPU = fXX/2^2 */ 48 #define _03_CG_CPUCLK_MAIN3 0x03U /* fCPU = fXX/2^3 */ 49 #define _04_CG_CPUCLK_MAIN4 0x04U /* fCPU = fXX/2^4 */ 50 #define _05_CG_CPUCLK_MAIN5 0x05U /* fCPU = fXX/2^5 */ 51 #define _0B_CG_CPUCLK_SUB 0x0BU /* fXT */ 52 53 /* 54 Internal oscillator mode register (RCM) 55 */ 56 /* Oscillation/stop of internal oscillator (RSTOP) */ 57 #define _00_CG_INTER_OSC_ON 0x00U /* internal oscillator oscillation */ 58 #define _01_CG_INTER_OSC_OFF 0x01U /* internal oscillator stopped */ 59 60 /* 61 CPU operation clock status register (CCLS) 62 */ 63 /* CPU operation clock status (CCLSF) */ 64 #define _00_CG_CPUCLK_STATUS_MAINORSUB 0x00U /* operating on main clock(fX) or subclock(fXT) */ 65 #define _01_CG_CPUCLK_STATUS_INTEROSC 0x01U /* operating on internal oscillation clock(fR) */ 66 67 /* 68 Lock register (LOCKR) 69 */ 70 /* PLL lock status check (LOCK) */ 71 #define _00_CG_PLLSTATUS_LOCK 0x00U /* locked status */ 72 #define _01_CG_PLLSTATUS_UNLOCK 0x01U /* unlocked status */ 73 74 /* 75 PLL control register (PLLCTL) 76 */ 77 #define _01_CG_PLLCTL_INITIALVALUE 0x01U 78 /* CPU operation clock selection register (SELPLL) */ 79 #define _00_CG_CPUCLK_CLKTHROUGH 0x00U /* clock-through mode */ 80 #define _02_CG_CPUCLK_PLL 0x02U /* PLL mode */ 81 /* PLL operation stop register (PLLON) */ 82 #define _00_CG_CPUCLK_PLLOFF 0x00U /* PLL stopped */ 83 #define _01_CG_CPUCLK_PLLON 0x01U /* PLL operating */ 84 85 /* 86 Clock control register (CKC) 87 */ 88 #define _0A_CG_CKC_INITIALVALUE 0x0AU 89 /* Internal system clock(fXX) in PLL mode */ 90 #define _00_CG_CPUCLK_4PLL 0x00U /* fXX = 4* fX (fX = 2.5 to 5.0 MHz) */ 91 #define _01_CG_CPUCLK_8PLL 0x01U /* fXX = 8* fX (fX = 2.5 to 4.0 MHz) */ 92 93 /* 94 PLL lockup time specification register (PLLS) 95 */ 96 #define _03_CG_PLLS_INITIALVALUE 0x03U 97 /* PLL lockup time selection (PLLS2 - PLLS0) */ 98 #define _00_CG_PLLLOCKUP_SEL0 0x00U /* 2^10/fX */ 99 #define _01_CG_PLLLOCKUP_SEL1 0x01U /* 2^11/fX*/ 100 #define _02_CG_PLLLOCKUP_SEL2 0x02U /* 2^12/fX */ 101 #define _03_CG_PLLLOCKUP_SEL3 0x03U /* 2^13/fX (default value) */ 102 103 /* 104 Power save control register (PSC) 105 */ 106 /* Stand-by mode release control by occurrence of INTWDT2 signal (NMI1M) */ 107 #define _00_CG_STANDBY_INTWDT2EN 0x00U /* enable releasing stand-by mode by INTWDT2 signal */ 108 #define _40_CG_STANDBY_INTWDT2DIS 0x40U /* disable releasing stand-by mode by INTWDT2 signal */ 109 /* Stand-by mode release control by NMI pin input (NMI0M) */ 110 #define _00_CG_STANDBY_NMIEN 0x00U /* enable releasing stand-by mode by NMI pin input */ 111 #define _20_CG_STANDBY_NMIDIS 0x20U /* disable releasing stand-by mode by NMI pin input */ 112 /* Stand-by mode release control by maskable interrupt request signal (NMI0M) */ 113 #define _00_CG_STANDBY_MASKIEN 0x00U /* enable releasing stand-by mode by maskable interrupt request signal */ 114 #define _10_CG_STANDBY_MASKIDIS 0x10U /* disable releasing stand-by mode by maskable interrupt request signal */ 115 /* Setting of stand-by mode (STP) */ 116 #define _00_CG_STANDBY_UNUSE 0x00U /* normal mode */ 117 #define _02_CG_STANDBY_USE 0x02U /* stand-by mode */ 118 119 /* 120 Power save mode control register (PSMR) 121 */ 122 /* Specification of operation in software stand-by mode (PSM1,PSM0) */ 123 #define _00_CG_POWERSAVE_IDLE1 0x00U /* IDLE1, sub-IDLE modes */ 124 #define _01_CG_POWERSAVE_STOP1 0x01U /* STOP, sub-IDLE modes */ 125 #define _02_CG_POWERSAVE_IDLE2 0x02U /* IDLE2, sub-IDLE modes */ 126 #define _03_CG_POWERSAVE_STOP2 0x03U /* STOP mode */ 127 128 /* 129 Clock monitor mode register (CLM) 130 */ 131 /* Clock monitor operation enable or disable (CLME) */ 132 #define _01_CG_MONITOR_ENABLE 0x01U /* enable clock monitor operation */ 133 #define _00_CG_MONITOR_DISABLE 0x00U /* disable clock monitor operation */ 134 135 /* 136 Watchdog Timer 2 mode register (WDTM2) 137 */ 138 /* Selection of operation mode (WDM21, WDM20) */ 139 #define _00_WDT2_OPERMODE_STOP 0x00U /* stops operation */ 140 #define _20_WDT2_OPERMODE_NONMASK 0x20U /* non-maskable interrupt request mode (generation of INTWDT2) */ 141 #define _40_WDT2_OPERMODE_RESET 0x40U /* reset mode (generation of RESWDT2) */ 142 /* Selection of clock mode (WDCS24,WDCS23) */ 143 #define _00_WDT2_CLKMODE_INTEROSC 0x00U /* use internal oscillator */ 144 #define _08_WDT2_CLKMODE_MAINCLK 0x08U /* use Main clock */ 145 #define _10_WDT2_CLKMODE_SUBCLK 0x10U /* use subclock */ 146 /* Watchdog Timer 2 clock Selection (WDCS22 - WDCS20) */ 147 #define _00_WDT2_CLOCK_SEL0 0x00U /* 2^12/fR or 2^18/fXX or 2^9/fXT */ 148 #define _01_WDT2_CLOCK_SEL1 0x01U /* 2^13/fR or 2^19/fXX or 2^10/fXT */ 149 #define _02_WDT2_CLOCK_SEL2 0x02U /* 2^14/fR or 2^20/fXX or 2^11/fXT */ 150 #define _03_WDT2_CLOCK_SEL3 0x03U /* 2^15/fR or 2^21/fXX or 2^12/fXT */ 151 #define _04_WDT2_CLOCK_SEL4 0x04U /* 2^16/fR or 2^22/fXX or 2^13/fXT */ 152 #define _05_WDT2_CLOCK_SEL5 0x05U /* 2^17/fR or 2^23/fXX or 2^14/fXT */ 153 #define _06_WDT2_CLOCK_SEL6 0x06U /* 2^18/fR or 2^24/fXX or 2^15/fXT */ 154 #define _07_WDT2_CLOCK_SEL7 0x07U /* 2^19/fR or 2^25/fXX or 2^16/fXT */ 155 /* 156 ******************************************************************************* 157 ** Macro define 158 ******************************************************************************* 159 */ 160 #define _00_CG_VSWC_VALUE 0x00U 161 /* 162 ******************************************************************************* 163 ** Function define 164 ******************************************************************************* 165 */ 166 void CLOCK_Init(void); 167 void WDT2_Restart(void); 168 void CG_ReadResetSource(void); 169 170 /* Start user code for function. Do not edit comment generated here */ 171 /* End user code. Do not edit comment generated here */ 172 #endif 173