1 /**
2 ******************************************************************************
3 * @file system_stm32l1xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32l1xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 ******************************************************************************
22 * @attention
23 *
24 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
25 * All rights reserved.</center></h2>
26 *
27 * This software component is licensed by ST under BSD 3-Clause license,
28 * the "License"; You may not use this file except in compliance with the
29 * License. You may obtain a copy of the License at:
30 * opensource.org/licenses/BSD-3-Clause
31 *
32 ******************************************************************************
33 */
34
35 /** @addtogroup CMSIS
36 * @{
37 */
38
39 /** @addtogroup stm32l1xx_system
40 * @{
41 */
42
43 /** @addtogroup STM32L1xx_System_Private_Includes
44 * @{
45 */
46
47 #include "stm32l1xx.h"
48
49 /**
50 * @}
51 */
52
53 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
54 * @{
55 */
56
57 /**
58 * @}
59 */
60
61 /** @addtogroup STM32L1xx_System_Private_Defines
62 * @{
63 */
64 #if !defined (HSE_VALUE)
65 #define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
66 This value can be provided and adapted by the user application. */
67 #endif /* HSE_VALUE */
68
69 #if !defined (HSI_VALUE)
70 #define HSI_VALUE ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.
71 This value can be provided and adapted by the user application. */
72 #endif /* HSI_VALUE */
73
74 /*!< Uncomment the following line if you need to use external SRAM mounted
75 on STM32L152D_EVAL board as data memory */
76 /* #define DATA_IN_ExtSRAM */
77
78 /* Note: Following vector table addresses must be defined in line with linker
79 configuration. */
80 /*!< Uncomment the following line if you need to relocate the vector table
81 anywhere in Flash or Sram, else the vector table is kept at the automatic
82 remap of boot address selected */
83 /* #define USER_VECT_TAB_ADDRESS */
84
85 #if defined(USER_VECT_TAB_ADDRESS)
86 /*!< Uncomment the following line if you need to relocate your vector Table
87 in Sram else user remap will be done in Flash. */
88 /* #define VECT_TAB_SRAM */
89 #if defined(VECT_TAB_SRAM)
90 #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
91 This value must be a multiple of 0x200. */
92 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
93 This value must be a multiple of 0x200. */
94 #else
95 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
96 This value must be a multiple of 0x200. */
97 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
98 This value must be a multiple of 0x200. */
99 #endif /* VECT_TAB_SRAM */
100 #endif /* USER_VECT_TAB_ADDRESS */
101
102 /******************************************************************************/
103 /**
104 * @}
105 */
106
107 /** @addtogroup STM32L1xx_System_Private_Macros
108 * @{
109 */
110
111 /**
112 * @}
113 */
114
115 /** @addtogroup STM32L1xx_System_Private_Variables
116 * @{
117 */
118 /* This variable is updated in three ways:
119 1) by calling CMSIS function SystemCoreClockUpdate()
120 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
121 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
122 Note: If you use this function to configure the system clock; then there
123 is no need to call the 2 first functions listed above, since SystemCoreClock
124 variable is updated automatically.
125 */
126 uint32_t SystemCoreClock = 2097000U;
127 const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
128 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
129 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
130
131 /**
132 * @}
133 */
134
135 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
136 * @{
137 */
138
139 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
140 #ifdef DATA_IN_ExtSRAM
141 static void SystemInit_ExtMemCtl(void);
142 #endif /* DATA_IN_ExtSRAM */
143 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
144
145 /**
146 * @}
147 */
148
149 /** @addtogroup STM32L1xx_System_Private_Functions
150 * @{
151 */
152
153 /**
154 * @brief Setup the microcontroller system.
155 * Initialize the Embedded Flash Interface, the PLL and update the
156 * SystemCoreClock variable.
157 * @param None
158 * @retval None
159 */
SystemInit(void)160 void SystemInit (void)
161 {
162 #ifdef DATA_IN_ExtSRAM
163 SystemInit_ExtMemCtl();
164 #endif /* DATA_IN_ExtSRAM */
165
166 /* Configure the Vector Table location -------------------------------------*/
167 #if defined(USER_VECT_TAB_ADDRESS)
168 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
169 #endif /* USER_VECT_TAB_ADDRESS */
170 }
171
172 /**
173 * @brief Update SystemCoreClock according to Clock Register Values
174 * The SystemCoreClock variable contains the core clock (HCLK), it can
175 * be used by the user application to setup the SysTick timer or configure
176 * other parameters.
177 *
178 * @note Each time the core clock (HCLK) changes, this function must be called
179 * to update SystemCoreClock variable value. Otherwise, any configuration
180 * based on this variable will be incorrect.
181 *
182 * @note - The system frequency computed by this function is not the real
183 * frequency in the chip. It is calculated based on the predefined
184 * constant and the selected clock source:
185 *
186 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
187 * value as defined by the MSI range.
188 *
189 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
190 *
191 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
192 *
193 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
194 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
195 *
196 * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
197 * 16 MHz) but the real value may vary depending on the variations
198 * in voltage and temperature.
199 *
200 * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
201 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
202 * frequency of the crystal used. Otherwise, this function may
203 * have wrong result.
204 *
205 * - The result of this function could be not correct when using fractional
206 * value for HSE crystal.
207 * @param None
208 * @retval None
209 */
SystemCoreClockUpdate(void)210 void SystemCoreClockUpdate (void)
211 {
212 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
213
214 /* Get SYSCLK source -------------------------------------------------------*/
215 tmp = RCC->CFGR & RCC_CFGR_SWS;
216
217 switch (tmp)
218 {
219 case 0x00: /* MSI used as system clock */
220 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
221 SystemCoreClock = (32768 * (1 << (msirange + 1)));
222 break;
223 case 0x04: /* HSI used as system clock */
224 SystemCoreClock = HSI_VALUE;
225 break;
226 case 0x08: /* HSE used as system clock */
227 SystemCoreClock = HSE_VALUE;
228 break;
229 case 0x0C: /* PLL used as system clock */
230 /* Get PLL clock source and multiplication factor ----------------------*/
231 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
232 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
233 pllmul = PLLMulTable[(pllmul >> 18)];
234 plldiv = (plldiv >> 22) + 1;
235
236 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
237
238 if (pllsource == 0x00)
239 {
240 /* HSI oscillator clock selected as PLL clock entry */
241 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
242 }
243 else
244 {
245 /* HSE selected as PLL clock entry */
246 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
247 }
248 break;
249 default: /* MSI used as system clock */
250 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
251 SystemCoreClock = (32768 * (1 << (msirange + 1)));
252 break;
253 }
254 /* Compute HCLK clock frequency --------------------------------------------*/
255 /* Get HCLK prescaler */
256 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
257 /* HCLK clock frequency */
258 SystemCoreClock >>= tmp;
259 }
260
261 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
262 #ifdef DATA_IN_ExtSRAM
263 /**
264 * @brief Setup the external memory controller.
265 * Called in SystemInit() function before jump to main.
266 * This function configures the external SRAM mounted on STM32L152D_EVAL board
267 * This SRAM will be used as program data memory (including heap and stack).
268 * @param None
269 * @retval None
270 */
SystemInit_ExtMemCtl(void)271 void SystemInit_ExtMemCtl(void)
272 {
273 __IO uint32_t tmpreg = 0;
274
275 /* Flash 1 wait state */
276 FLASH->ACR |= FLASH_ACR_LATENCY;
277
278 /* Power enable */
279 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
280
281 /* Delay after an RCC peripheral clock enabling */
282 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
283
284 /* Select the Voltage Range 1 (1.8 V) */
285 PWR->CR = PWR_CR_VOS_0;
286
287 /* Wait Until the Voltage Regulator is ready */
288 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
289 {
290 }
291
292 /*-- GPIOs Configuration -----------------------------------------------------*/
293 /*
294 +-------------------+--------------------+------------------+------------------+
295 + SRAM pins assignment +
296 +-------------------+--------------------+------------------+------------------+
297 | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
298 | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
299 | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
300 | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
301 | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
302 | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
303 | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
304 | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
305 | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
306 | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
307 | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
308 | PD15 <-> FSMC_D1 |--------------------+
309 +-------------------+
310 */
311
312 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
313 RCC->AHBENR = 0x000080D8;
314
315 /* Delay after an RCC peripheral clock enabling */
316 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
317
318 /* Connect PDx pins to FSMC Alternate function */
319 GPIOD->AFR[0] = 0x00CC00CC;
320 GPIOD->AFR[1] = 0xCCCCCCCC;
321 /* Configure PDx pins in Alternate function mode */
322 GPIOD->MODER = 0xAAAA0A0A;
323 /* Configure PDx pins speed to 40 MHz */
324 GPIOD->OSPEEDR = 0xFFFF0F0F;
325 /* Configure PDx pins Output type to push-pull */
326 GPIOD->OTYPER = 0x00000000;
327 /* No pull-up, pull-down for PDx pins */
328 GPIOD->PUPDR = 0x00000000;
329
330 /* Connect PEx pins to FSMC Alternate function */
331 GPIOE->AFR[0] = 0xC00000CC;
332 GPIOE->AFR[1] = 0xCCCCCCCC;
333 /* Configure PEx pins in Alternate function mode */
334 GPIOE->MODER = 0xAAAA800A;
335 /* Configure PEx pins speed to 40 MHz */
336 GPIOE->OSPEEDR = 0xFFFFC00F;
337 /* Configure PEx pins Output type to push-pull */
338 GPIOE->OTYPER = 0x00000000;
339 /* No pull-up, pull-down for PEx pins */
340 GPIOE->PUPDR = 0x00000000;
341
342 /* Connect PFx pins to FSMC Alternate function */
343 GPIOF->AFR[0] = 0x00CCCCCC;
344 GPIOF->AFR[1] = 0xCCCC0000;
345 /* Configure PFx pins in Alternate function mode */
346 GPIOF->MODER = 0xAA000AAA;
347 /* Configure PFx pins speed to 40 MHz */
348 GPIOF->OSPEEDR = 0xFF000FFF;
349 /* Configure PFx pins Output type to push-pull */
350 GPIOF->OTYPER = 0x00000000;
351 /* No pull-up, pull-down for PFx pins */
352 GPIOF->PUPDR = 0x00000000;
353
354 /* Connect PGx pins to FSMC Alternate function */
355 GPIOG->AFR[0] = 0x00CCCCCC;
356 GPIOG->AFR[1] = 0x00000C00;
357 /* Configure PGx pins in Alternate function mode */
358 GPIOG->MODER = 0x00200AAA;
359 /* Configure PGx pins speed to 40 MHz */
360 GPIOG->OSPEEDR = 0x00300FFF;
361 /* Configure PGx pins Output type to push-pull */
362 GPIOG->OTYPER = 0x00000000;
363 /* No pull-up, pull-down for PGx pins */
364 GPIOG->PUPDR = 0x00000000;
365
366 /*-- FSMC Configuration ------------------------------------------------------*/
367 /* Enable the FSMC interface clock */
368 RCC->AHBENR = 0x400080D8;
369
370 /* Delay after an RCC peripheral clock enabling */
371 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
372
373 (void)(tmpreg);
374
375 /* Configure and enable Bank1_SRAM3 */
376 FSMC_Bank1->BTCR[4] = 0x00001011;
377 FSMC_Bank1->BTCR[5] = 0x00000300;
378 FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
379 /*
380 Bank1_SRAM3 is configured as follow:
381
382 p.FSMC_AddressSetupTime = 0;
383 p.FSMC_AddressHoldTime = 0;
384 p.FSMC_DataSetupTime = 3;
385 p.FSMC_BusTurnAroundDuration = 0;
386 p.FSMC_CLKDivision = 0;
387 p.FSMC_DataLatency = 0;
388 p.FSMC_AccessMode = FSMC_AccessMode_A;
389
390 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
391 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
392 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
393 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
394 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
395 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
396 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
397 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
398 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
399 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
400 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
401 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
402 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
403 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
404 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
405
406 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
407
408 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
409 */
410
411 }
412 #endif /* DATA_IN_ExtSRAM */
413 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
414
415 /**
416 * @}
417 */
418
419 /**
420 * @}
421 */
422
423 /**
424 * @}
425 */
426
427 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
428