1 /**************************************************************************//**
2 * @file cmsis_iccarm.h
3 * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
4 * @version V5.0.8
5 * @date 04. September 2018
6 ******************************************************************************/
7
8 //------------------------------------------------------------------------------
9 //
10 // Copyright (c) 2017-2018 IAR Systems
11 //
12 // Licensed under the Apache License, Version 2.0 (the "License")
13 // you may not use this file except in compliance with the License.
14 // You may obtain a copy of the License at
15 // http://www.apache.org/licenses/LICENSE-2.0
16 //
17 // Unless required by applicable law or agreed to in writing, software
18 // distributed under the License is distributed on an "AS IS" BASIS,
19 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 // See the License for the specific language governing permissions and
21 // limitations under the License.
22 //
23 //------------------------------------------------------------------------------
24
25
26 #ifndef __CMSIS_ICCARM_H__
27 #define __CMSIS_ICCARM_H__
28
29 #ifndef __ICCARM__
30 #error This file should only be compiled by ICCARM
31 #endif
32
33 #pragma system_include
34
35 #define __IAR_FT _Pragma("inline=forced") __intrinsic
36
37 #if (__VER__ >= 8000000)
38 #define __ICCARM_V8 1
39 #else
40 #define __ICCARM_V8 0
41 #endif
42
43 #ifndef __ALIGNED
44 #if __ICCARM_V8
45 #define __ALIGNED(x) __attribute__((aligned(x)))
46 #elif (__VER__ >= 7080000)
47 /* Needs IAR language extensions */
48 #define __ALIGNED(x) __attribute__((aligned(x)))
49 #else
50 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
51 #define __ALIGNED(x)
52 #endif
53 #endif
54
55
56 /* Define compiler macros for CPU architecture, used in CMSIS 5.
57 */
58 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
59 /* Macros already defined */
60 #else
61 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
62 #define __ARM_ARCH_8M_MAIN__ 1
63 #elif defined(__ARM8M_BASELINE__)
64 #define __ARM_ARCH_8M_BASE__ 1
65 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
66 #if __ARM_ARCH == 6
67 #define __ARM_ARCH_6M__ 1
68 #elif __ARM_ARCH == 7
69 #if __ARM_FEATURE_DSP
70 #define __ARM_ARCH_7EM__ 1
71 #else
72 #define __ARM_ARCH_7M__ 1
73 #endif
74 #endif /* __ARM_ARCH */
75 #endif /* __ARM_ARCH_PROFILE == 'M' */
76 #endif
77
78 /* Alternativ core deduction for older ICCARM's */
79 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
80 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
81 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
82 #define __ARM_ARCH_6M__ 1
83 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
84 #define __ARM_ARCH_7M__ 1
85 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
86 #define __ARM_ARCH_7EM__ 1
87 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
88 #define __ARM_ARCH_8M_BASE__ 1
89 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
90 #define __ARM_ARCH_8M_MAIN__ 1
91 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
92 #define __ARM_ARCH_8M_MAIN__ 1
93 #else
94 #error "Unknown target."
95 #endif
96 #endif
97
98
99
100 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
101 #define __IAR_M0_FAMILY 1
102 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
103 #define __IAR_M0_FAMILY 1
104 #else
105 #define __IAR_M0_FAMILY 0
106 #endif
107
108
109 #ifndef __ASM
110 #define __ASM __asm
111 #endif
112
113 #ifndef __INLINE
114 #define __INLINE inline
115 #endif
116
117 #ifndef __NO_RETURN
118 #if __ICCARM_V8
119 #define __NO_RETURN __attribute__((__noreturn__))
120 #else
121 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
122 #endif
123 #endif
124
125 #ifndef __PACKED
126 #if __ICCARM_V8
127 #define __PACKED __attribute__((packed, aligned(1)))
128 #else
129 /* Needs IAR language extensions */
130 #define __PACKED __packed
131 #endif
132 #endif
133
134 #ifndef __PACKED_STRUCT
135 #if __ICCARM_V8
136 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
137 #else
138 /* Needs IAR language extensions */
139 #define __PACKED_STRUCT __packed struct
140 #endif
141 #endif
142
143 #ifndef __PACKED_UNION
144 #if __ICCARM_V8
145 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
146 #else
147 /* Needs IAR language extensions */
148 #define __PACKED_UNION __packed union
149 #endif
150 #endif
151
152 #ifndef __RESTRICT
153 #if __ICCARM_V8
154 #define __RESTRICT __restrict
155 #else
156 /* Needs IAR language extensions */
157 #define __RESTRICT restrict
158 #endif
159 #endif
160
161 #ifndef __STATIC_INLINE
162 #define __STATIC_INLINE static inline
163 #endif
164
165 #ifndef __FORCEINLINE
166 #define __FORCEINLINE _Pragma("inline=forced")
167 #endif
168
169 #ifndef __STATIC_FORCEINLINE
170 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
171 #endif
172
173 #ifndef __UNALIGNED_UINT16_READ
174 #pragma language=save
175 #pragma language=extended
__iar_uint16_read(void const * ptr)176 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
177 {
178 return *(__packed uint16_t *)(ptr);
179 }
180 #pragma language=restore
181 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
182 #endif
183
184
185 #ifndef __UNALIGNED_UINT16_WRITE
186 #pragma language=save
187 #pragma language=extended
__iar_uint16_write(void const * ptr,uint16_t val)188 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
189 {
190 *(__packed uint16_t *)(ptr) = val;;
191 }
192 #pragma language=restore
193 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
194 #endif
195
196 #ifndef __UNALIGNED_UINT32_READ
197 #pragma language=save
198 #pragma language=extended
__iar_uint32_read(void const * ptr)199 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
200 {
201 return *(__packed uint32_t *)(ptr);
202 }
203 #pragma language=restore
204 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
205 #endif
206
207 #ifndef __UNALIGNED_UINT32_WRITE
208 #pragma language=save
209 #pragma language=extended
__iar_uint32_write(void const * ptr,uint32_t val)210 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
211 {
212 *(__packed uint32_t *)(ptr) = val;;
213 }
214 #pragma language=restore
215 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
216 #endif
217
218 #ifndef __UNALIGNED_UINT32 /* deprecated */
219 #pragma language=save
220 #pragma language=extended
221 __packed struct __iar_u32
222 {
223 uint32_t v;
224 };
225 #pragma language=restore
226 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
227 #endif
228
229 #ifndef __USED
230 #if __ICCARM_V8
231 #define __USED __attribute__((used))
232 #else
233 #define __USED _Pragma("__root")
234 #endif
235 #endif
236
237 #ifndef __WEAK
238 #if __ICCARM_V8
239 #define __WEAK __attribute__((weak))
240 #else
241 #define __WEAK _Pragma("__weak")
242 #endif
243 #endif
244
245
246 #ifndef __ICCARM_INTRINSICS_VERSION__
247 #define __ICCARM_INTRINSICS_VERSION__ 0
248 #endif
249
250 #if __ICCARM_INTRINSICS_VERSION__ == 2
251
252 #if defined(__CLZ)
253 #undef __CLZ
254 #endif
255 #if defined(__REVSH)
256 #undef __REVSH
257 #endif
258 #if defined(__RBIT)
259 #undef __RBIT
260 #endif
261 #if defined(__SSAT)
262 #undef __SSAT
263 #endif
264 #if defined(__USAT)
265 #undef __USAT
266 #endif
267
268 #include "iccarm_builtin.h"
269
270 #define __disable_fault_irq __iar_builtin_disable_fiq
271 #define __disable_irq __iar_builtin_disable_interrupt
272 #define __enable_fault_irq __iar_builtin_enable_fiq
273 #define __enable_irq __iar_builtin_enable_interrupt
274 #define __arm_rsr __iar_builtin_rsr
275 #define __arm_wsr __iar_builtin_wsr
276
277
278 #define __get_APSR() (__arm_rsr("APSR"))
279 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
280 #define __get_CONTROL() (__arm_rsr("CONTROL"))
281 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
282
283 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
284 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
285 #define __get_FPSCR() (__arm_rsr("FPSCR"))
286 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
287 #else
288 #define __get_FPSCR() ( 0 )
289 #define __set_FPSCR(VALUE) ((void)VALUE)
290 #endif
291
292 #define __get_IPSR() (__arm_rsr("IPSR"))
293 #define __get_MSP() (__arm_rsr("MSP"))
294 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
295 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
296 // without main extensions, the non-secure MSPLIM is RAZ/WI
297 #define __get_MSPLIM() (0U)
298 #else
299 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
300 #endif
301 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
302 #define __get_PSP() (__arm_rsr("PSP"))
303
304 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
305 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
306 // without main extensions, the non-secure PSPLIM is RAZ/WI
307 #define __get_PSPLIM() (0U)
308 #else
309 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
310 #endif
311
312 #define __get_xPSR() (__arm_rsr("xPSR"))
313
314 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
315 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
316 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
317 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
318 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
319
320 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
321 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
322 // without main extensions, the non-secure MSPLIM is RAZ/WI
323 #define __set_MSPLIM(VALUE) ((void)(VALUE))
324 #else
325 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
326 #endif
327 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
328 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
329 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
330 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
331 // without main extensions, the non-secure PSPLIM is RAZ/WI
332 #define __set_PSPLIM(VALUE) ((void)(VALUE))
333 #else
334 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
335 #endif
336
337 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
338 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
339 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
340 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
341 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
342 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
343 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
344 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
345 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
346 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
347 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
348 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
349 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
350 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
351
352 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
353 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
354 // without main extensions, the non-secure PSPLIM is RAZ/WI
355 #define __TZ_get_PSPLIM_NS() (0U)
356 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
357 #else
358 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
359 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
360 #endif
361
362 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
363 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
364
365 #define __NOP __iar_builtin_no_operation
366
367 #define __CLZ __iar_builtin_CLZ
368 #define __CLREX __iar_builtin_CLREX
369
370 #define __DMB __iar_builtin_DMB
371 #define __DSB __iar_builtin_DSB
372 #define __ISB __iar_builtin_ISB
373
374 #define __LDREXB __iar_builtin_LDREXB
375 #define __LDREXH __iar_builtin_LDREXH
376 #define __LDREXW __iar_builtin_LDREX
377
378 #define __RBIT __iar_builtin_RBIT
379 #define __REV __iar_builtin_REV
380 #define __REV16 __iar_builtin_REV16
381
__REVSH(int16_t val)382 __IAR_FT int16_t __REVSH(int16_t val)
383 {
384 return (int16_t) __iar_builtin_REVSH(val);
385 }
386
387 #define __ROR __iar_builtin_ROR
388 #define __RRX __iar_builtin_RRX
389
390 #define __SEV __iar_builtin_SEV
391
392 #if !__IAR_M0_FAMILY
393 #define __SSAT __iar_builtin_SSAT
394 #endif
395
396 #define __STREXB __iar_builtin_STREXB
397 #define __STREXH __iar_builtin_STREXH
398 #define __STREXW __iar_builtin_STREX
399
400 #if !__IAR_M0_FAMILY
401 #define __USAT __iar_builtin_USAT
402 #endif
403
404 #define __WFE __iar_builtin_WFE
405 #define __WFI __iar_builtin_WFI
406
407 #if __ARM_MEDIA__
408 #define __SADD8 __iar_builtin_SADD8
409 #define __QADD8 __iar_builtin_QADD8
410 #define __SHADD8 __iar_builtin_SHADD8
411 #define __UADD8 __iar_builtin_UADD8
412 #define __UQADD8 __iar_builtin_UQADD8
413 #define __UHADD8 __iar_builtin_UHADD8
414 #define __SSUB8 __iar_builtin_SSUB8
415 #define __QSUB8 __iar_builtin_QSUB8
416 #define __SHSUB8 __iar_builtin_SHSUB8
417 #define __USUB8 __iar_builtin_USUB8
418 #define __UQSUB8 __iar_builtin_UQSUB8
419 #define __UHSUB8 __iar_builtin_UHSUB8
420 #define __SADD16 __iar_builtin_SADD16
421 #define __QADD16 __iar_builtin_QADD16
422 #define __SHADD16 __iar_builtin_SHADD16
423 #define __UADD16 __iar_builtin_UADD16
424 #define __UQADD16 __iar_builtin_UQADD16
425 #define __UHADD16 __iar_builtin_UHADD16
426 #define __SSUB16 __iar_builtin_SSUB16
427 #define __QSUB16 __iar_builtin_QSUB16
428 #define __SHSUB16 __iar_builtin_SHSUB16
429 #define __USUB16 __iar_builtin_USUB16
430 #define __UQSUB16 __iar_builtin_UQSUB16
431 #define __UHSUB16 __iar_builtin_UHSUB16
432 #define __SASX __iar_builtin_SASX
433 #define __QASX __iar_builtin_QASX
434 #define __SHASX __iar_builtin_SHASX
435 #define __UASX __iar_builtin_UASX
436 #define __UQASX __iar_builtin_UQASX
437 #define __UHASX __iar_builtin_UHASX
438 #define __SSAX __iar_builtin_SSAX
439 #define __QSAX __iar_builtin_QSAX
440 #define __SHSAX __iar_builtin_SHSAX
441 #define __USAX __iar_builtin_USAX
442 #define __UQSAX __iar_builtin_UQSAX
443 #define __UHSAX __iar_builtin_UHSAX
444 #define __USAD8 __iar_builtin_USAD8
445 #define __USADA8 __iar_builtin_USADA8
446 #define __SSAT16 __iar_builtin_SSAT16
447 #define __USAT16 __iar_builtin_USAT16
448 #define __UXTB16 __iar_builtin_UXTB16
449 #define __UXTAB16 __iar_builtin_UXTAB16
450 #define __SXTB16 __iar_builtin_SXTB16
451 #define __SXTAB16 __iar_builtin_SXTAB16
452 #define __SMUAD __iar_builtin_SMUAD
453 #define __SMUADX __iar_builtin_SMUADX
454 #define __SMMLA __iar_builtin_SMMLA
455 #define __SMLAD __iar_builtin_SMLAD
456 #define __SMLADX __iar_builtin_SMLADX
457 #define __SMLALD __iar_builtin_SMLALD
458 #define __SMLALDX __iar_builtin_SMLALDX
459 #define __SMUSD __iar_builtin_SMUSD
460 #define __SMUSDX __iar_builtin_SMUSDX
461 #define __SMLSD __iar_builtin_SMLSD
462 #define __SMLSDX __iar_builtin_SMLSDX
463 #define __SMLSLD __iar_builtin_SMLSLD
464 #define __SMLSLDX __iar_builtin_SMLSLDX
465 #define __SEL __iar_builtin_SEL
466 #define __QADD __iar_builtin_QADD
467 #define __QSUB __iar_builtin_QSUB
468 #define __PKHBT __iar_builtin_PKHBT
469 #define __PKHTB __iar_builtin_PKHTB
470 #endif
471
472 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
473
474 #if __IAR_M0_FAMILY
475 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
476 #define __CLZ __cmsis_iar_clz_not_active
477 #define __SSAT __cmsis_iar_ssat_not_active
478 #define __USAT __cmsis_iar_usat_not_active
479 #define __RBIT __cmsis_iar_rbit_not_active
480 #define __get_APSR __cmsis_iar_get_APSR_not_active
481 #endif
482
483
484 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
485 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
486 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
487 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
488 #endif
489
490 #ifdef __INTRINSICS_INCLUDED
491 #error intrinsics.h is already included previously!
492 #endif
493
494 #include <intrinsics.h>
495
496 #if __IAR_M0_FAMILY
497 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
498 #undef __CLZ
499 #undef __SSAT
500 #undef __USAT
501 #undef __RBIT
502 #undef __get_APSR
503
__CLZ(uint32_t data)504 __STATIC_INLINE uint8_t __CLZ(uint32_t data)
505 {
506 if (data == 0U)
507 {
508 return 32U;
509 }
510
511 uint32_t count = 0U;
512 uint32_t mask = 0x80000000U;
513
514 while ((data & mask) == 0U)
515 {
516 count += 1U;
517 mask = mask >> 1U;
518 }
519 return count;
520 }
521
__RBIT(uint32_t v)522 __STATIC_INLINE uint32_t __RBIT(uint32_t v)
523 {
524 uint8_t sc = 31U;
525 uint32_t r = v;
526 for (v >>= 1U; v; v >>= 1U)
527 {
528 r <<= 1U;
529 r |= v & 1U;
530 sc--;
531 }
532 return (r << sc);
533 }
534
__get_APSR(void)535 __STATIC_INLINE uint32_t __get_APSR(void)
536 {
537 uint32_t res;
538 __asm("MRS %0,APSR" : "=r"(res));
539 return res;
540 }
541
542 #endif
543
544 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
545 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
546 #undef __get_FPSCR
547 #undef __set_FPSCR
548 #define __get_FPSCR() (0)
549 #define __set_FPSCR(VALUE) ((void)VALUE)
550 #endif
551
552 #pragma diag_suppress=Pe940
553 #pragma diag_suppress=Pe177
554
555 #define __enable_irq __enable_interrupt
556 #define __disable_irq __disable_interrupt
557 #define __NOP __no_operation
558
559 #define __get_xPSR __get_PSR
560
561 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
562
__LDREXW(uint32_t volatile * ptr)563 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
564 {
565 return __LDREX((unsigned long *)ptr);
566 }
567
__STREXW(uint32_t value,uint32_t volatile * ptr)568 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
569 {
570 return __STREX(value, (unsigned long *)ptr);
571 }
572 #endif
573
574
575 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
576 #if (__CORTEX_M >= 0x03)
577
__RRX(uint32_t value)578 __IAR_FT uint32_t __RRX(uint32_t value)
579 {
580 uint32_t result;
581 __ASM("RRX %0, %1" : "=r"(result) : "r"(value) : "cc");
582 return (result);
583 }
584
__set_BASEPRI_MAX(uint32_t value)585 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
586 {
587 __asm volatile("MSR BASEPRI_MAX,%0"::"r"(value));
588 }
589
590
591 #define __enable_fault_irq __enable_fiq
592 #define __disable_fault_irq __disable_fiq
593
594
595 #endif /* (__CORTEX_M >= 0x03) */
596
__ROR(uint32_t op1,uint32_t op2)597 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
598 {
599 return (op1 >> op2) | (op1 << ((sizeof(op1) * 8) - op2));
600 }
601
602 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
603 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
604
__get_MSPLIM(void)605 __IAR_FT uint32_t __get_MSPLIM(void)
606 {
607 uint32_t res;
608 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
609 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
610 // without main extensions, the non-secure MSPLIM is RAZ/WI
611 res = 0U;
612 #else
613 __asm volatile("MRS %0,MSPLIM" : "=r"(res));
614 #endif
615 return res;
616 }
617
__set_MSPLIM(uint32_t value)618 __IAR_FT void __set_MSPLIM(uint32_t value)
619 {
620 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
621 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
622 // without main extensions, the non-secure MSPLIM is RAZ/WI
623 (void)value;
624 #else
625 __asm volatile("MSR MSPLIM,%0" :: "r"(value));
626 #endif
627 }
628
__get_PSPLIM(void)629 __IAR_FT uint32_t __get_PSPLIM(void)
630 {
631 uint32_t res;
632 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
633 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
634 // without main extensions, the non-secure PSPLIM is RAZ/WI
635 res = 0U;
636 #else
637 __asm volatile("MRS %0,PSPLIM" : "=r"(res));
638 #endif
639 return res;
640 }
641
__set_PSPLIM(uint32_t value)642 __IAR_FT void __set_PSPLIM(uint32_t value)
643 {
644 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
645 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
646 // without main extensions, the non-secure PSPLIM is RAZ/WI
647 (void)value;
648 #else
649 __asm volatile("MSR PSPLIM,%0" :: "r"(value));
650 #endif
651 }
652
__TZ_get_CONTROL_NS(void)653 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
654 {
655 uint32_t res;
656 __asm volatile("MRS %0,CONTROL_NS" : "=r"(res));
657 return res;
658 }
659
__TZ_set_CONTROL_NS(uint32_t value)660 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
661 {
662 __asm volatile("MSR CONTROL_NS,%0" :: "r"(value));
663 }
664
__TZ_get_PSP_NS(void)665 __IAR_FT uint32_t __TZ_get_PSP_NS(void)
666 {
667 uint32_t res;
668 __asm volatile("MRS %0,PSP_NS" : "=r"(res));
669 return res;
670 }
671
__TZ_set_PSP_NS(uint32_t value)672 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
673 {
674 __asm volatile("MSR PSP_NS,%0" :: "r"(value));
675 }
676
__TZ_get_MSP_NS(void)677 __IAR_FT uint32_t __TZ_get_MSP_NS(void)
678 {
679 uint32_t res;
680 __asm volatile("MRS %0,MSP_NS" : "=r"(res));
681 return res;
682 }
683
__TZ_set_MSP_NS(uint32_t value)684 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
685 {
686 __asm volatile("MSR MSP_NS,%0" :: "r"(value));
687 }
688
__TZ_get_SP_NS(void)689 __IAR_FT uint32_t __TZ_get_SP_NS(void)
690 {
691 uint32_t res;
692 __asm volatile("MRS %0,SP_NS" : "=r"(res));
693 return res;
694 }
__TZ_set_SP_NS(uint32_t value)695 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
696 {
697 __asm volatile("MSR SP_NS,%0" :: "r"(value));
698 }
699
__TZ_get_PRIMASK_NS(void)700 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
701 {
702 uint32_t res;
703 __asm volatile("MRS %0,PRIMASK_NS" : "=r"(res));
704 return res;
705 }
706
__TZ_set_PRIMASK_NS(uint32_t value)707 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
708 {
709 __asm volatile("MSR PRIMASK_NS,%0" :: "r"(value));
710 }
711
__TZ_get_BASEPRI_NS(void)712 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
713 {
714 uint32_t res;
715 __asm volatile("MRS %0,BASEPRI_NS" : "=r"(res));
716 return res;
717 }
718
__TZ_set_BASEPRI_NS(uint32_t value)719 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
720 {
721 __asm volatile("MSR BASEPRI_NS,%0" :: "r"(value));
722 }
723
__TZ_get_FAULTMASK_NS(void)724 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
725 {
726 uint32_t res;
727 __asm volatile("MRS %0,FAULTMASK_NS" : "=r"(res));
728 return res;
729 }
730
__TZ_set_FAULTMASK_NS(uint32_t value)731 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
732 {
733 __asm volatile("MSR FAULTMASK_NS,%0" :: "r"(value));
734 }
735
__TZ_get_PSPLIM_NS(void)736 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
737 {
738 uint32_t res;
739 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
740 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
741 // without main extensions, the non-secure PSPLIM is RAZ/WI
742 res = 0U;
743 #else
744 __asm volatile("MRS %0,PSPLIM_NS" : "=r"(res));
745 #endif
746 return res;
747 }
748
__TZ_set_PSPLIM_NS(uint32_t value)749 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
750 {
751 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
752 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
753 // without main extensions, the non-secure PSPLIM is RAZ/WI
754 (void)value;
755 #else
756 __asm volatile("MSR PSPLIM_NS,%0" :: "r"(value));
757 #endif
758 }
759
__TZ_get_MSPLIM_NS(void)760 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
761 {
762 uint32_t res;
763 __asm volatile("MRS %0,MSPLIM_NS" : "=r"(res));
764 return res;
765 }
766
__TZ_set_MSPLIM_NS(uint32_t value)767 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
768 {
769 __asm volatile("MSR MSPLIM_NS,%0" :: "r"(value));
770 }
771
772 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
773
774 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
775
776 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
777
778 #if __IAR_M0_FAMILY
__SSAT(int32_t val,uint32_t sat)779 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
780 {
781 if ((sat >= 1U) && (sat <= 32U))
782 {
783 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
784 const int32_t min = -1 - max ;
785 if (val > max)
786 {
787 return max;
788 }
789 else if (val < min)
790 {
791 return min;
792 }
793 }
794 return val;
795 }
796
__USAT(int32_t val,uint32_t sat)797 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
798 {
799 if (sat <= 31U)
800 {
801 const uint32_t max = ((1U << sat) - 1U);
802 if (val > (int32_t)max)
803 {
804 return max;
805 }
806 else if (val < 0)
807 {
808 return 0U;
809 }
810 }
811 return (uint32_t)val;
812 }
813 #endif
814
815 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
816
__LDRBT(volatile uint8_t * addr)817 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
818 {
819 uint32_t res;
820 __ASM("LDRBT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
821 return ((uint8_t)res);
822 }
823
__LDRHT(volatile uint16_t * addr)824 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
825 {
826 uint32_t res;
827 __ASM("LDRHT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
828 return ((uint16_t)res);
829 }
830
__LDRT(volatile uint32_t * addr)831 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
832 {
833 uint32_t res;
834 __ASM("LDRT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
835 return res;
836 }
837
__STRBT(uint8_t value,volatile uint8_t * addr)838 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
839 {
840 __ASM("STRBT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory");
841 }
842
__STRHT(uint16_t value,volatile uint16_t * addr)843 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
844 {
845 __ASM("STRHT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory");
846 }
847
__STRT(uint32_t value,volatile uint32_t * addr)848 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
849 {
850 __ASM("STRT %1, [%0]" : : "r"(addr), "r"(value) : "memory");
851 }
852
853 #endif /* (__CORTEX_M >= 0x03) */
854
855 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
856 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
857
858
__LDAB(volatile uint8_t * ptr)859 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
860 {
861 uint32_t res;
862 __ASM volatile("LDAB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
863 return ((uint8_t)res);
864 }
865
__LDAH(volatile uint16_t * ptr)866 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
867 {
868 uint32_t res;
869 __ASM volatile("LDAH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
870 return ((uint16_t)res);
871 }
872
__LDA(volatile uint32_t * ptr)873 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
874 {
875 uint32_t res;
876 __ASM volatile("LDA %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
877 return res;
878 }
879
__STLB(uint8_t value,volatile uint8_t * ptr)880 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
881 {
882 __ASM volatile("STLB %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
883 }
884
__STLH(uint16_t value,volatile uint16_t * ptr)885 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
886 {
887 __ASM volatile("STLH %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
888 }
889
__STL(uint32_t value,volatile uint32_t * ptr)890 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
891 {
892 __ASM volatile("STL %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
893 }
894
__LDAEXB(volatile uint8_t * ptr)895 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
896 {
897 uint32_t res;
898 __ASM volatile("LDAEXB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
899 return ((uint8_t)res);
900 }
901
__LDAEXH(volatile uint16_t * ptr)902 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
903 {
904 uint32_t res;
905 __ASM volatile("LDAEXH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
906 return ((uint16_t)res);
907 }
908
__LDAEX(volatile uint32_t * ptr)909 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
910 {
911 uint32_t res;
912 __ASM volatile("LDAEX %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
913 return res;
914 }
915
__STLEXB(uint8_t value,volatile uint8_t * ptr)916 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
917 {
918 uint32_t res;
919 __ASM volatile("STLEXB %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
920 return res;
921 }
922
__STLEXH(uint16_t value,volatile uint16_t * ptr)923 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
924 {
925 uint32_t res;
926 __ASM volatile("STLEXH %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
927 return res;
928 }
929
__STLEX(uint32_t value,volatile uint32_t * ptr)930 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
931 {
932 uint32_t res;
933 __ASM volatile("STLEX %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
934 return res;
935 }
936
937 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
938
939 #undef __IAR_FT
940 #undef __IAR_M0_FAMILY
941 #undef __ICCARM_V8
942
943 #pragma diag_default=Pe940
944 #pragma diag_default=Pe177
945
946 #endif /* __CMSIS_ICCARM_H__ */
947