1 /*
2 * Copyright (c) 2001-2002 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
21
22
23 /* definitions used for the EHCI driver */
24 #include <usb_gen_hcd.h>
25 #include <usb_os_platform.h>
26 #include <ehci_def.h>
27 #include <hal_osal.h>
28
29 #define __hc32 uint32_t
30
31 #define ehci_readl(a, addr) readl(addr)
32 #define ehci_writel(a, val, addr) writel(val, addr)
33
34 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
35 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
36
37 struct ehci_stats {
38 /* irq usage */
39 unsigned long normal;
40 unsigned long error;
41 unsigned long iaa;
42 unsigned long lost_iaa;
43
44 /* termination of urbs from core */
45 unsigned long complete;
46 unsigned long unlink;
47 };
48
49 /*
50 * Scheduling and budgeting information for periodic transfers, for both
51 * high-speed devices and full/low-speed devices lying behind a TT.
52 */
53 struct ehci_per_sched {
54 //struct usb_device *udev; /* access to the TT */
55 struct usb_host_virt_dev *udev; /* access to the TT */
56 //struct usb_host_endpoint *ep;
57 struct usb_host_virt_endpoint *ep;
58 struct list_head ps_list; /* node on ehci_tt's ps_list */
59 u16 tt_usecs; /* time on the FS/LS bus */
60 u16 cs_mask; /* C-mask and S-mask bytes */
61 u16 period; /* actual period in frames */
62 u16 phase; /* actual phase, frame part */
63 u8 bw_phase; /* same, for bandwidth
64 reservation */
65 u8 phase_uf; /* uframe part of the phase */
66 u8 usecs, c_usecs; /* times on the HS bus */
67 u8 bw_uperiod; /* period in microframes, for
68 bandwidth reservation */
69 u8 bw_period; /* same, in frames */
70 };
71 #define NO_FRAME 29999 /* frame not assigned yet */
72
73 /* ehci_hcd->lock guards shared data against other CPUs:
74 * ehci_hcd: async, unlink, periodic (and shadow), ...
75 * usb_host_endpoint: hcpriv
76 * ehci_qh: qh_next, qtd_list
77 * ehci_qtd: qtd_list
78 *
79 * Also, hold this lock when talking to HC registers or
80 * when updating hw_* fields in shared qh/qtd/... structures.
81 */
82
83 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
84
85 /*
86 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
87 * controller may be doing DMA. Lower values mean there's no DMA.
88 */
89 enum ehci_rh_state {
90 EHCI_RH_HALTED,
91 EHCI_RH_SUSPENDED,
92 EHCI_RH_RUNNING,
93 EHCI_RH_STOPPING
94 };
95
96 /*
97 * Timer events, ordered by increasing delay length.
98 * Always update event_delays_ns[] and event_handlers[] (defined in
99 * ehci-timer.c) in parallel with this list.
100 */
101 enum ehci_hrtimer_event {
102 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
103 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
104 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
105 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
106 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
107 EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */
108 EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
109 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
110 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
111 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
112 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
113 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
114 EHCI_HRTIMER_NUM_EVENTS /* Must come last */
115 };
116 #define EHCI_HRTIMER_NO_EVENT 99
117
118 struct ehci_hcd { /* one per controller */
119 /* timing support */
120 enum ehci_hrtimer_event next_hrtimer_event;
121 unsigned enabled_hrtimer_events;
122 unsigned long hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
123 osal_timer_t hrtimer;
124
125 int PSS_poll_count;
126 int ASS_poll_count;
127 int died_poll_count;
128
129 /* glue to PCI and HCD framework */
130 struct ehci_caps *caps;
131 struct ehci_regs *regs;
132 //struct ehci_dbg_port __iomem *debug;
133
134 uint32_t hcs_params; /* cached register copy */
135 hal_spinlock_t lock;
136 enum ehci_rh_state rh_state;
137
138 /* general schedule support */
139 bool scanning:1;
140 bool need_rescan:1;
141 bool intr_unlinking:1;
142 bool iaa_in_progress:1;
143 bool async_unlinking:1;
144 bool shutdown:1;
145 struct ehci_qh *qh_scan_next;
146
147 /* async schedule support */
148 struct ehci_qh *async;
149 struct ehci_qh *dummy; /* For AMD quirk use */
150 struct list_head async_unlink;
151 struct list_head async_idle;
152 struct list_head wait_free_list; /* akira 20202020 */
153 unsigned async_unlink_cycle;
154 unsigned async_count; /* async activity count */
155 uint32_t old_current; /* Test for QH becoming */
156 uint32_t old_token; /* inactive during unlink */
157
158 /* periodic schedule support */
159 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
160 unsigned periodic_size;
161 uint32_t *periodic; /* hw periodic table */
162 uint32_t periodic_dma;
163 struct list_head intr_qh_list;
164 unsigned i_thresh; /* uframes HC might cache */
165
166 union ehci_shadow *pshadow; /* mirror hw periodic table */
167 struct list_head intr_unlink_wait;
168 struct list_head intr_unlink;
169 unsigned intr_unlink_wait_cycle;
170 unsigned intr_unlink_cycle;
171 unsigned now_frame; /* frame from HC hardware */
172 unsigned last_iso_frame; /* last frame scanned for iso */
173 unsigned intr_count; /* intr activity count */
174 unsigned isoc_count; /* isoc activity count */
175 unsigned periodic_count; /* periodic activity count */
176 unsigned uframe_periodic_max; /* max periodic time per uframe */
177
178
179 /* list of itds & sitds completed while now_frame was still active */
180 struct list_head cached_itd_list;
181 struct ehci_itd *last_itd_to_free;
182 struct list_head cached_sitd_list;
183 struct ehci_sitd *last_sitd_to_free;
184
185 /* per root hub port */
186 unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
187
188 /* bit vectors (one bit per port) */
189 unsigned long bus_suspended; /* which ports were
190 already suspended at the start of a bus suspend */
191 unsigned long companion_ports; /* which ports are
192 dedicated to the companion controller */
193 unsigned long owned_ports; /* which ports are
194 owned by the companion during a bus suspend */
195 unsigned long port_c_suspend; /* which ports have
196 the change-suspend feature turned on */
197 unsigned long suspended_ports; /* which ports are
198 suspended */
199 unsigned long resuming_ports; /* which ports have
200 started to resume */
201
202 /* per-HC memory pools (could be per-bus, but ...) */
203 struct dma_pool *qh_pool; /* qh per active urb */
204 struct dma_pool *qtd_pool; /* one or more per qh */
205 struct dma_pool *itd_pool; /* itd per iso urb */
206 struct dma_pool *sitd_pool; /* sitd per split iso urb */
207
208 unsigned random_frame;
209 uint32_t command;
210
211 /* SILICON QUIRKS */
212 unsigned no_selective_suspend:1;
213 unsigned has_fsl_port_bug:1; /* FreeScale */
214 unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */
215 unsigned big_endian_mmio:1;
216 unsigned big_endian_desc:1;
217 unsigned big_endian_capbase:1;
218 unsigned has_amcc_usb23:1;
219 unsigned need_io_watchdog:1;
220 unsigned amd_pll_fix:1;
221 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
222 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
223 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
224 unsigned need_oc_pp_cycle:1; /* MPC834X port power */
225 unsigned imx28_write_fix:1; /* For Freescale i.MX28 */
226
227 /* required for usb32 quirk */
228 #define OHCI_CTRL_HCFS (3 << 6)
229 #define OHCI_USB_OPER (2 << 6)
230 #define OHCI_USB_SUSPEND (3 << 6)
231
232 #define OHCI_HCCTRL_OFFSET 0x4
233 #define OHCI_HCCTRL_LEN 0x4
234 uint32_t *ohci_hcctrl_reg;
235 unsigned has_hostpc:1;
236 unsigned has_tdi_phy_lpm:1;
237 unsigned has_ppcd:1; /* support per-port change bits */
238 uint8_t sbrn; /* packed release number */
239
240 /* irq statistics */
241 #ifdef EHCI_STATS
242 struct ehci_stats stats;
243 # define COUNT(x) ((x)++)
244 #else
245 # define COUNT(x)
246 #endif
247
248 /* debug files */
249 #ifdef CONFIG_DYNAMIC_DEBUG
250 struct dentry *debug_dir;
251 #endif
252
253 /* bandwidth usage */
254 #define EHCI_BANDWIDTH_SIZE 64
255 #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
256 u8 bandwidth[EHCI_BANDWIDTH_SIZE];
257 /* us allocated per uframe */
258 u8 tt_budget[EHCI_BANDWIDTH_SIZE];
259 /* us budgeted per uframe */
260 struct list_head tt_list;
261
262 /* platform-specific data -- must come last */
263 unsigned long priv[0];
264 };
265
266 /* convert between an HCD pointer and the corresponding EHCI_HCD */
267 #if 0
268 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
269 {
270 return (struct ehci_hcd *) (hcd->hcd_priv);
271 }
272 #endif
273
ehci_to_hcd(struct ehci_hcd * ehci)274 static inline struct hc_gen_dev *ehci_to_hcd(struct ehci_hcd *ehci)
275 {
276 return container_of((void *) ehci, struct hc_gen_dev, hcd_priv);
277 }
hcd_to_ehci(struct hc_gen_dev * hcd)278 static inline struct ehci_hcd *hcd_to_ehci(struct hc_gen_dev *hcd)
279 {
280 return (struct ehci_hcd *) (hcd->hcd_priv);
281 }
282
283 /*-------------------------------------------------------------------------*/
284
285 //#include <linux/usb/ehci_def.h>
286
287 /*-------------------------------------------------------------------------*/
288
289 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
290
291 /*
292 * EHCI Specification 0.95 Section 3.5
293 * QTD: describe data transfer components (buffer, direction, ...)
294 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
295 *
296 * These are associated only with "QH" (Queue Head) structures,
297 * used with control, bulk, and interrupt transfers.
298 */
299 struct ehci_qtd {
300 /* first part defined by EHCI spec */
301 uint32_t hw_next; /* see EHCI 3.5.1 */
302 uint32_t hw_alt_next; /* see EHCI 3.5.2 */
303 uint32_t hw_token; /* see EHCI 3.5.3 */
304 #define QTD_TOGGLE (1 << 31) /* data toggle */
305 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
306 #define QTD_IOC (1 << 15) /* interrupt on complete */
307 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
308 #define QTD_PID(tok) (((tok)>>8) & 0x3)
309 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
310 #define QTD_STS_HALT (1 << 6) /* halted on error */
311 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
312 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
313 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
314 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
315 #define QTD_STS_STS (1 << 1) /* split transaction state */
316 #define QTD_STS_PING (1 << 0) /* issue PING? */
317
318 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
319 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
320 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
321
322 uint32_t hw_buf[5]; /* see EHCI 3.5.4 */
323 uint32_t hw_buf_hi[5]; /* Appendix B */
324
325 /* the rest is HCD-private */
326 dma_addr_t qtd_dma; /* qtd address */
327 struct list_head qtd_list; /* sw qtd list */
328 struct urb *urb; /* qtd's urb */
329 size_t length; /* length of buffer */
330 } __aligned(32);
331
332 /* mask NakCnt+T in qh->hw_alt_next */
333 #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f)
334
335 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
336
337 /*-------------------------------------------------------------------------*/
338
339 /* type tag from {qh,itd,sitd,fstn}->hw_next */
340 #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
341
342 /*
343 * Now the following defines are not converted using the
344 * cpu_to_le32() macro anymore, since we have to support
345 * "dynamic" switching between be and le support, so that the driver
346 * can be used on one system with SoC EHCI controller using big-endian
347 * descriptors as well as a normal little-endian PCI EHCI controller.
348 */
349 /* values for that type tag */
350 #define Q_TYPE_ITD (0 << 1)
351 #define Q_TYPE_QH (1 << 1)
352 #define Q_TYPE_SITD (2 << 1)
353 #define Q_TYPE_FSTN (3 << 1)
354
355 /* next async queue entry, or pointer to interrupt/periodic QH */
356 #define QH_NEXT(ehci, dma) \
357 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
358
359 /* for periodic/async schedules and qtd lists, mark end of list */
360 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
361
362 /*
363 * Entries in periodic shadow table are pointers to one of four kinds
364 * of data structure. That's dictated by the hardware; a type tag is
365 * encoded in the low bits of the hardware's periodic schedule. Use
366 * Q_NEXT_TYPE to get the tag.
367 *
368 * For entries in the async schedule, the type tag always says "qh".
369 */
370 union ehci_shadow {
371 struct ehci_qh *qh; /* Q_TYPE_QH */
372 struct ehci_itd *itd; /* Q_TYPE_ITD */
373 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
374 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
375 uint32_t *hw_next; /* (all types) */
376 void *ptr;
377 };
378
379 /*-------------------------------------------------------------------------*/
380
381 /*
382 * EHCI Specification 0.95 Section 3.6
383 * QH: describes control/bulk/interrupt endpoints
384 * See Fig 3-7 "Queue Head Structure Layout".
385 *
386 * These appear in both the async and (for interrupt) periodic schedules.
387 */
388
389 /* first part defined by EHCI spec */
390 struct ehci_qh_hw {
391 uint32_t hw_next; /* see EHCI 3.6.1 */
392 uint32_t hw_info1; /* see EHCI 3.6.2 */
393 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
394 #define QH_HEAD (1 << 15) /* Head of async reclamation list */
395 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
396 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
397 #define QH_LOW_SPEED (1 << 12)
398 #define QH_FULL_SPEED (0 << 12)
399 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
400 uint32_t hw_info2; /* see EHCI 3.6.2 */
401 #define QH_SMASK 0x000000ff
402 #define QH_CMASK 0x0000ff00
403 #define QH_HUBADDR 0x007f0000
404 #define QH_HUBPORT 0x3f800000
405 #define QH_MULT 0xc0000000
406 uint32_t hw_current; /* qtd list - see EHCI 3.6.4 */
407
408 /* qtd overlay (hardware parts of a struct ehci_qtd) */
409 uint32_t hw_qtd_next;
410 uint32_t hw_alt_next;
411 uint32_t hw_token;
412 uint32_t hw_buf[5];
413 uint32_t hw_buf_hi[5];
414 } __aligned(32);
415
416 struct ehci_qh {
417 struct ehci_qh_hw *hw; /* Must come first */
418 /* the rest is HCD-private */
419 dma_addr_t qh_dma; /* address of qh */
420 union ehci_shadow qh_next; /* ptr to qh; or periodic */
421 struct list_head qtd_list; /* sw qtd list */
422 struct list_head intr_node; /* list of intr QHs */
423 struct ehci_qtd *dummy;
424 struct list_head unlink_node;
425 struct ehci_per_sched ps; /* scheduling info */
426
427 unsigned unlink_cycle;
428
429 u8 qh_state;
430 #define QH_STATE_LINKED 1 /* HC sees this */
431 #define QH_STATE_UNLINK 2 /* HC may still see this */
432 #define QH_STATE_IDLE 3 /* HC doesn't see this */
433 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
434 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
435
436 u8 xacterrs; /* XactErr retry counter */
437 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
438
439 u8 unlink_reason;
440 #define QH_UNLINK_HALTED 0x01 /* Halt flag is set */
441 #define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */
442 #define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */
443 #define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */
444 #define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */
445 #define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */
446
447 u8 gap_uf; /* uframes split/csplit gap */
448
449 unsigned is_out:1; /* bulk or intr OUT */
450 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
451 unsigned dequeue_during_giveback:1;
452 unsigned should_be_inactive:1;
453 };
454
455 /*-------------------------------------------------------------------------*/
456
457 /* description of one iso transaction (up to 3 KB data if highspeed) */
458 struct ehci_iso_packet {
459 /* These will be copied to iTD when scheduling */
460 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
461 uint32_t transaction; /* itd->hw_transaction[i] |= */
462 u8 cross; /* buf crosses pages */
463 /* for full speed OUT splits */
464 u32 buf1;
465 };
466
467 /* temporary schedule data for packets from iso urbs (both speeds)
468 * each packet is one logical usb transaction to the device (not TT),
469 * beginning at stream->next_uframe
470 */
471 struct ehci_iso_sched {
472 struct list_head td_list;
473 unsigned span;
474 unsigned first_packet;
475 struct ehci_iso_packet packet[0];
476 };
477
478 /*
479 * ehci_iso_stream - groups all (s)itds for this endpoint.
480 * acts like a qh would, if EHCI had them for ISO.
481 */
482 struct ehci_iso_stream {
483 /* first field matches ehci_hq, but is NULL */
484 struct ehci_qh_hw *hw;
485
486 u8 bEndpointAddress;
487 u8 highspeed;
488 struct list_head td_list; /* queued itds/sitds */
489 struct list_head free_list; /* list of unused itds/sitds */
490
491 /* output of (re)scheduling */
492 struct ehci_per_sched ps; /* scheduling info */
493 unsigned next_uframe;
494 uint32_t splits;
495
496 /* the rest is derived from the endpoint descriptor,
497 * including the extra info for hw_bufp[0..2]
498 */
499 u16 uperiod; /* period in uframes */
500 u16 maxp;
501 unsigned bandwidth;
502
503 /* This is used to initialize iTD's hw_bufp fields */
504 uint32_t buf0;
505 uint32_t buf1;
506 uint32_t buf2;
507
508 /* this is used to initialize sITD's tt info */
509 uint32_t address;
510 };
511
512 /*-------------------------------------------------------------------------*/
513
514 /*
515 * EHCI Specification 0.95 Section 3.3
516 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
517 *
518 * Schedule records for high speed iso xfers
519 */
520 struct ehci_itd {
521 /* first part defined by EHCI spec */
522 uint32_t hw_next; /* see EHCI 3.3.1 */
523 uint32_t hw_transaction[8]; /* see EHCI 3.3.2 */
524 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
525 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
526 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
527 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
528 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
529 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
530
531 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
532
533 uint32_t hw_bufp[7]; /* see EHCI 3.3.3 */
534 uint32_t hw_bufp_hi[7]; /* Appendix B */
535
536 /* the rest is HCD-private */
537 uint32_t itd_dma; /* for this itd */
538 union ehci_shadow itd_next; /* ptr to periodic q entry */
539
540 struct urb *urb;
541 struct ehci_iso_stream *stream; /* endpoint's queue */
542 struct list_head itd_list; /* list of stream's itds */
543
544 /* any/all hw_transactions here may be used by that urb */
545 unsigned frame; /* where scheduled */
546 unsigned pg;
547 unsigned index[8]; /* in urb->iso_frame_desc */
548 } __aligned(32);
549
550 /*-------------------------------------------------------------------------*/
551
552 /*
553 * EHCI Specification 0.95 Section 3.4
554 * siTD, aka split-transaction isochronous Transfer Descriptor
555 * ... describe full speed iso xfers through TT in hubs
556 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
557 */
558 struct ehci_sitd {
559 /* first part defined by EHCI spec */
560 uint32_t hw_next;
561 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
562 uint32_t hw_fullspeed_ep; /* EHCI table 3-9 */
563 uint32_t hw_uframe; /* EHCI table 3-10 */
564 uint32_t hw_results; /* EHCI table 3-11 */
565 #define SITD_IOC (1 << 31) /* interrupt on completion */
566 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
567 #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff)
568 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
569 #define SITD_STS_ERR (1 << 6) /* error from TT */
570 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
571 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
572 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
573 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
574 #define SITD_STS_STS (1 << 1) /* split transaction state */
575
576 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
577
578 uint32_t hw_buf[2]; /* EHCI table 3-12 */
579 uint32_t hw_backpointer; /* EHCI table 3-13 */
580 uint32_t hw_buf_hi[2]; /* Appendix B */
581
582 /* the rest is HCD-private */
583 uint32_t sitd_dma;
584 union ehci_shadow sitd_next; /* ptr to periodic q entry */
585
586 struct urb *urb;
587 struct ehci_iso_stream *stream; /* endpoint's queue */
588 struct list_head sitd_list; /* list of stream's sitds */
589 unsigned frame;
590 unsigned index;
591 } __aligned(32);
592
593 /*-------------------------------------------------------------------------*/
594
595 /*
596 * EHCI Specification 0.96 Section 3.7
597 * Periodic Frame Span Traversal Node (FSTN)
598 *
599 * Manages split interrupt transactions (using TT) that span frame boundaries
600 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
601 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
602 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
603 */
604 struct ehci_fstn {
605 uint32_t hw_next; /* any periodic q entry */
606 uint32_t hw_prev; /* qh or EHCI_LIST_END */
607
608 /* the rest is HCD-private */
609 uint32_t fstn_dma;
610 union ehci_shadow fstn_next; /* ptr to periodic q entry */
611 } __aligned(32);
612
613 /*-------------------------------------------------------------------------*/
614
615 /*
616 * USB-2.0 Specification Sections 11.14 and 11.18
617 * Scheduling and budgeting split transactions using TTs
618 *
619 * A hub can have a single TT for all its ports, or multiple TTs (one for each
620 * port). The bandwidth and budgeting information for the full/low-speed bus
621 * below each TT is self-contained and independent of the other TTs or the
622 * high-speed bus.
623 *
624 * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
625 * to an interrupt or isochronous endpoint for each frame. "Budget" refers to
626 * the best-case estimate of the number of full-speed bytes allocated to an
627 * endpoint for each microframe within an allocated frame.
628 *
629 * Removal of an endpoint invalidates a TT's budget. Instead of trying to
630 * keep an up-to-date record, we recompute the budget when it is needed.
631 */
632
633 struct ehci_tt {
634 u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
635
636 struct list_head tt_list; /* List of all ehci_tt's */
637 struct list_head ps_list; /* Items using this TT */
638 struct usb_tt *usb_tt;
639 int tt_port; /* TT port number */
640 };
641
642 /*-------------------------------------------------------------------------*/
643
644 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
645
646 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
647 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
648
649 #define ehci_prepare_ports_for_controller_resume(ehci) \
650 ehci_adjust_port_wakeup_flags(ehci, false, false)
651
652 //#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
653 //static inline unsigned int
654 //ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
655 //{
656 // if (ehci_is_TDI(ehci)) {
657 // switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
658 // case 0:
659 // return 0;
660 // case 1:
661 // return USB_PORT_STAT_LOW_SPEED;
662 // case 2:
663 // default:
664 // return USB_PORT_STAT_HIGH_SPEED;
665 // }
666 // }
667 // return USB_PORT_STAT_HIGH_SPEED;
668 //}
669 #define ehci_is_TDI(e) (0)
670 //
671 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
672 //#endif
673 /*-------------------------------------------------------------------------*/
674
675 #define ehci_has_fsl_portno_bug(e) (0)
676
677 #define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */
678
679 #define ehci_has_fsl_hs_errata(e) (0)
680 /*
681 * While most USB host controllers implement their registers in
682 * little-endian format, a minority (celleb companion chip) implement
683 * them in big endian format.
684 *
685 * This attempts to support either format at compile time without a
686 * runtime penalty, or both formats with the additional overhead
687 * of checking a flag bit.
688 *
689 * ehci_big_endian_capbase is a special quirk for controllers that
690 * implement the HC capability registers as separate registers and not
691 * as fields of a 32-bit register.
692 */
693
694 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
695 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
696 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
697 #else
698 #define ehci_big_endian_mmio(e) 0
699 #define ehci_big_endian_capbase(e) 0
700 #endif
701
702 /*
703 * Big-endian read/write functions are arch-specific.
704 * Other arches can be added if/when they're needed.
705 */
706 //#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
707 //#define readl_be(addr) __raw_readl((__force unsigned *)addr)
708 //#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
709 //#endif
710 //
711 //static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
712 // __u32 *regs)
713 //{
714 // return readl(regs);
715 //}
716 //
717 //#ifdef CONFIG_SOC_IMX28
718 //static inline void imx28_ehci_writel(const unsigned int val,
719 // volatile __u32 __iomem *addr)
720 //{
721 // __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
722 //}
723 //#else
724 //static inline void imx28_ehci_writel(const unsigned int val,
725 // volatile __u32 __iomem *addr)
726 //{
727 //}
728 //#endif
729 //static inline void ehci_writel(const struct ehci_hcd *ehci,
730 // const unsigned int val, __u32 __iomem *regs)
731 //{
732 //#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
733 // ehci_big_endian_mmio(ehci) ?
734 // writel_be(val, regs) :
735 // writel(val, regs);
736 //#else
737 // if (ehci->imx28_write_fix)
738 // imx28_ehci_writel(val, regs);
739 // else
740 // writel(val, regs);
741 //#endif
742 //}
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)743 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
744 { }
745
746 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)747 static inline uint32_t cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
748 {
749 return cpu_to_le32(x);
750 }
751
752 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const uint32_t x)753 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const uint32_t x)
754 {
755 return le32_to_cpu(x);
756 }
757
hc32_to_cpup(const struct ehci_hcd * ehci,const uint32_t * x)758 static inline uint32_t hc32_to_cpup(const struct ehci_hcd *ehci, const uint32_t *x)
759 {
760 return le32_to_cpup(x);
761 }
762
763
764 #define ehci_dbg(fmt, args...) \
765 hal_log_debug(fmt, ## args)
766 #define ehci_err(fmt, args...) \
767 hal_log_err(fmt, ## args)
768 #define ehci_info(fmt, args...) \
769 hal_log_info(fmt, ## args)
770 #define ehci_warn(fmt, args...) \
771 hal_log_warn(fmt, ## args)
772 /*-------------------------------------------------------------------------*/
773 /*
774 #define ehci_dbg(ehci, fmt, args...) \
775 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
776 #define ehci_err(ehci, fmt, args...) \
777 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
778 #define ehci_info(ehci, fmt, args...) \
779 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
780 #define ehci_warn(ehci, fmt, args...) \
781 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
782 */
783 /*-------------------------------------------------------------------------*/
784
785 /* Declarations of things exported for use by ehci platform drivers */
786
787 struct ehci_driver_overrides {
788 size_t extra_priv_size;
789 int (*reset)(struct hc_gen_dev *hcd);
790 int (*port_power)(struct hc_gen_dev *hcd,
791 int portnum, bool enable);
792 };
793
794 extern void ehci_init_driver(struct hc_driver *drv,
795 const struct ehci_driver_overrides *over);
796 extern int ehci_setup(struct hc_gen_dev *hcd);
797 extern int ehci_handshake(struct ehci_hcd *ehci, u32 *ptr,
798 u32 mask, u32 done, int usec);
799 extern int ehci_reset(struct ehci_hcd *ehci);
800
801 extern int ehci_suspend(struct hc_gen_dev *hcd, bool do_wakeup);
802 extern int ehci_resume(struct hc_gen_dev *hcd, bool force_reset);
803 extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
804 bool suspending, bool do_wakeup);
805
806 extern int ehci_hub_control(struct hc_gen_dev *hcd, u16 typeReq, u16 wValue,
807 u16 wIndex, char *buf, u16 wLength);
808
809 void ehci_stop (struct hc_gen_dev *hcd);
810 int ehci_init(struct hc_gen_dev *hcd);
811 int ehci_halt (struct ehci_hcd *ehci);
812 void ehci_work (struct ehci_hcd *ehci);
813 int ehci_run (struct hc_gen_dev *hcd);
814 int ehci_urb_enqueue (struct hc_gen_dev *hcd, struct urb *urb, unsigned mem_flags);
815 int ehci_urb_dequeue(struct hc_gen_dev *hcd, struct urb *urb);
816 int ehci_get_frame (struct hc_gen_dev *hcd);
817 void ehci_endpoint_disable (struct hc_gen_dev *hcd, struct usb_host_virt_endpoint *ep);
818 int ehci_hub_status_data (struct hc_gen_dev *hcd, char *buf);
819 int ehci_bus_suspend (struct hc_gen_dev *hcd);
820 int ehci_bus_resume (struct hc_gen_dev *hcd);
821 irqreturn_t ehci_irq_handler (int dummy, void *dev);
822
823 int sunxi_ehci_hcd_init(int hci_num);
824 int sunxi_ehci_hcd_deinit(int hci_num);
825
826 #endif /* __LINUX_EHCI_HCD_H */
827