1 //########################################################################### 2 // 3 // FILE: F2837xD_flash.h 4 // 5 // TITLE: FLASH Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_FLASH_H__ 44 #define __F2837xD_FLASH_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // FLASH Individual Register Bit Definitions: 53 54 struct FRDCNTL_BITS { // bits description 55 Uint16 rsvd1:8; // 7:0 Reserved 56 Uint16 RWAIT:4; // 11:8 Random Read Waitstate 57 Uint16 rsvd2:4; // 15:12 Reserved 58 Uint16 rsvd3:16; // 31:16 Reserved 59 }; 60 61 union FRDCNTL_REG { 62 Uint32 all; 63 struct FRDCNTL_BITS bit; 64 }; 65 66 struct FBAC_BITS { // bits description 67 Uint16 VREADST:8; // 7:0 VREAD Setup Time Count 68 Uint16 rsvd1:8; // 15:8 Reserved 69 Uint16 rsvd2:16; // 31:16 Reserved 70 }; 71 72 union FBAC_REG { 73 Uint32 all; 74 struct FBAC_BITS bit; 75 }; 76 77 struct FBFALLBACK_BITS { // bits description 78 Uint16 BNKPWR0:2; // 1:0 Bank Power Mode 79 Uint16 rsvd1:14; // 15:2 Reserved 80 Uint16 rsvd2:16; // 31:16 Reserved 81 }; 82 83 union FBFALLBACK_REG { 84 Uint32 all; 85 struct FBFALLBACK_BITS bit; 86 }; 87 88 struct FBPRDY_BITS { // bits description 89 Uint16 BANKRDY:1; // 0 Flash Bank Active Power State 90 Uint16 rsvd1:14; // 14:1 Reserved 91 Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode 92 Uint16 rsvd2:16; // 31:16 Reserved 93 }; 94 95 union FBPRDY_REG { 96 Uint32 all; 97 struct FBPRDY_BITS bit; 98 }; 99 100 struct FPAC1_BITS { // bits description 101 Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode 102 Uint16 rsvd1:15; // 15:1 Reserved 103 Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count 104 Uint16 rsvd2:4; // 31:28 Reserved 105 }; 106 107 union FPAC1_REG { 108 Uint32 all; 109 struct FPAC1_BITS bit; 110 }; 111 112 struct FMSTAT_BITS { // bits description 113 Uint16 rsvd1:1; // 0 Reserved 114 Uint16 rsvd2:1; // 1 Reserved 115 Uint16 rsvd3:1; // 2 Reserved 116 Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status 117 Uint16 CSTAT:1; // 4 Command Fail Status 118 Uint16 INVDAT:1; // 5 Invalid Data 119 Uint16 PGM:1; // 6 Program Operation Status 120 Uint16 ERS:1; // 7 Erase Operation Status 121 Uint16 BUSY:1; // 8 Busy Bit 122 Uint16 rsvd4:1; // 9 Reserved 123 Uint16 EV:1; // 10 Erase Verify Status 124 Uint16 rsvd5:1; // 11 Reserved 125 Uint16 PGV:1; // 12 Programming Verify Status 126 Uint16 rsvd6:1; // 13 Reserved 127 Uint16 rsvd7:1; // 14 Reserved 128 Uint16 rsvd8:1; // 15 Reserved 129 Uint16 rsvd9:1; // 16 Reserved 130 Uint16 rsvd10:1; // 17 Reserved 131 Uint16 rsvd11:14; // 31:18 Reserved 132 }; 133 134 union FMSTAT_REG { 135 Uint32 all; 136 struct FMSTAT_BITS bit; 137 }; 138 139 struct FRD_INTF_CTRL_BITS { // bits description 140 Uint16 PREFETCH_EN:1; // 0 Prefetch Enable 141 Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable 142 Uint16 rsvd1:14; // 15:2 Reserved 143 Uint16 rsvd2:16; // 31:16 Reserved 144 }; 145 146 union FRD_INTF_CTRL_REG { 147 Uint32 all; 148 struct FRD_INTF_CTRL_BITS bit; 149 }; 150 151 struct FLASH_CTRL_REGS { 152 union FRDCNTL_REG FRDCNTL; // Flash Read Control Register 153 Uint16 rsvd1[28]; // Reserved 154 union FBAC_REG FBAC; // Flash Bank Access Control Register 155 union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register 156 union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register 157 union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 158 Uint16 rsvd2[4]; // Reserved 159 union FMSTAT_REG FMSTAT; // Flash Module Status Register 160 Uint16 rsvd3[340]; // Reserved 161 union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register 162 }; 163 164 struct ECC_ENABLE_BITS { // bits description 165 Uint16 ENABLE:4; // 3:0 Enable ECC 166 Uint16 rsvd1:12; // 15:4 Reserved 167 Uint16 rsvd2:16; // 31:16 Reserved 168 }; 169 170 union ECC_ENABLE_REG { 171 Uint32 all; 172 struct ECC_ENABLE_BITS bit; 173 }; 174 175 struct ERR_STATUS_BITS { // bits description 176 Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 177 Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 178 Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred 179 Uint16 rsvd1:13; // 15:3 Reserved 180 Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 181 Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 182 Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred 183 Uint16 rsvd2:13; // 31:19 Reserved 184 }; 185 186 union ERR_STATUS_REG { 187 Uint32 all; 188 struct ERR_STATUS_BITS bit; 189 }; 190 191 struct ERR_POS_BITS { // bits description 192 Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits 193 Uint16 rsvd1:2; // 7:6 Reserved 194 Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits 195 Uint16 rsvd2:7; // 15:9 Reserved 196 Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits 197 Uint16 rsvd3:2; // 23:22 Reserved 198 Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits 199 Uint16 rsvd4:7; // 31:25 Reserved 200 }; 201 202 union ERR_POS_REG { 203 Uint32 all; 204 struct ERR_POS_BITS bit; 205 }; 206 207 struct ERR_STATUS_CLR_BITS { // bits description 208 Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear 209 Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear 210 Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear 211 Uint16 rsvd1:13; // 15:3 Reserved 212 Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear 213 Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear 214 Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear 215 Uint16 rsvd2:13; // 31:19 Reserved 216 }; 217 218 union ERR_STATUS_CLR_REG { 219 Uint32 all; 220 struct ERR_STATUS_CLR_BITS bit; 221 }; 222 223 struct ERR_CNT_BITS { // bits description 224 Uint16 ERR_CNT:16; // 15:0 Error counter 225 Uint16 rsvd1:16; // 31:16 Reserved 226 }; 227 228 union ERR_CNT_REG { 229 Uint32 all; 230 struct ERR_CNT_BITS bit; 231 }; 232 233 struct ERR_THRESHOLD_BITS { // bits description 234 Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold 235 Uint16 rsvd1:16; // 31:16 Reserved 236 }; 237 238 union ERR_THRESHOLD_REG { 239 Uint32 all; 240 struct ERR_THRESHOLD_BITS bit; 241 }; 242 243 struct ERR_INTFLG_BITS { // bits description 244 Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag 245 Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag 246 Uint16 rsvd1:14; // 15:2 Reserved 247 Uint16 rsvd2:16; // 31:16 Reserved 248 }; 249 250 union ERR_INTFLG_REG { 251 Uint32 all; 252 struct ERR_INTFLG_BITS bit; 253 }; 254 255 struct ERR_INTCLR_BITS { // bits description 256 Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear 257 Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear 258 Uint16 rsvd1:14; // 15:2 Reserved 259 Uint16 rsvd2:16; // 31:16 Reserved 260 }; 261 262 union ERR_INTCLR_REG { 263 Uint32 all; 264 struct ERR_INTCLR_BITS bit; 265 }; 266 267 struct FADDR_TEST_BITS { // bits description 268 Uint16 rsvd1:3; // 2:0 Reserved 269 Uint16 ADDRL:13; // 15:3 ECC Address Low 270 Uint16 ADDRH:6; // 21:16 ECC Address High 271 Uint16 rsvd2:10; // 31:22 Reserved 272 }; 273 274 union FADDR_TEST_REG { 275 Uint32 all; 276 struct FADDR_TEST_BITS bit; 277 }; 278 279 struct FECC_TEST_BITS { // bits description 280 Uint16 ECC:8; // 7:0 ECC Control Bits 281 Uint16 rsvd1:8; // 15:8 Reserved 282 Uint16 rsvd2:16; // 31:16 Reserved 283 }; 284 285 union FECC_TEST_REG { 286 Uint32 all; 287 struct FECC_TEST_BITS bit; 288 }; 289 290 struct FECC_CTRL_BITS { // bits description 291 Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic 292 Uint16 ECC_SELECT:1; // 1 ECC Bit Select 293 Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation 294 Uint16 rsvd1:13; // 15:3 Reserved 295 Uint16 rsvd2:16; // 31:16 Reserved 296 }; 297 298 union FECC_CTRL_REG { 299 Uint32 all; 300 struct FECC_CTRL_BITS bit; 301 }; 302 303 struct FECC_STATUS_BITS { // bits description 304 Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error 305 Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error 306 Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error 307 Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error 308 Uint16 rsvd1:7; // 15:9 Reserved 309 Uint16 rsvd2:16; // 31:16 Reserved 310 }; 311 312 union FECC_STATUS_REG { 313 Uint32 all; 314 struct FECC_STATUS_BITS bit; 315 }; 316 317 struct FLASH_ECC_REGS { 318 union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable 319 Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low 320 Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High 321 Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low 322 Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High 323 union ERR_STATUS_REG ERR_STATUS; // Error Status 324 union ERR_POS_REG ERR_POS; // Error Position 325 union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear 326 union ERR_CNT_REG ERR_CNT; // Error Control 327 union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold 328 union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag 329 union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear 330 Uint32 FDATAH_TEST; // Data High Test 331 Uint32 FDATAL_TEST; // Data Low Test 332 union FADDR_TEST_REG FADDR_TEST; // ECC Test Address 333 union FECC_TEST_REG FECC_TEST; // ECC Test Address 334 union FECC_CTRL_REG FECC_CTRL; // ECC Control 335 Uint32 FOUTH_TEST; // Test Data Out High 336 Uint32 FOUTL_TEST; // Test Data Out Low 337 union FECC_STATUS_REG FECC_STATUS; // ECC Status 338 }; 339 340 struct PUMPREQUEST_BITS { // bits description 341 Uint16 PUMP_OWNERSHIP:2; // 1:0 Flash Pump Request Semaphore between CPU1 and CPU2 342 Uint16 rsvd1:14; // 15:2 Reserved 343 Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register 344 }; 345 346 union PUMPREQUEST_REG { 347 Uint32 all; 348 struct PUMPREQUEST_BITS bit; 349 }; 350 351 struct FLASH_PUMP_SEMAPHORE_REGS { 352 union PUMPREQUEST_REG PUMPREQUEST; // Flash programming semaphore PUMP request register 353 }; 354 355 //--------------------------------------------------------------------------- 356 // FLASH External References & Function Declarations: 357 // 358 #ifdef CPU1 359 extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; 360 extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; 361 extern volatile struct FLASH_ECC_REGS Flash0EccRegs; 362 #endif 363 #ifdef CPU2 364 extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; 365 extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; 366 extern volatile struct FLASH_ECC_REGS Flash0EccRegs; 367 #endif 368 #ifdef __cplusplus 369 } 370 #endif /* extern "C" */ 371 372 #endif 373 374 //=========================================================================== 375 // End of file. 376 //=========================================================================== 377