1 //########################################################################### 2 // 3 // FILE: F2837xD_i2c.h 4 // 5 // TITLE: I2C Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_I2C_H__ 44 #define __F2837xD_I2C_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // I2C Individual Register Bit Definitions: 53 54 struct I2COAR_BITS { // bits description 55 Uint16 OAR:10; // 9:0 I2C Own address 56 Uint16 rsvd1:6; // 15:10 Reserved 57 }; 58 59 union I2COAR_REG { 60 Uint16 all; 61 struct I2COAR_BITS bit; 62 }; 63 64 struct I2CIER_BITS { // bits description 65 Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable 66 Uint16 NACK:1; // 1 No-acknowledgment interrupt enable 67 Uint16 ARDY:1; // 2 Register-access-ready interrupt enable 68 Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable 69 Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable 70 Uint16 SCD:1; // 5 Stop condition detected interrupt enable 71 Uint16 AAS:1; // 6 Addressed as slave interrupt enable 72 Uint16 rsvd1:9; // 15:7 Reserved 73 }; 74 75 union I2CIER_REG { 76 Uint16 all; 77 struct I2CIER_BITS bit; 78 }; 79 80 struct I2CSTR_BITS { // bits description 81 Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit 82 Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. 83 Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit 84 Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. 85 Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. 86 Uint16 SCD:1; // 5 Stop condition detected bit. 87 Uint16 rsvd1:2; // 7:6 Reserved 88 Uint16 AD0:1; // 8 Address 0 bits 89 Uint16 AAS:1; // 9 Addressed-as-slave bit 90 Uint16 XSMT:1; // 10 Transmit shift register empty bit. 91 Uint16 RSFULL:1; // 11 Receive shift register full bit. 92 Uint16 BB:1; // 12 Bus busy bit. 93 Uint16 NACKSNT:1; // 13 NACK sent bit. 94 Uint16 SDIR:1; // 14 Slave direction bit 95 Uint16 rsvd2:1; // 15 Reserved 96 }; 97 98 union I2CSTR_REG { 99 Uint16 all; 100 struct I2CSTR_BITS bit; 101 }; 102 103 struct I2CDRR_BITS { // bits description 104 Uint16 DATA:8; // 7:0 Receive data 105 Uint16 rsvd1:8; // 15:8 Reserved 106 }; 107 108 union I2CDRR_REG { 109 Uint16 all; 110 struct I2CDRR_BITS bit; 111 }; 112 113 struct I2CSAR_BITS { // bits description 114 Uint16 SAR:10; // 9:0 Slave Address 115 Uint16 rsvd1:6; // 15:10 Reserved 116 }; 117 118 union I2CSAR_REG { 119 Uint16 all; 120 struct I2CSAR_BITS bit; 121 }; 122 123 struct I2CDXR_BITS { // bits description 124 Uint16 DATA:8; // 7:0 Transmit data 125 Uint16 rsvd1:8; // 15:8 Reserved 126 }; 127 128 union I2CDXR_REG { 129 Uint16 all; 130 struct I2CDXR_BITS bit; 131 }; 132 133 struct I2CMDR_BITS { // bits description 134 Uint16 BC:3; // 2:0 Bit count bits. 135 Uint16 FDF:1; // 3 Free Data Format 136 Uint16 STB:1; // 4 START Byte Mode 137 Uint16 IRS:1; // 5 I2C Module Reset 138 Uint16 DLB:1; // 6 Digital Loopback Mode 139 Uint16 RM:1; // 7 Repeat Mode 140 Uint16 XA:1; // 8 Expanded Address Mode 141 Uint16 TRX:1; // 9 Transmitter Mode 142 Uint16 MST:1; // 10 Master Mode 143 Uint16 STP:1; // 11 STOP Condition 144 Uint16 rsvd1:1; // 12 Reserved 145 Uint16 STT:1; // 13 START condition bit 146 Uint16 FREE:1; // 14 Debug Action 147 Uint16 NACKMOD:1; // 15 NACK mode bit 148 }; 149 150 union I2CMDR_REG { 151 Uint16 all; 152 struct I2CMDR_BITS bit; 153 }; 154 155 struct I2CISRC_BITS { // bits description 156 Uint16 INTCODE:3; // 2:0 Interrupt code bits. 157 Uint16 rsvd1:5; // 7:3 Reserved 158 Uint16 WRITE_ZEROS:4; // 11:8 Reserved 159 Uint16 rsvd2:4; // 15:12 Reserved 160 }; 161 162 union I2CISRC_REG { 163 Uint16 all; 164 struct I2CISRC_BITS bit; 165 }; 166 167 struct I2CEMDR_BITS { // bits description 168 Uint16 BC:1; // 0 Backwards compatibility mode 169 Uint16 rsvd1:15; // 15:1 Reserved 170 }; 171 172 union I2CEMDR_REG { 173 Uint16 all; 174 struct I2CEMDR_BITS bit; 175 }; 176 177 struct I2CPSC_BITS { // bits description 178 Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down 179 Uint16 rsvd1:8; // 15:8 Reserved 180 }; 181 182 union I2CPSC_REG { 183 Uint16 all; 184 struct I2CPSC_BITS bit; 185 }; 186 187 struct I2CFFTX_BITS { // bits description 188 Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level 189 Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable 190 Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear 191 Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag 192 Uint16 TXFFST:5; // 12:8 Transmit FIFO Status 193 Uint16 TXFFRST:1; // 13 Transmit FIFO Reset 194 Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable 195 Uint16 rsvd1:1; // 15 Reserved 196 }; 197 198 union I2CFFTX_REG { 199 Uint16 all; 200 struct I2CFFTX_BITS bit; 201 }; 202 203 struct I2CFFRX_BITS { // bits description 204 Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level 205 Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable 206 Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear 207 Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag 208 Uint16 RXFFST:5; // 12:8 Receive FIFO Status 209 Uint16 RXFFRST:1; // 13 Receive FIFO Reset 210 Uint16 rsvd1:2; // 15:14 Reserved 211 }; 212 213 union I2CFFRX_REG { 214 Uint16 all; 215 struct I2CFFRX_BITS bit; 216 }; 217 218 struct I2C_REGS { 219 union I2COAR_REG I2COAR; // I2C Own address 220 union I2CIER_REG I2CIER; // I2C Interrupt Enable 221 union I2CSTR_REG I2CSTR; // I2C Status 222 Uint16 I2CCLKL; // I2C Clock low-time divider 223 Uint16 I2CCLKH; // I2C Clock high-time divider 224 Uint16 I2CCNT; // I2C Data count 225 union I2CDRR_REG I2CDRR; // I2C Data receive 226 union I2CSAR_REG I2CSAR; // I2C Slave address 227 union I2CDXR_REG I2CDXR; // I2C Data Transmit 228 union I2CMDR_REG I2CMDR; // I2C Mode 229 union I2CISRC_REG I2CISRC; // I2C Interrupt Source 230 union I2CEMDR_REG I2CEMDR; // I2C Extended Mode 231 union I2CPSC_REG I2CPSC; // I2C Prescaler 232 Uint16 rsvd1[19]; // Reserved 233 union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit 234 union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive 235 }; 236 237 //--------------------------------------------------------------------------- 238 // I2C External References & Function Declarations: 239 // 240 #ifdef CPU1 241 extern volatile struct I2C_REGS I2caRegs; 242 extern volatile struct I2C_REGS I2cbRegs; 243 #endif 244 #ifdef CPU2 245 extern volatile struct I2C_REGS I2caRegs; 246 extern volatile struct I2C_REGS I2cbRegs; 247 #endif 248 #ifdef __cplusplus 249 } 250 #endif /* extern "C" */ 251 252 #endif 253 254 //=========================================================================== 255 // End of file. 256 //=========================================================================== 257