1 //########################################################################### 2 // 3 // FILE: F2837xD_piectrl.h 4 // 5 // TITLE: PIECTRL Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_PIECTRL_H__ 44 #define __F2837xD_PIECTRL_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // PIECTRL Individual Register Bit Definitions: 53 54 struct PIECTRL_BITS { // bits description 55 Uint16 ENPIE:1; // 0 PIE Enable 56 Uint16 PIEVECT:15; // 15:1 PIE Vector Address 57 }; 58 59 union PIECTRL_REG { 60 Uint16 all; 61 struct PIECTRL_BITS bit; 62 }; 63 64 struct PIEACK_BITS { // bits description 65 Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 66 Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 67 Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 68 Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 69 Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 70 Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 71 Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 72 Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 73 Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 74 Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 75 Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 76 Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 77 Uint16 rsvd1:4; // 15:12 Reserved 78 }; 79 80 union PIEACK_REG { 81 Uint16 all; 82 struct PIEACK_BITS bit; 83 }; 84 85 struct PIEIER1_BITS { // bits description 86 Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 87 Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 88 Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 89 Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 90 Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 91 Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 92 Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 93 Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 94 Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 95 Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 96 Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 97 Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 98 Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 99 Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 100 Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 101 Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 102 }; 103 104 union PIEIER1_REG { 105 Uint16 all; 106 struct PIEIER1_BITS bit; 107 }; 108 109 struct PIEIFR1_BITS { // bits description 110 Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 111 Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 112 Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 113 Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 114 Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 115 Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 116 Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 117 Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 118 Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 119 Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 120 Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 121 Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 122 Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 123 Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 124 Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 125 Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 126 }; 127 128 union PIEIFR1_REG { 129 Uint16 all; 130 struct PIEIFR1_BITS bit; 131 }; 132 133 struct PIEIER2_BITS { // bits description 134 Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 135 Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 136 Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 137 Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 138 Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 139 Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 140 Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 141 Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 142 Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 143 Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 144 Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 145 Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 146 Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 147 Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 148 Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 149 Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 150 }; 151 152 union PIEIER2_REG { 153 Uint16 all; 154 struct PIEIER2_BITS bit; 155 }; 156 157 struct PIEIFR2_BITS { // bits description 158 Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 159 Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 160 Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 161 Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 162 Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 163 Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 164 Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 165 Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 166 Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 167 Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 168 Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 169 Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 170 Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 171 Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 172 Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 173 Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 174 }; 175 176 union PIEIFR2_REG { 177 Uint16 all; 178 struct PIEIFR2_BITS bit; 179 }; 180 181 struct PIEIER3_BITS { // bits description 182 Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 183 Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 184 Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 185 Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 186 Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 187 Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 188 Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 189 Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 190 Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 191 Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 192 Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 193 Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 194 Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 195 Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 196 Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 197 Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 198 }; 199 200 union PIEIER3_REG { 201 Uint16 all; 202 struct PIEIER3_BITS bit; 203 }; 204 205 struct PIEIFR3_BITS { // bits description 206 Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 207 Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 208 Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 209 Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 210 Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 211 Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 212 Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 213 Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 214 Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 215 Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 216 Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 217 Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 218 Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 219 Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 220 Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 221 Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 222 }; 223 224 union PIEIFR3_REG { 225 Uint16 all; 226 struct PIEIFR3_BITS bit; 227 }; 228 229 struct PIEIER4_BITS { // bits description 230 Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 231 Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 232 Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 233 Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 234 Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 235 Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 236 Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 237 Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 238 Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 239 Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 240 Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 241 Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 242 Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 243 Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 244 Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 245 Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 246 }; 247 248 union PIEIER4_REG { 249 Uint16 all; 250 struct PIEIER4_BITS bit; 251 }; 252 253 struct PIEIFR4_BITS { // bits description 254 Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 255 Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 256 Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 257 Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 258 Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 259 Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 260 Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 261 Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 262 Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 263 Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 264 Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 265 Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 266 Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 267 Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 268 Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 269 Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 270 }; 271 272 union PIEIFR4_REG { 273 Uint16 all; 274 struct PIEIFR4_BITS bit; 275 }; 276 277 struct PIEIER5_BITS { // bits description 278 Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 279 Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 280 Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 281 Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 282 Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 283 Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 284 Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 285 Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 286 Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 287 Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 288 Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 289 Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 290 Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 291 Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 292 Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 293 Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 294 }; 295 296 union PIEIER5_REG { 297 Uint16 all; 298 struct PIEIER5_BITS bit; 299 }; 300 301 struct PIEIFR5_BITS { // bits description 302 Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 303 Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 304 Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 305 Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 306 Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 307 Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 308 Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 309 Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 310 Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 311 Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 312 Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 313 Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 314 Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 315 Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 316 Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 317 Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 318 }; 319 320 union PIEIFR5_REG { 321 Uint16 all; 322 struct PIEIFR5_BITS bit; 323 }; 324 325 struct PIEIER6_BITS { // bits description 326 Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 327 Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 328 Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 329 Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 330 Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 331 Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 332 Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 333 Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 334 Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 335 Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 336 Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 337 Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 338 Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 339 Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 340 Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 341 Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 342 }; 343 344 union PIEIER6_REG { 345 Uint16 all; 346 struct PIEIER6_BITS bit; 347 }; 348 349 struct PIEIFR6_BITS { // bits description 350 Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 351 Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 352 Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 353 Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 354 Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 355 Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 356 Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 357 Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 358 Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 359 Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 360 Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 361 Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 362 Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 363 Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 364 Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 365 Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 366 }; 367 368 union PIEIFR6_REG { 369 Uint16 all; 370 struct PIEIFR6_BITS bit; 371 }; 372 373 struct PIEIER7_BITS { // bits description 374 Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 375 Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 376 Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 377 Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 378 Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 379 Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 380 Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 381 Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 382 Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 383 Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 384 Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 385 Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 386 Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 387 Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 388 Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 389 Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 390 }; 391 392 union PIEIER7_REG { 393 Uint16 all; 394 struct PIEIER7_BITS bit; 395 }; 396 397 struct PIEIFR7_BITS { // bits description 398 Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 399 Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 400 Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 401 Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 402 Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 403 Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 404 Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 405 Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 406 Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 407 Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 408 Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 409 Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 410 Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 411 Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 412 Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 413 Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 414 }; 415 416 union PIEIFR7_REG { 417 Uint16 all; 418 struct PIEIFR7_BITS bit; 419 }; 420 421 struct PIEIER8_BITS { // bits description 422 Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 423 Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 424 Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 425 Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 426 Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 427 Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 428 Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 429 Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 430 Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 431 Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 432 Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 433 Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 434 Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 435 Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 436 Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 437 Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 438 }; 439 440 union PIEIER8_REG { 441 Uint16 all; 442 struct PIEIER8_BITS bit; 443 }; 444 445 struct PIEIFR8_BITS { // bits description 446 Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 447 Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 448 Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 449 Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 450 Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 451 Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 452 Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 453 Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 454 Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 455 Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 456 Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 457 Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 458 Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 459 Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 460 Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 461 Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 462 }; 463 464 union PIEIFR8_REG { 465 Uint16 all; 466 struct PIEIFR8_BITS bit; 467 }; 468 469 struct PIEIER9_BITS { // bits description 470 Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 471 Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 472 Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 473 Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 474 Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 475 Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 476 Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 477 Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 478 Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 479 Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 480 Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 481 Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 482 Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 483 Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 484 Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 485 Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 486 }; 487 488 union PIEIER9_REG { 489 Uint16 all; 490 struct PIEIER9_BITS bit; 491 }; 492 493 struct PIEIFR9_BITS { // bits description 494 Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 495 Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 496 Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 497 Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 498 Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 499 Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 500 Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 501 Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 502 Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 503 Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 504 Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 505 Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 506 Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 507 Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 508 Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 509 Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 510 }; 511 512 union PIEIFR9_REG { 513 Uint16 all; 514 struct PIEIFR9_BITS bit; 515 }; 516 517 struct PIEIER10_BITS { // bits description 518 Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 519 Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 520 Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 521 Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 522 Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 523 Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 524 Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 525 Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 526 Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 527 Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 528 Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 529 Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 530 Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 531 Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 532 Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 533 Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 534 }; 535 536 union PIEIER10_REG { 537 Uint16 all; 538 struct PIEIER10_BITS bit; 539 }; 540 541 struct PIEIFR10_BITS { // bits description 542 Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 543 Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 544 Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 545 Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 546 Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 547 Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 548 Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 549 Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 550 Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 551 Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 552 Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 553 Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 554 Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 555 Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 556 Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 557 Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 558 }; 559 560 union PIEIFR10_REG { 561 Uint16 all; 562 struct PIEIFR10_BITS bit; 563 }; 564 565 struct PIEIER11_BITS { // bits description 566 Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 567 Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 568 Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 569 Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 570 Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 571 Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 572 Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 573 Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 574 Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 575 Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 576 Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 577 Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 578 Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 579 Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 580 Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 581 Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 582 }; 583 584 union PIEIER11_REG { 585 Uint16 all; 586 struct PIEIER11_BITS bit; 587 }; 588 589 struct PIEIFR11_BITS { // bits description 590 Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 591 Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 592 Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 593 Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 594 Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 595 Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 596 Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 597 Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 598 Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 599 Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 600 Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 601 Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 602 Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 603 Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 604 Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 605 Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 606 }; 607 608 union PIEIFR11_REG { 609 Uint16 all; 610 struct PIEIFR11_BITS bit; 611 }; 612 613 struct PIEIER12_BITS { // bits description 614 Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 615 Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 616 Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 617 Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 618 Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 619 Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 620 Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 621 Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 622 Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 623 Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 624 Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 625 Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 626 Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 627 Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 628 Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 629 Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 630 }; 631 632 union PIEIER12_REG { 633 Uint16 all; 634 struct PIEIER12_BITS bit; 635 }; 636 637 struct PIEIFR12_BITS { // bits description 638 Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 639 Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 640 Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 641 Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 642 Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 643 Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 644 Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 645 Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 646 Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 647 Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 648 Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 649 Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 650 Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 651 Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 652 Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 653 Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 654 }; 655 656 union PIEIFR12_REG { 657 Uint16 all; 658 struct PIEIFR12_BITS bit; 659 }; 660 661 struct PIE_CTRL_REGS { 662 union PIECTRL_REG PIECTRL; // ePIE Control Register 663 union PIEACK_REG PIEACK; // Interrupt Acknowledge Register 664 union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register 665 union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register 666 union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register 667 union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register 668 union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register 669 union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register 670 union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register 671 union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register 672 union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register 673 union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register 674 union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register 675 union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register 676 union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register 677 union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register 678 union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register 679 union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register 680 union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register 681 union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register 682 union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register 683 union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register 684 union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register 685 union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register 686 union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register 687 union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register 688 }; 689 690 //--------------------------------------------------------------------------- 691 // PIECTRL External References & Function Declarations: 692 // 693 #ifdef CPU1 694 extern volatile struct PIE_CTRL_REGS PieCtrlRegs; 695 #endif 696 #ifdef CPU2 697 extern volatile struct PIE_CTRL_REGS PieCtrlRegs; 698 #endif 699 #ifdef __cplusplus 700 } 701 #endif /* extern "C" */ 702 703 #endif 704 705 //=========================================================================== 706 // End of file. 707 //=========================================================================== 708