1 //########################################################################### 2 // 3 // FILE: F2837xD_xbar.h 4 // 5 // TITLE: XBAR Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_XBAR_H__ 44 #define __F2837xD_XBAR_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // XBAR Individual Register Bit Definitions: 53 54 struct XBARFLG1_BITS { // bits description 55 Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal 56 Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal 57 Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal 58 Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal 59 Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal 60 Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal 61 Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal 62 Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal 63 Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal 64 Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal 65 Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal 66 Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal 67 Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal 68 Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal 69 Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal 70 Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal 71 Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal 72 Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal 73 Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal 74 Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal 75 Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal 76 Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal 77 Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal 78 Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal 79 Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal 80 Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal 81 Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal 82 Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal 83 Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal 84 Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal 85 Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal 86 Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal 87 }; 88 89 union XBARFLG1_REG { 90 Uint32 all; 91 struct XBARFLG1_BITS bit; 92 }; 93 94 struct XBARFLG2_BITS { // bits description 95 Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal 96 Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal 97 Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal 98 Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal 99 Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal 100 Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal 101 Uint16 ADCSOCAO:1; // 6 Input Flag for ADCSOCAO Signal 102 Uint16 ADCSOCBO:1; // 7 Input Flag for ADCSOCBO Signal 103 Uint16 rsvd1:1; // 8 Reserved 104 Uint16 rsvd2:1; // 9 Reserved 105 Uint16 rsvd3:1; // 10 Reserved 106 Uint16 rsvd4:1; // 11 Reserved 107 Uint16 rsvd5:1; // 12 Reserved 108 Uint16 rsvd6:1; // 13 Reserved 109 Uint16 rsvd7:1; // 14 Reserved 110 Uint16 rsvd8:1; // 15 Reserved 111 Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal 112 Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal 113 Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal 114 Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal 115 Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal 116 Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal 117 Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal 118 Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal 119 Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal 120 Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal 121 Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal 122 Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal 123 Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal 124 Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal 125 Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal 126 Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal 127 }; 128 129 union XBARFLG2_REG { 130 Uint32 all; 131 struct XBARFLG2_BITS bit; 132 }; 133 134 struct XBARFLG3_BITS { // bits description 135 Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal 136 Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal 137 Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal 138 Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal 139 Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal 140 Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal 141 Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal 142 Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal 143 Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal 144 Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal 145 Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal 146 Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal 147 Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal 148 Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal 149 Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal 150 Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal 151 Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal 152 Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal 153 Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal 154 Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal 155 Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal 156 Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal 157 Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal 158 Uint16 rsvd1:9; // 31:23 Reserved 159 }; 160 161 union XBARFLG3_REG { 162 Uint32 all; 163 struct XBARFLG3_BITS bit; 164 }; 165 166 struct XBARCLR1_BITS { // bits description 167 Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal 168 Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal 169 Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal 170 Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal 171 Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal 172 Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal 173 Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal 174 Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal 175 Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal 176 Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal 177 Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal 178 Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal 179 Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal 180 Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal 181 Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal 182 Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal 183 Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal 184 Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal 185 Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal 186 Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal 187 Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal 188 Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal 189 Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal 190 Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal 191 Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal 192 Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal 193 Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal 194 Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal 195 Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal 196 Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal 197 Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal 198 Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal 199 }; 200 201 union XBARCLR1_REG { 202 Uint32 all; 203 struct XBARCLR1_BITS bit; 204 }; 205 206 struct XBARCLR2_BITS { // bits description 207 Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal 208 Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal 209 Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal 210 Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal 211 Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal 212 Uint16 INPUT7:1; // 5 Input Flag Clear for INPUT7 Signal 213 Uint16 ADCSOCAO:1; // 6 Input Flag Clear for ADCSOCAO Signal 214 Uint16 ADCSOCBO:1; // 7 Input Flag Clear for ADCSOCBO Signal 215 Uint16 rsvd1:1; // 8 Reserved 216 Uint16 rsvd2:1; // 9 Reserved 217 Uint16 rsvd3:1; // 10 Reserved 218 Uint16 rsvd4:1; // 11 Reserved 219 Uint16 rsvd5:1; // 12 Reserved 220 Uint16 rsvd6:1; // 13 Reserved 221 Uint16 rsvd7:1; // 14 Reserved 222 Uint16 rsvd8:1; // 15 Reserved 223 Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal 224 Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal 225 Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal 226 Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal 227 Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal 228 Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal 229 Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal 230 Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal 231 Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal 232 Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal 233 Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal 234 Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal 235 Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal 236 Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal 237 Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal 238 Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal 239 }; 240 241 union XBARCLR2_REG { 242 Uint32 all; 243 struct XBARCLR2_BITS bit; 244 }; 245 246 struct XBARCLR3_BITS { // bits description 247 Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal 248 Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal 249 Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal 250 Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal 251 Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal 252 Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal 253 Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal 254 Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal 255 Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal 256 Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal 257 Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal 258 Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal 259 Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal 260 Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal 261 Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal 262 Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal 263 Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal 264 Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal 265 Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal 266 Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal 267 Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal 268 Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal 269 Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal 270 Uint16 rsvd1:9; // 31:23 Reserved 271 }; 272 273 union XBARCLR3_REG { 274 Uint32 all; 275 struct XBARCLR3_BITS bit; 276 }; 277 278 struct XBAR_REGS { 279 union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 280 union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 281 union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 282 Uint16 rsvd1[2]; // Reserved 283 union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 284 union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 285 union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 286 Uint16 rsvd2[18]; // Reserved 287 }; 288 289 //--------------------------------------------------------------------------- 290 // XBAR External References & Function Declarations: 291 // 292 #ifdef CPU1 293 extern volatile struct XBAR_REGS XbarRegs; 294 #endif 295 #ifdef __cplusplus 296 } 297 #endif /* extern "C" */ 298 299 #endif 300 301 //=========================================================================== 302 // End of file. 303 //=========================================================================== 304