1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the CORTEX:
9 * + Initialization and de-initialization functions
10 * + Peripheral Control functions
11 *
12 * @verbatim
13 ==============================================================================
14 ##### How to use this driver #####
15 ==============================================================================
16
17 [..]
18 *** How to configure Interrupts using Cortex HAL driver ***
19 ===========================================================
20 [..]
21 This section provide functions allowing to configure the NVIC interrupts (IRQ).
22 The Cortex-M3 exceptions are managed by CMSIS functions.
23
24 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
25
26 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
27
28 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
29
30
31 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
32 The pending IRQ priority will be managed only by the sub priority.
33
34 -@- IRQ priority order (sorted by highest to lowest priority):
35 (+@) Lowest pre-emption priority
36 (+@) Lowest sub priority
37 (+@) Lowest hardware priority (IRQ number)
38
39 [..]
40 *** How to configure Systick using Cortex HAL driver ***
41 ========================================================
42 [..]
43 Setup SysTick Timer for 1 msec interrupts.
44
45 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
46 is a CMSIS function that:
47 (++) Configures the SysTick Reload register with value passed as function parameter.
48 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
49 (++) Resets the SysTick Counter register.
50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
51 (++) Enables the SysTick Interrupt.
52 (++) Starts the SysTick Counter.
53
54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
55 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
56 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
57 inside the stm32l1xx_hal_cortex.h file.
58
59 (+) You can change the SysTick IRQ priority by calling the
60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
62
63 (+) To adjust the SysTick time base, use the following formula:
64
65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
67 (++) Reload Value should not exceed 0xFFFFFF
68
69 @endverbatim
70 ******************************************************************************
71 * @attention
72 *
73 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
74 * All rights reserved.</center></h2>
75 *
76 * This software component is licensed by ST under BSD 3-Clause license,
77 * the "License"; You may not use this file except in compliance with the
78 * License. You may obtain a copy of the License at:
79 * opensource.org/licenses/BSD-3-Clause
80 *
81 ******************************************************************************
82 */
83
84 /*
85 Additional Tables: CORTEX_NVIC_Priority_Table
86 The table below gives the allowed values of the pre-emption priority and subpriority according
87 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
88 ==========================================================================================================================
89 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
90 ==========================================================================================================================
91 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
92 | | | 4 bits for subpriority
93 --------------------------------------------------------------------------------------------------------------------------
94 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
95 | | | 3 bits for subpriority
96 --------------------------------------------------------------------------------------------------------------------------
97 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
98 | | | 2 bits for subpriority
99 --------------------------------------------------------------------------------------------------------------------------
100 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
101 | | | 1 bits for subpriority
102 --------------------------------------------------------------------------------------------------------------------------
103 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
104 | | | 0 bits for subpriority
105 ==========================================================================================================================
106 */
107
108 /* Includes ------------------------------------------------------------------*/
109 #include "stm32l1xx_hal.h"
110
111 /** @addtogroup STM32L1xx_HAL_Driver
112 * @{
113 */
114
115 /** @defgroup CORTEX CORTEX
116 * @brief CORTEX HAL module driver
117 * @{
118 */
119
120 #ifdef HAL_CORTEX_MODULE_ENABLED
121
122 /* Private typedef -----------------------------------------------------------*/
123 /* Private define ------------------------------------------------------------*/
124 /* Private macro -------------------------------------------------------------*/
125 /* Private variables ---------------------------------------------------------*/
126 /* Private function prototypes -----------------------------------------------*/
127 /* Private functions ---------------------------------------------------------*/
128
129 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
130 * @{
131 */
132
133
134 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
135 * @brief Initialization and Configuration functions
136 *
137 @verbatim
138 ==============================================================================
139 ##### Initialization and de-initialization functions #####
140 ==============================================================================
141 [..]
142 This section provide the Cortex HAL driver functions allowing to configure Interrupts
143 Systick functionalities
144
145 @endverbatim
146 * @{
147 */
148
149
150 /**
151 * @brief Sets the priority grouping field (pre-emption priority and subpriority)
152 * using the required unlock sequence.
153 * @param PriorityGroup The priority grouping bits length.
154 * This parameter can be one of the following values:
155 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
156 * 4 bits for subpriority
157 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
158 * 3 bits for subpriority
159 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
160 * 2 bits for subpriority
161 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
162 * 1 bits for subpriority
163 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
164 * 0 bits for subpriority
165 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
166 * The pending IRQ priority will be managed only by the subpriority.
167 * @retval None
168 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)169 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
170 {
171 /* Check the parameters */
172 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
173
174 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
175 NVIC_SetPriorityGrouping(PriorityGroup);
176 }
177
178 /**
179 * @brief Sets the priority of an interrupt.
180 * @param IRQn External interrupt number
181 * This parameter can be an enumerator of IRQn_Type enumeration
182 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
183 * @param PreemptPriority The pre-emption priority for the IRQn channel.
184 * This parameter can be a value between 0 and 15
185 * A lower priority value indicates a higher priority
186 * @param SubPriority the subpriority level for the IRQ channel.
187 * This parameter can be a value between 0 and 15
188 * A lower priority value indicates a higher priority.
189 * @retval None
190 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)191 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
192 {
193 uint32_t prioritygroup = 0x00;
194
195 /* Check the parameters */
196 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
197 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
198
199 prioritygroup = NVIC_GetPriorityGrouping();
200
201 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
202 }
203
204 /**
205 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
206 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
207 * function should be called before.
208 * @param IRQn External interrupt number
209 * This parameter can be an enumerator of IRQn_Type enumeration
210 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
211 * @retval None
212 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)213 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
214 {
215 /* Check the parameters */
216 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
217
218 /* Enable interrupt */
219 NVIC_EnableIRQ(IRQn);
220 }
221
222 /**
223 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
224 * @param IRQn External interrupt number
225 * This parameter can be an enumerator of IRQn_Type enumeration
226 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
227 * @retval None
228 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)229 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
230 {
231 /* Check the parameters */
232 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
233
234 /* Disable interrupt */
235 NVIC_DisableIRQ(IRQn);
236 }
237
238 /**
239 * @brief Initiates a system reset request to reset the MCU.
240 * @retval None
241 */
HAL_NVIC_SystemReset(void)242 void HAL_NVIC_SystemReset(void)
243 {
244 /* System Reset */
245 NVIC_SystemReset();
246 }
247
248 /**
249 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
250 * Counter is in free running mode to generate periodic interrupts.
251 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
252 * @retval status: - 0 Function succeeded.
253 * - 1 Function failed.
254 */
HAL_SYSTICK_Config(uint32_t TicksNumb)255 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
256 {
257 return SysTick_Config(TicksNumb);
258 }
259 /**
260 * @}
261 */
262
263 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
264 * @brief Cortex control functions
265 *
266 @verbatim
267 ==============================================================================
268 ##### Peripheral Control functions #####
269 ==============================================================================
270 [..]
271 This subsection provides a set of functions allowing to control the CORTEX
272 (NVIC, SYSTICK, MPU) functionalities.
273
274
275 @endverbatim
276 * @{
277 */
278
279 #if (__MPU_PRESENT == 1)
280 /**
281 * @brief Enable the MPU.
282 * @param MPU_Control Specifies the control mode of the MPU during hard fault,
283 * NMI, FAULTMASK and privileged accessto the default memory
284 * This parameter can be one of the following values:
285 * @arg MPU_HFNMI_PRIVDEF_NONE
286 * @arg MPU_HARDFAULT_NMI
287 * @arg MPU_PRIVILEGED_DEFAULT
288 * @arg MPU_HFNMI_PRIVDEF
289 * @retval None
290 */
HAL_MPU_Enable(uint32_t MPU_Control)291 void HAL_MPU_Enable(uint32_t MPU_Control)
292 {
293 /* Enable the MPU */
294 MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
295
296 /* Ensure MPU setting take effects */
297 __DSB();
298 __ISB();
299 }
300
301 /**
302 * @brief Disable the MPU.
303 * @retval None
304 */
HAL_MPU_Disable(void)305 void HAL_MPU_Disable(void)
306 {
307 /* Make sure outstanding transfers are done */
308 __DMB();
309
310 /* Disable the MPU and clear the control register*/
311 MPU->CTRL = 0;
312 }
313
314 /**
315 * @brief Initializes and configures the Region and the memory to be protected.
316 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
317 * the initialization and configuration information.
318 * @retval None
319 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)320 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
321 {
322 /* Check the parameters */
323 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
324 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
325
326 /* Set the Region number */
327 MPU->RNR = MPU_Init->Number;
328
329 if ((MPU_Init->Enable) != RESET)
330 {
331 /* Check the parameters */
332 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
333 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
334 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
335 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
336 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
337 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
338 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
339 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
340
341 MPU->RBAR = MPU_Init->BaseAddress;
342 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
343 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
344 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
345 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
346 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
347 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
348 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
349 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
350 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
351 }
352 else
353 {
354 MPU->RBAR = 0x00;
355 MPU->RASR = 0x00;
356 }
357 }
358 #endif /* __MPU_PRESENT */
359
360 /**
361 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
362 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
363 */
HAL_NVIC_GetPriorityGrouping(void)364 uint32_t HAL_NVIC_GetPriorityGrouping(void)
365 {
366 /* Get the PRIGROUP[10:8] field value */
367 return NVIC_GetPriorityGrouping();
368 }
369
370 /**
371 * @brief Gets the priority of an interrupt.
372 * @param IRQn External interrupt number
373 * This parameter can be an enumerator of IRQn_Type enumeration
374 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
375 * @param PriorityGroup the priority grouping bits length.
376 * This parameter can be one of the following values:
377 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
378 * 4 bits for subpriority
379 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
380 * 3 bits for subpriority
381 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
382 * 2 bits for subpriority
383 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
384 * 1 bits for subpriority
385 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
386 * 0 bits for subpriority
387 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
388 * @param pSubPriority Pointer on the Subpriority value (starting from 0).
389 * @retval None
390 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)391 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
392 {
393 /* Check the parameters */
394 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
395 /* Get priority for Cortex-M system or device specific interrupts */
396 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
397 }
398
399 /**
400 * @brief Sets Pending bit of an external interrupt.
401 * @param IRQn External interrupt number
402 * This parameter can be an enumerator of IRQn_Type enumeration
403 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
404 * @retval None
405 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)406 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
407 {
408 /* Set interrupt pending */
409 NVIC_SetPendingIRQ(IRQn);
410 }
411
412 /**
413 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
414 * and returns the pending bit for the specified interrupt).
415 * @param IRQn External interrupt number
416 * This parameter can be an enumerator of IRQn_Type enumeration
417 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
418 * @retval status: - 0 Interrupt status is not pending.
419 * - 1 Interrupt status is pending.
420 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)421 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
422 {
423 /* Return 1 if pending else 0 */
424 return NVIC_GetPendingIRQ(IRQn);
425 }
426
427 /**
428 * @brief Clears the pending bit of an external interrupt.
429 * @param IRQn External interrupt number
430 * This parameter can be an enumerator of IRQn_Type enumeration
431 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
432 * @retval None
433 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)434 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
435 {
436 /* Clear pending interrupt */
437 NVIC_ClearPendingIRQ(IRQn);
438 }
439
440 /**
441 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
442 * @param IRQn External interrupt number
443 * This parameter can be an enumerator of IRQn_Type enumeration
444 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
445 * @retval status: - 0 Interrupt status is not pending.
446 * - 1 Interrupt status is pending.
447 */
HAL_NVIC_GetActive(IRQn_Type IRQn)448 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
449 {
450 /* Return 1 if active else 0 */
451 return NVIC_GetActive(IRQn);
452 }
453
454 /**
455 * @brief Configures the SysTick clock source.
456 * @param CLKSource specifies the SysTick clock source.
457 * This parameter can be one of the following values:
458 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
459 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
460 * @retval None
461 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)462 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
463 {
464 /* Check the parameters */
465 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
466 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
467 {
468 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
469 }
470 else
471 {
472 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
473 }
474 }
475
476 /**
477 * @brief This function handles SYSTICK interrupt request.
478 * @retval None
479 */
HAL_SYSTICK_IRQHandler(void)480 void HAL_SYSTICK_IRQHandler(void)
481 {
482 HAL_SYSTICK_Callback();
483 }
484
485 /**
486 * @brief SYSTICK callback.
487 * @retval None
488 */
HAL_SYSTICK_Callback(void)489 __weak void HAL_SYSTICK_Callback(void)
490 {
491 /* NOTE : This function Should not be modified, when the callback is needed,
492 the HAL_SYSTICK_Callback could be implemented in the user file
493 */
494 }
495
496 /**
497 * @}
498 */
499
500 /**
501 * @}
502 */
503
504 #endif /* HAL_CORTEX_MODULE_ENABLED */
505 /**
506 * @}
507 */
508
509 /**
510 * @}
511 */
512
513 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
514