1 /***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
2 * File Name : ch32f10x_dma.c
3 * Author : WCH
4 * Version : V1.0.0
5 * Date : 2019/10/15
6 * Description : This file provides all the DMA firmware functions.
7 *******************************************************************************/
8 #include "ch32f10x_dma.h"
9 #include "ch32f10x_rcc.h"
10
11 /* DMA1 Channelx interrupt pending bit masks */
12 #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
13 #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
14 #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
15 #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
16 #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
17 #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
18 #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
19
20 /* DMA2 Channelx interrupt pending bit masks */
21 #define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
22 #define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
23 #define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
24 #define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
25 #define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
26
27 /* DMA2 FLAG mask */
28 #define FLAG_Mask ((uint32_t)0x10000000)
29
30 /* DMA registers Masks */
31 #define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
32
33
34 /********************************************************************************
35 * Function Name : DMA_DeInit
36 * Description : Deinitializes the DMAy Channelx registers to their default reset
37 * values.
38 * Input : DMAy_Channelx:here y can be 1 or 2 to select the DMA and x can be
39 * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
40 * DMA Channel.
41 * Return : None
42 *********************************************************************************/
DMA_DeInit(DMA_Channel_TypeDef * DMAy_Channelx)43 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
44 {
45 DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
46 DMAy_Channelx->CFGR = 0;
47 DMAy_Channelx->CNTR = 0;
48 DMAy_Channelx->PADDR = 0;
49 DMAy_Channelx->MADDR = 0;
50 if (DMAy_Channelx == DMA1_Channel1)
51 {
52 DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
53 }
54 else if (DMAy_Channelx == DMA1_Channel2)
55 {
56 DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
57 }
58 else if (DMAy_Channelx == DMA1_Channel3)
59 {
60 DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
61 }
62 else if (DMAy_Channelx == DMA1_Channel4)
63 {
64 DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
65 }
66 else if (DMAy_Channelx == DMA1_Channel5)
67 {
68 DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
69 }
70 else if (DMAy_Channelx == DMA1_Channel6)
71 {
72 DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
73 }
74 else if (DMAy_Channelx == DMA1_Channel7)
75 {
76 DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
77 }
78 else if (DMAy_Channelx == DMA2_Channel1)
79 {
80 DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
81 }
82 else if (DMAy_Channelx == DMA2_Channel2)
83 {
84 DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
85 }
86 else if (DMAy_Channelx == DMA2_Channel3)
87 {
88 DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
89 }
90 else if (DMAy_Channelx == DMA2_Channel4)
91 {
92 DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
93 }
94 else
95 {
96 if (DMAy_Channelx == DMA2_Channel5)
97 {
98 DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
99 }
100 }
101 }
102
103
104 /********************************************************************************
105 * Function Name : DMA_Init
106 * Description : Initializes the DMAy Channelx according to the specified
107 * parameters in the DMA_InitStruct.
108 * Input : DMAy_Channelx:here y can be 1 or 2 to select the DMA and x can be
109 * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
110 * DMA Channel.
111 * DMA_InitStruct:pointer to a DMA_InitTypeDef structure that
112 * contains the configuration information for the
113 * specified DMA Channel.
114 * Return : None
115 *********************************************************************************/
DMA_Init(DMA_Channel_TypeDef * DMAy_Channelx,DMA_InitTypeDef * DMA_InitStruct)116 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
117 {
118 uint32_t tmpreg = 0;
119
120 tmpreg = DMAy_Channelx->CFGR;
121 tmpreg &= CFGR_CLEAR_Mask;
122 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
123 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
124 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
125 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
126
127 DMAy_Channelx->CFGR = tmpreg;
128 DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
129 DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
130 DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
131 }
132
133
134 /********************************************************************************
135 * Function Name : DMA_StructInit
136 * Description : Fills each DMA_InitStruct member with its default value.
137 * Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
138 * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
139 * be initialized.
140 * Return : None
141 *********************************************************************************/
DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct)142 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
143 {
144 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
145 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
146 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
147 DMA_InitStruct->DMA_BufferSize = 0;
148 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
149 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
150 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
151 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
152 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
153 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
154 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
155 }
156
157
158 /********************************************************************************
159 * Function Name : DMA_Cmd
160 * Description : Enables or disables the specified DMAy Channelx.
161 * Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
162 * be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
163 * the DMA Channel.
164 * NewState : new state of the DMAy Channelx(ENABLE or DISABLE).
165 * Return : None
166 *********************************************************************************/
DMA_Cmd(DMA_Channel_TypeDef * DMAy_Channelx,FunctionalState NewState)167 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
168 {
169 if (NewState != DISABLE)
170 {
171 DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
172 }
173 else
174 {
175 DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
176 }
177 }
178
179 /********************************************************************************
180 * Function Name : DMA_ITConfig
181 * Description : Enables or disables the specified DMAy Channelx interrupts.
182 * Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
183 * be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
184 * the DMA Channel.
185 * DMA_IT : specifies the DMA interrupts sources to be enabled
186 * or disabled.
187 * DMA_IT_TC : Transfer complete interrupt mask
188 * DMA_IT_HT : Half transfer interrupt mask
189 * DMA_IT_TE : Transfer error interrupt mask
190 * NewState : new state of the DMAy Channelx(ENABLE or DISABLE).
191 * Return : None
192 *********************************************************************************/
DMA_ITConfig(DMA_Channel_TypeDef * DMAy_Channelx,uint32_t DMA_IT,FunctionalState NewState)193 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
194 {
195 if (NewState != DISABLE)
196 {
197 DMAy_Channelx->CFGR |= DMA_IT;
198 }
199 else
200 {
201 DMAy_Channelx->CFGR &= ~DMA_IT;
202 }
203 }
204
205 /********************************************************************************
206 * Function Name : DMA_SetCurrDataCounter
207 * Description : Sets the number of data units in the current DMAy Channelx transfer.
208 * Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
209 * be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
210 * the DMA Channel.
211 * DataNumber : The number of data units in the current DMAy Channelx
212 * transfer.
213 * Return : None
214 *********************************************************************************/
DMA_SetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx,uint16_t DataNumber)215 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
216 {
217 DMAy_Channelx->CNTR = DataNumber;
218 }
219
220 /********************************************************************************
221 * Function Name : DMA_SetCurrDataCounter
222 * Description : Sets the number of data units in the current DMAy Channelx transfer.
223 * Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
224 * be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
225 * the DMA Channel.
226 * Return : DataNumber : The number of remaining data units in the current
227 * DMAy Channelx transfer.
228 *********************************************************************************/
DMA_GetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx)229 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
230 {
231 return ((uint16_t)(DMAy_Channelx->CNTR));
232 }
233
234
235 /********************************************************************************
236 * Function Name : DMA_GetFlagStatus
237 * Description : Checks whether the specified DMAy Channelx flag is set or not.
238 * Input : DMAy_FLAG: specifies the flag to check.
239 * DMA1_FLAG_GL1: DMA1 Channel1 global flag.
240 * DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
241 * DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
242 * DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
243 * DMA1_FLAG_GL2: DMA1 Channel2 global flag.
244 * DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
245 * DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
246 * DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
247 * DMA1_FLAG_GL3: DMA1 Channel3 global flag.
248 * DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
249 * DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
250 * DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
251 * DMA1_FLAG_GL4: DMA1 Channel4 global flag.
252 * DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
253 * DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
254 * DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
255 * DMA1_FLAG_GL5: DMA1 Channel5 global flag.
256 * DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
257 * DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
258 * DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
259 * DMA1_FLAG_GL6: DMA1 Channel6 global flag.
260 * DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
261 * DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
262 * DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
263 * DMA1_FLAG_GL7: DMA1 Channel7 global flag.
264 * DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
265 * DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
266 * DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
267 * DMA2_FLAG_GL1: DMA2 Channel1 global flag.
268 * DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
269 * DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
270 * DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
271 * DMA2_FLAG_GL2: DMA2 Channel2 global flag.
272 * DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
273 * DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
274 * DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
275 * DMA2_FLAG_GL3: DMA2 Channel3 global flag.
276 * DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
277 * DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
278 * DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
279 * DMA2_FLAG_GL4: DMA2 Channel4 global flag.
280 * DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
281 * DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
282 * DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
283 * DMA2_FLAG_GL5: DMA2 Channel5 global flag.
284 * DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
285 * DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
286 * DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
287 * Return : The new state of DMAy_FLAG (SET or RESET).
288 *********************************************************************************/
DMA_GetFlagStatus(uint32_t DMAy_FLAG)289 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
290 {
291 FlagStatus bitstatus = RESET;
292 uint32_t tmpreg = 0;
293
294 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
295 {
296 tmpreg = DMA2->INTFR ;
297 }
298 else
299 {
300 tmpreg = DMA1->INTFR ;
301 }
302
303 if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
304 {
305 bitstatus = SET;
306 }
307 else
308 {
309 bitstatus = RESET;
310 }
311
312 return bitstatus;
313 }
314
315
316 /********************************************************************************
317 * Function Name : DMA_ClearFlag
318 * Description : Clears the DMAy Channelx's pending flags.
319 * Input : DMAy_FLAG: specifies the flag to check.
320 * DMA1_FLAG_GL1: DMA1 Channel1 global flag.
321 * DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
322 * DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
323 * DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
324 * DMA1_FLAG_GL2: DMA1 Channel2 global flag.
325 * DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
326 * DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
327 * DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
328 * DMA1_FLAG_GL3: DMA1 Channel3 global flag.
329 * DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
330 * DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
331 * DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
332 * DMA1_FLAG_GL4: DMA1 Channel4 global flag.
333 * DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
334 * DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
335 * DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
336 * DMA1_FLAG_GL5: DMA1 Channel5 global flag.
337 * DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
338 * DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
339 * DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
340 * DMA1_FLAG_GL6: DMA1 Channel6 global flag.
341 * DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
342 * DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
343 * DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
344 * DMA1_FLAG_GL7: DMA1 Channel7 global flag.
345 * DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
346 * DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
347 * DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
348 * DMA2_FLAG_GL1: DMA2 Channel1 global flag.
349 * DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
350 * DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
351 * DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
352 * DMA2_FLAG_GL2: DMA2 Channel2 global flag.
353 * DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
354 * DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
355 * DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
356 * DMA2_FLAG_GL3: DMA2 Channel3 global flag.
357 * DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
358 * DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
359 * DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
360 * DMA2_FLAG_GL4: DMA2 Channel4 global flag.
361 * DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
362 * DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
363 * DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
364 * DMA2_FLAG_GL5: DMA2 Channel5 global flag.
365 * DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
366 * DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
367 * DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
368 * Return : NONE
369 *********************************************************************************/
DMA_ClearFlag(uint32_t DMAy_FLAG)370 void DMA_ClearFlag(uint32_t DMAy_FLAG)
371 {
372 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
373 {
374 DMA2->INTFCR = DMAy_FLAG;
375 }
376 else
377 {
378 DMA1->INTFCR = DMAy_FLAG;
379 }
380 }
381
382 /********************************************************************************
383 * Function Name : DMA_GetITStatus
384 * Description : Checks whether the specified DMAy Channelx interrupt has occurred
385 * or not.
386 * Input : DMAy_IT: specifies the DMAy interrupt source to check.
387 * DMA1_IT_GL1: DMA1 Channel1 global flag.
388 * DMA1_IT_TC1: DMA1 Channel1 transfer complete flag.
389 * DMA1_IT_HT1: DMA1 Channel1 half transfer flag.
390 * DMA1_IT_TE1: DMA1 Channel1 transfer error flag.
391 * DMA1_IT_GL2: DMA1 Channel2 global flag.
392 * DMA1_IT_TC2: DMA1 Channel2 transfer complete flag.
393 * DMA1_IT_HT2: DMA1 Channel2 half transfer flag.
394 * DMA1_IT_TE2: DMA1 Channel2 transfer error flag.
395 * DMA1_IT_GL3: DMA1 Channel3 global flag.
396 * DMA1_IT_TC3: DMA1 Channel3 transfer complete flag.
397 * DMA1_IT_HT3: DMA1 Channel3 half transfer flag.
398 * DMA1_IT_TE3: DMA1 Channel3 transfer error flag.
399 * DMA1_IT_GL4: DMA1 Channel4 global flag.
400 * DMA1_IT_TC4: DMA1 Channel4 transfer complete flag.
401 * DMA1_IT_HT4: DMA1 Channel4 half transfer flag.
402 * DMA1_IT_TE4: DMA1 Channel4 transfer error flag.
403 * DMA1_IT_GL5: DMA1 Channel5 global flag.
404 * DMA1_IT_TC5: DMA1 Channel5 transfer complete flag.
405 * DMA1_IT_HT5: DMA1 Channel5 half transfer flag.
406 * DMA1_IT_TE5: DMA1 Channel5 transfer error flag.
407 * DMA1_IT_GL6: DMA1 Channel6 global flag.
408 * DMA1_IT_TC6: DMA1 Channel6 transfer complete flag.
409 * DMA1_IT_HT6: DMA1 Channel6 half transfer flag.
410 * DMA1_IT_TE6: DMA1 Channel6 transfer error flag.
411 * DMA1_IT_GL7: DMA1 Channel7 global flag.
412 * DMA1_IT_TC7: DMA1 Channel7 transfer complete flag.
413 * DMA1_IT_HT7: DMA1 Channel7 half transfer flag.
414 * DMA1_IT_TE7: DMA1 Channel7 transfer error flag.
415 * DMA2_IT_GL1: DMA2 Channel1 global flag.
416 * DMA2_IT_TC1: DMA2 Channel1 transfer complete flag.
417 * DMA2_IT_HT1: DMA2 Channel1 half transfer flag.
418 * DMA2_IT_TE1: DMA2 Channel1 transfer error flag.
419 * DMA2_IT_GL2: DMA2 Channel2 global flag.
420 * DMA2_IT_TC2: DMA2 Channel2 transfer complete flag.
421 * DMA2_IT_HT2: DMA2 Channel2 half transfer flag.
422 * DMA2_IT_TE2: DMA2 Channel2 transfer error flag.
423 * DMA2_IT_GL3: DMA2 Channel3 global flag.
424 * DMA2_IT_TC3: DMA2 Channel3 transfer complete flag.
425 * DMA2_IT_HT3: DMA2 Channel3 half transfer flag.
426 * DMA2_IT_TE3: DMA2 Channel3 transfer error flag.
427 * DMA2_IT_GL4: DMA2 Channel4 global flag.
428 * DMA2_IT_TC4: DMA2 Channel4 transfer complete flag.
429 * DMA2_IT_HT4: DMA2 Channel4 half transfer flag.
430 * DMA2_IT_TE4: DMA2 Channel4 transfer error flag.
431 * DMA2_IT_GL5: DMA2 Channel5 global flag.
432 * DMA2_IT_TC5: DMA2 Channel5 transfer complete flag.
433 * DMA2_IT_HT5: DMA2 Channel5 half transfer flag.
434 * DMA2_IT_TE5: DMA2 Channel5 transfer error flag.
435 * Return : The new state of DMAy_IT (SET or RESET).
436 *********************************************************************************/
DMA_GetITStatus(uint32_t DMAy_IT)437 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
438 {
439 ITStatus bitstatus = RESET;
440 uint32_t tmpreg = 0;
441
442 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
443 {
444 tmpreg = DMA2->INTFR;
445 }
446 else
447 {
448 tmpreg = DMA1->INTFR;
449 }
450
451 if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
452 {
453 bitstatus = SET;
454 }
455 else
456 {
457 bitstatus = RESET;
458 }
459 return bitstatus;
460 }
461
462
463 /********************************************************************************
464 * Function Name : DMA_ClearITPendingBit
465 * Description : Clears the DMAy Channelx's interrupt pending bits.
466 * Input : DMAy_IT: specifies the DMAy interrupt source to check.
467 * DMA1_IT_GL1: DMA1 Channel1 global flag.
468 * DMA1_IT_TC1: DMA1 Channel1 transfer complete flag.
469 * DMA1_IT_HT1: DMA1 Channel1 half transfer flag.
470 * DMA1_IT_TE1: DMA1 Channel1 transfer error flag.
471 * DMA1_IT_GL2: DMA1 Channel2 global flag.
472 * DMA1_IT_TC2: DMA1 Channel2 transfer complete flag.
473 * DMA1_IT_HT2: DMA1 Channel2 half transfer flag.
474 * DMA1_IT_TE2: DMA1 Channel2 transfer error flag.
475 * DMA1_IT_GL3: DMA1 Channel3 global flag.
476 * DMA1_IT_TC3: DMA1 Channel3 transfer complete flag.
477 * DMA1_IT_HT3: DMA1 Channel3 half transfer flag.
478 * DMA1_IT_TE3: DMA1 Channel3 transfer error flag.
479 * DMA1_IT_GL4: DMA1 Channel4 global flag.
480 * DMA1_IT_TC4: DMA1 Channel4 transfer complete flag.
481 * DMA1_IT_HT4: DMA1 Channel4 half transfer flag.
482 * DMA1_IT_TE4: DMA1 Channel4 transfer error flag.
483 * DMA1_IT_GL5: DMA1 Channel5 global flag.
484 * DMA1_IT_TC5: DMA1 Channel5 transfer complete flag.
485 * DMA1_IT_HT5: DMA1 Channel5 half transfer flag.
486 * DMA1_IT_TE5: DMA1 Channel5 transfer error flag.
487 * DMA1_IT_GL6: DMA1 Channel6 global flag.
488 * DMA1_IT_TC6: DMA1 Channel6 transfer complete flag.
489 * DMA1_IT_HT6: DMA1 Channel6 half transfer flag.
490 * DMA1_IT_TE6: DMA1 Channel6 transfer error flag.
491 * DMA1_IT_GL7: DMA1 Channel7 global flag.
492 * DMA1_IT_TC7: DMA1 Channel7 transfer complete flag.
493 * DMA1_IT_HT7: DMA1 Channel7 half transfer flag.
494 * DMA1_IT_TE7: DMA1 Channel7 transfer error flag.
495 * DMA2_IT_GL1: DMA2 Channel1 global flag.
496 * DMA2_IT_TC1: DMA2 Channel1 transfer complete flag.
497 * DMA2_IT_HT1: DMA2 Channel1 half transfer flag.
498 * DMA2_IT_TE1: DMA2 Channel1 transfer error flag.
499 * DMA2_IT_GL2: DMA2 Channel2 global flag.
500 * DMA2_IT_TC2: DMA2 Channel2 transfer complete flag.
501 * DMA2_IT_HT2: DMA2 Channel2 half transfer flag.
502 * DMA2_IT_TE2: DMA2 Channel2 transfer error flag.
503 * DMA2_IT_GL3: DMA2 Channel3 global flag.
504 * DMA2_IT_TC3: DMA2 Channel3 transfer complete flag.
505 * DMA2_IT_HT3: DMA2 Channel3 half transfer flag.
506 * DMA2_IT_TE3: DMA2 Channel3 transfer error flag.
507 * DMA2_IT_GL4: DMA2 Channel4 global flag.
508 * DMA2_IT_TC4: DMA2 Channel4 transfer complete flag.
509 * DMA2_IT_HT4: DMA2 Channel4 half transfer flag.
510 * DMA2_IT_TE4: DMA2 Channel4 transfer error flag.
511 * DMA2_IT_GL5: DMA2 Channel5 global flag.
512 * DMA2_IT_TC5: DMA2 Channel5 transfer complete flag.
513 * DMA2_IT_HT5: DMA2 Channel5 half transfer flag.
514 * DMA2_IT_TE5: DMA2 Channel5 transfer error flag.
515 * Return : None
516 *********************************************************************************/
DMA_ClearITPendingBit(uint32_t DMAy_IT)517 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
518 {
519 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
520 {
521 DMA2->INTFCR = DMAy_IT;
522 }
523 else
524 {
525 DMA1->INTFCR = DMAy_IT;
526 }
527 }
528
529