1 /***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
2 * File Name : ch32f10x_rcc.c
3 * Author : WCH
4 * Version : V1.0.0
5 * Date : 2019/10/15
6 * Description : This file provides all the RCC firmware functions.
7 *******************************************************************************/
8 #include "ch32f10x_rcc.h"
9
10 /* ------------ RCC registers bit address in the alias region ----------- */
11 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
12
13 /* --- CTLR Register ---*/
14
15 /* Alias word address of HSION bit */
16 #define CTLR_OFFSET (RCC_OFFSET + 0x00)
17 #define HSION_BitNumber 0x00
18 #define CTLR_HSION_BB (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (HSION_BitNumber * 4))
19
20 /* Alias word address of PLLON bit */
21 #define PLLON_BitNumber 0x18
22 #define CTLR_PLLON_BB (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (PLLON_BitNumber * 4))
23
24 /* Alias word address of CSSON bit */
25 #define CSSON_BitNumber 0x13
26 #define CTLR_CSSON_BB (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (CSSON_BitNumber * 4))
27
28 /* --- CFGR0 Register ---*/
29
30 /* Alias word address of USBPRE bit */
31 #define CFGR0_OFFSET (RCC_OFFSET + 0x04)
32 #define USBPRE_BitNumber 0x16
33 #define CFGR0_USBPRE_BB (PERIPH_BB_BASE + (CFGR0_OFFSET * 32) + (USBPRE_BitNumber * 4))
34
35 /* --- BDCTLR Register ---*/
36
37 /* Alias word address of RTCEN bit */
38 #define BDCTLR_OFFSET (RCC_OFFSET + 0x20)
39 #define RTCEN_BitNumber 0x0F
40 #define BDCTLR_RTCEN_BB (PERIPH_BB_BASE + (BDCTLR_OFFSET * 32) + (RTCEN_BitNumber * 4))
41
42 /* Alias word address of BDRST bit */
43 #define BDRST_BitNumber 0x10
44 #define BDCTLR_BDRST_BB (PERIPH_BB_BASE + (BDCTLR_OFFSET * 32) + (BDRST_BitNumber * 4))
45
46 /* --- RSTSCKR Register ---*/
47
48 /* Alias word address of LSION bit */
49 #define RSTSCKR_OFFSET (RCC_OFFSET + 0x24)
50 #define LSION_BitNumber 0x00
51 #define RSTSCKR_LSION_BB (PERIPH_BB_BASE + (RSTSCKR_OFFSET * 32) + (LSION_BitNumber * 4))
52
53 /* ---------------------- RCC registers bit mask ------------------------ */
54
55 /* CTLR register bit mask */
56 #define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
57 #define CTLR_HSEBYP_Set ((uint32_t)0x00040000)
58 #define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
59 #define CTLR_HSEON_Set ((uint32_t)0x00010000)
60 #define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
61
62 #define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF)
63 #define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000)
64 #define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000)
65 #define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000)
66 #define CFGR0_SWS_Mask ((uint32_t)0x0000000C)
67 #define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC)
68 #define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
69 #define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
70 #define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
71 #define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700)
72 #define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
73 #define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800)
74 #define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
75 #define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
76
77 /* RSTSCKR register bit mask */
78 #define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
79
80 /* RCC Flag Mask */
81 #define FLAG_Mask ((uint8_t)0x1F)
82
83 /* INTR register byte 2 (Bits[15:8]) base address */
84 #define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009)
85
86 /* INTR register byte 3 (Bits[23:16]) base address */
87 #define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
88
89 /* CFGR0 register byte 4 (Bits[31:24]) base address */
90 #define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
91
92 /* BDCTLR register base address */
93 #define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET)
94
95
96 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
97 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
98
99 /*******************************************************************************
100 * Function Name : RCC_DeInit
101 * Description : Resets the RCC clock configuration to the default reset state.
102 * Input : None
103 * Return : None
104 *******************************************************************************/
RCC_DeInit(void)105 void RCC_DeInit(void)
106 {
107 RCC->CTLR |= (uint32_t)0x00000001;
108 RCC->CFGR0 &= (uint32_t)0xF8FF0000;
109 RCC->CTLR &= (uint32_t)0xFEF6FFFF;
110 RCC->CTLR &= (uint32_t)0xFFFBFFFF;
111 RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
112 RCC->INTR = 0x009F0000;
113 }
114
115 /*******************************************************************************
116 * Function Name : RCC_HSEConfig
117 * Description : Configures the External High Speed oscillator (HSE).
118 * Input : RCC_HSE:
119 * RCC_HSE_OFF: HSE oscillator OFF.
120 * RCC_HSE_ON: HSE oscillator ON.
121 * RCC_HSE_Bypass: HSE oscillator bypassed with external clock.
122 * Return : None
123 *******************************************************************************/
RCC_HSEConfig(uint32_t RCC_HSE)124 void RCC_HSEConfig(uint32_t RCC_HSE)
125 {
126 RCC->CTLR &= CTLR_HSEON_Reset;
127 RCC->CTLR &= CTLR_HSEBYP_Reset;
128
129 switch(RCC_HSE)
130 {
131 case RCC_HSE_ON:
132 RCC->CTLR |= CTLR_HSEON_Set;
133 break;
134
135 case RCC_HSE_Bypass:
136 RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
137 break;
138
139 default:
140 break;
141 }
142 }
143
144 /*******************************************************************************
145 * Function Name : RCC_WaitForHSEStartUp
146 * Description : Configures the External High Speed oscillator (HSE).
147 * Input : None
148 * Return : SUCCESS: HSE oscillator is stable and ready to use.
149 * ERROR: HSE oscillator not yet ready.
150 *******************************************************************************/
RCC_WaitForHSEStartUp(void)151 ErrorStatus RCC_WaitForHSEStartUp(void)
152 {
153 __IO uint32_t StartUpCounter = 0;
154
155 ErrorStatus status = ERROR;
156 FlagStatus HSEStatus = RESET;
157
158 do
159 {
160 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
161 StartUpCounter++;
162 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
163
164 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
165 {
166 status = SUCCESS;
167 }
168 else
169 {
170 status = ERROR;
171 }
172
173 return (status);
174 }
175
176 /*******************************************************************************
177 * Function Name : RCC_AdjustHSICalibrationValue
178 * Description : Adjusts the Internal High Speed oscillator (HSI) calibration value.
179 * Input : HSICalibrationValue: specifies the calibration trimming value.
180 * This parameter must be a number between 0 and 0x1F.
181 * Return : None
182 *******************************************************************************/
RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)183 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
184 {
185 uint32_t tmpreg = 0;
186
187 tmpreg = RCC->CTLR;
188 tmpreg &= CTLR_HSITRIM_Mask;
189 tmpreg |= (uint32_t)HSICalibrationValue << 3;
190 RCC->CTLR = tmpreg;
191 }
192
193 /*******************************************************************************
194 * Function Name : RCC_HSICmd
195 * Description : Enables or disables the Internal High Speed oscillator (HSI).
196 * Input : NewState: ENABLE or DISABLE.
197 * Return : None
198 *******************************************************************************/
RCC_HSICmd(FunctionalState NewState)199 void RCC_HSICmd(FunctionalState NewState)
200 {
201 *(__IO uint32_t *) CTLR_HSION_BB = (uint32_t)NewState;
202 }
203
204 /*******************************************************************************
205 * Function Name : RCC_PLLConfig
206 * Description : Configures the PLL clock source and multiplication factor.
207 * Input : RCC_PLLSource: specifies the PLL entry clock source.
208 * RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2
209 * selected as PLL clock entry.
210 * RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL
211 * clock entry.
212 * RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2
213 * selected as PLL clock entry.
214 * RCC_PLLMul: specifies the PLL multiplication factor.
215 * This parameter can be RCC_PLLMul_x where x:[2,16].
216 * Return : None
217 *******************************************************************************/
RCC_PLLConfig(uint32_t RCC_PLLSource,uint32_t RCC_PLLMul)218 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
219 {
220 uint32_t tmpreg = 0;
221
222 tmpreg = RCC->CFGR0;
223 tmpreg &= CFGR0_PLL_Mask;
224 tmpreg |= RCC_PLLSource | RCC_PLLMul;
225 RCC->CFGR0 = tmpreg;
226 }
227
228 /*******************************************************************************
229 * Function Name : RCC_PLLCmd
230 * Description : Enables or disables the PLL.
231 * Input : NewState: ENABLE or DISABLE.
232 * Return : None
233 *******************************************************************************/
RCC_PLLCmd(FunctionalState NewState)234 void RCC_PLLCmd(FunctionalState NewState)
235 {
236 *(__IO uint32_t *) CTLR_PLLON_BB = (uint32_t)NewState;
237 }
238
239 /*******************************************************************************
240 * Function Name : RCC_SYSCLKConfig
241 * Description : Configures the system clock (SYSCLK).
242 * Input : RCC_SYSCLKSource: specifies the clock source used as system clock.
243 * RCC_SYSCLKSource_HSI: HSI selected as system clock.
244 * RCC_SYSCLKSource_HSE: HSE selected as system clock.
245 * RCC_SYSCLKSource_PLLCLK: PLL selected as system clock.
246 * Return : None
247 *******************************************************************************/
RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)248 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
249 {
250 uint32_t tmpreg = 0;
251
252 tmpreg = RCC->CFGR0;
253 tmpreg &= CFGR0_SW_Mask;
254 tmpreg |= RCC_SYSCLKSource;
255 RCC->CFGR0 = tmpreg;
256 }
257
258 /*******************************************************************************
259 * Function Name : RCC_GetSYSCLKSource
260 * Description : Configures the system clock (SYSCLK).
261 * Input : None
262 * Return : 0x00: HSI used as system clock.
263 * 0x04: HSE used as system clock.
264 * 0x08: PLL used as system clock.
265 *******************************************************************************/
RCC_GetSYSCLKSource(void)266 uint8_t RCC_GetSYSCLKSource(void)
267 {
268 return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask));
269 }
270
271 /*******************************************************************************
272 * Function Name : RCC_HCLKConfig
273 * Description : Configures the AHB clock (HCLK).
274 * Input : RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
275 * the system clock (SYSCLK).
276 * RCC_SYSCLK_Div1: AHB clock = SYSCLK.
277 * RCC_SYSCLK_Div2: AHB clock = SYSCLK/2.
278 * RCC_SYSCLK_Div4: AHB clock = SYSCLK/4.
279 * RCC_SYSCLK_Div8: AHB clock = SYSCLK/8.
280 * RCC_SYSCLK_Div16: AHB clock = SYSCLK/16.
281 * RCC_SYSCLK_Div64: AHB clock = SYSCLK/64.
282 * RCC_SYSCLK_Div128: AHB clock = SYSCLK/128.
283 * RCC_SYSCLK_Div256: AHB clock = SYSCLK/256.
284 * RCC_SYSCLK_Div512: AHB clock = SYSCLK/512.
285 * Return : None
286 *******************************************************************************/
RCC_HCLKConfig(uint32_t RCC_SYSCLK)287 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
288 {
289 uint32_t tmpreg = 0;
290
291 tmpreg = RCC->CFGR0;
292 tmpreg &= CFGR0_HPRE_Reset_Mask;
293 tmpreg |= RCC_SYSCLK;
294 RCC->CFGR0 = tmpreg;
295 }
296
297 /*******************************************************************************
298 * Function Name : RCC_PCLK1Config
299 * Description : Configures the Low Speed APB clock (PCLK1).
300 * Input : RCC_HCLK: defines the APB1 clock divider. This clock is derived from
301 * the AHB clock (HCLK).
302 * RCC_HCLK_Div1: APB1 clock = HCLK.
303 * RCC_HCLK_Div2: APB1 clock = HCLK/2.
304 * RCC_HCLK_Div4: APB1 clock = HCLK/4.
305 * RCC_HCLK_Div8: APB1 clock = HCLK/8.
306 * RCC_HCLK_Div16: APB1 clock = HCLK/16.
307 * Return : None
308 *******************************************************************************/
RCC_PCLK1Config(uint32_t RCC_HCLK)309 void RCC_PCLK1Config(uint32_t RCC_HCLK)
310 {
311 uint32_t tmpreg = 0;
312
313 tmpreg = RCC->CFGR0;
314 tmpreg &= CFGR0_PPRE1_Reset_Mask;
315 tmpreg |= RCC_HCLK;
316 RCC->CFGR0 = tmpreg;
317 }
318
319 /*******************************************************************************
320 * Function Name : RCC_PCLK2Config
321 * Description : Configures the High Speed APB clock (PCLK2).
322 * Input : RCC_HCLK: defines the APB2 clock divider. This clock is derived from
323 * the AHB clock (HCLK).
324 * RCC_HCLK_Div1: APB2 clock = HCLK.
325 * RCC_HCLK_Div2: APB2 clock = HCLK/2.
326 * RCC_HCLK_Div4: APB2 clock = HCLK/4.
327 * RCC_HCLK_Div8: APB2 clock = HCLK/8.
328 * RCC_HCLK_Div16: APB2 clock = HCLK/16.
329 * Return : None
330 *******************************************************************************/
RCC_PCLK2Config(uint32_t RCC_HCLK)331 void RCC_PCLK2Config(uint32_t RCC_HCLK)
332 {
333 uint32_t tmpreg = 0;
334
335 tmpreg = RCC->CFGR0;
336 tmpreg &= CFGR0_PPRE2_Reset_Mask;
337 tmpreg |= RCC_HCLK << 3;
338 RCC->CFGR0 = tmpreg;
339 }
340
341 /*******************************************************************************
342 * Function Name : RCC_ITConfig
343 * Description : Enables or disables the specified RCC interrupts.
344 * Input : RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
345 * RCC_IT_LSIRDY: LSI ready interrupt.
346 * RCC_IT_LSERDY: LSE ready interrupt.
347 * RCC_IT_HSIRDY: HSI ready interrupt.
348 * RCC_IT_HSERDY: HSE ready interrupt.
349 * RCC_IT_PLLRDY: PLL ready interrupt.
350 * NewState: ENABLE or DISABLE.
351 * Return : None
352 *******************************************************************************/
RCC_ITConfig(uint8_t RCC_IT,FunctionalState NewState)353 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
354 {
355 if (NewState != DISABLE)
356 {
357 *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT;
358 }
359 else
360 {
361 *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
362 }
363 }
364
365 /*******************************************************************************
366 * Function Name : RCC_USBCLKConfig
367 * Description : Configures the USB clock (USBCLK).
368 * Input : RCC_USBCLKSource: specifies the USB clock source. This clock is
369 * derived from the PLL output.
370 * RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
371 * clock source.
372 * RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source.
373 * Return : None
374 *******************************************************************************/
RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)375 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
376 {
377 *(__IO uint32_t *) CFGR0_USBPRE_BB = RCC_USBCLKSource;
378 }
379
380 /*******************************************************************************
381 * Function Name : RCC_ADCCLKConfig
382 * Description : Configures the ADC clock (ADCCLK).
383 * Input : RCC_PCLK2: defines the ADC clock divider. This clock is derived from
384 * the APB2 clock (PCLK2).
385 * RCC_PCLK2_Div2: ADC clock = PCLK2/2.
386 * RCC_PCLK2_Div4: ADC clock = PCLK2/4.
387 * RCC_PCLK2_Div6: ADC clock = PCLK2/6.
388 * RCC_PCLK2_Div8: ADC clock = PCLK2/8.
389 * Return : None
390 ********************************************************************************/
RCC_ADCCLKConfig(uint32_t RCC_PCLK2)391 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
392 {
393 uint32_t tmpreg = 0;
394
395 tmpreg = RCC->CFGR0;
396 tmpreg &= CFGR0_ADCPRE_Reset_Mask;
397 tmpreg |= RCC_PCLK2;
398 RCC->CFGR0 = tmpreg;
399 }
400
401 /*******************************************************************************
402 * Function Name : RCC_LSEConfig
403 * Description : Configures the External Low Speed oscillator (LSE).
404 * Input : RCC_LSE: specifies the new state of the LSE.
405 * RCC_LSE_OFF: LSE oscillator OFF.
406 * RCC_LSE_ON: LSE oscillator ON.
407 * RCC_LSE_Bypass: LSE oscillator bypassed with external clock.
408 * Return : None
409 ********************************************************************************/
RCC_LSEConfig(uint8_t RCC_LSE)410 void RCC_LSEConfig(uint8_t RCC_LSE)
411 {
412 *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
413 *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
414
415 switch(RCC_LSE)
416 {
417 case RCC_LSE_ON:
418 *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON;
419 break;
420
421 case RCC_LSE_Bypass:
422 *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
423 break;
424
425 default:
426 break;
427 }
428 }
429
430 /*******************************************************************************
431 * Function Name : RCC_LSICmd
432 * Description : Enables or disables the Internal Low Speed oscillator (LSI).
433 * Input : NewState: ENABLE or DISABLE.
434 * Return : None
435 ********************************************************************************/
RCC_LSICmd(FunctionalState NewState)436 void RCC_LSICmd(FunctionalState NewState)
437 {
438 *(__IO uint32_t *) RSTSCKR_LSION_BB = (uint32_t)NewState;
439 }
440
441 /*******************************************************************************
442 * Function Name : RCC_RTCCLKConfig
443 * Description : Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
444 * Input : RCC_RTCCLKSource: specifies the RTC clock source.
445 * RCC_RTCCLKSource_LSE: LSE selected as RTC clock.
446 * RCC_RTCCLKSource_LSI: LSI selected as RTC clock.
447 * RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock.
448 * Return : None
449 ********************************************************************************/
RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)450 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
451 {
452 RCC->BDCTLR |= RCC_RTCCLKSource;
453 }
454
455 /*******************************************************************************
456 * Function Name : RCC_RTCCLKCmd
457 * Description : This function must be used only after the RTC clock was selected
458 * using the RCC_RTCCLKConfig function.
459 * Input : NewState: ENABLE or DISABLE.
460 * Return : None
461 ********************************************************************************/
RCC_RTCCLKCmd(FunctionalState NewState)462 void RCC_RTCCLKCmd(FunctionalState NewState)
463 {
464 *(__IO uint32_t *) BDCTLR_RTCEN_BB = (uint32_t)NewState;
465 }
466
467 /*******************************************************************************
468 * Function Name : RCC_GetClocksFreq
469 * Description : RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
470 * the clocks frequencies.
471 * Input : The result of this function could be not correct when using
472 * fractional value for HSE crystal.
473 * Return : None
474 ********************************************************************************/
RCC_GetClocksFreq(RCC_ClocksTypeDef * RCC_Clocks)475 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
476 {
477 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
478
479 tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
480
481 switch (tmp)
482 {
483 case 0x00:
484 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
485 break;
486
487 case 0x04:
488 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
489 break;
490
491 case 0x08:
492 pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
493 pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
494 pllmull = ( pllmull >> 18) + 2;
495
496 if (pllsource == 0x00)
497 {
498 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
499 }
500 else
501 {
502 if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
503 {
504 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
505 }
506 else
507 {
508 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
509 }
510 }
511 break;
512
513 default:
514 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
515 break;
516 }
517
518 tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
519 tmp = tmp >> 4;
520 presc = APBAHBPrescTable[tmp];
521 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
522 tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
523 tmp = tmp >> 8;
524 presc = APBAHBPrescTable[tmp];
525 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
526 tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
527 tmp = tmp >> 11;
528 presc = APBAHBPrescTable[tmp];
529 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
530 tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
531 tmp = tmp >> 14;
532 presc = ADCPrescTable[tmp];
533 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
534 }
535
536 /*******************************************************************************
537 * Function Name : RCC_AHBPeriphClockCmd
538 * Description : Enables or disables the AHB peripheral clock.
539 * Input : RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
540 * RCC_AHBPeriph_DMA1.
541 * RCC_AHBPeriph_DMA2.
542 * RCC_AHBPeriph_SRAM.
543 * RCC_AHBPeriph_FLITF.
544 * RCC_AHBPeriph_CRC.
545 * NewState: ENABLE or DISABLE.
546 * Return : None
547 *******************************************************************************/
RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph,FunctionalState NewState)548 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
549 {
550 if (NewState != DISABLE)
551 {
552 RCC->AHBPCENR |= RCC_AHBPeriph;
553 }
554 else
555 {
556 RCC->AHBPCENR &= ~RCC_AHBPeriph;
557 }
558 }
559
560 /*******************************************************************************
561 * Function Name : RCC_APB2PeriphClockCmd
562 * Description : Enables or disables the High Speed APB (APB2) peripheral clock.
563 * Input : RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
564 * RCC_APB2Periph_AFIO.
565 * RCC_APB2Periph_GPIOA.
566 * RCC_APB2Periph_GPIOB.
567 * RCC_APB2Periph_GPIOC.
568 * RCC_APB2Periph_GPIOD.
569 * RCC_APB2Periph_ADC1.
570 * RCC_APB2Periph_TIM1.
571 * RCC_APB2Periph_SPI1.
572 * RCC_APB2Periph_USART1.
573 * NewState: ENABLE or DISABLE
574 * Return : None
575 *******************************************************************************/
RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)576 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
577 {
578 if (NewState != DISABLE)
579 {
580 RCC->APB2PCENR |= RCC_APB2Periph;
581 }
582 else
583 {
584 RCC->APB2PCENR &= ~RCC_APB2Periph;
585 }
586 }
587
588 /*******************************************************************************
589 * Function Name : RCC_APB1PeriphClockCmd
590 * Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
591 * Input : RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
592 * RCC_APB1Periph_TIM2.
593 * RCC_APB1Periph_TIM3.
594 * RCC_APB1Periph_TIM4.
595 * RCC_APB1Periph_WWDG.
596 * RCC_APB1Periph_SPI2.
597 * RCC_APB1Periph_USART2.
598 * RCC_APB1Periph_USART3.
599 * RCC_APB1Periph_I2C1.
600 * RCC_APB1Periph_I2C2.
601 * RCC_APB1Periph_USB.
602 * RCC_APB1Periph_CAN1.
603 * RCC_APB1Periph_BKP.
604 * RCC_APB1Periph_PWR.
605 * RCC_APB1Periph_DAC.
606 * NewState: ENABLE or DISABLE.
607 * Return : None
608 *******************************************************************************/
RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)609 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
610 {
611 if (NewState != DISABLE)
612 {
613 RCC->APB1PCENR |= RCC_APB1Periph;
614 }
615 else
616 {
617 RCC->APB1PCENR &= ~RCC_APB1Periph;
618 }
619 }
620
621 /*******************************************************************************
622 * Function Name : RCC_APB2PeriphResetCmd
623 * Description : Forces or releases High Speed APB (APB2) peripheral reset.
624 * Input : RCC_APB2Periph: specifies the APB2 peripheral to reset.
625 * RCC_APB2Periph_AFIO.
626 * RCC_APB2Periph_GPIOA.
627 * RCC_APB2Periph_GPIOB.
628 * RCC_APB2Periph_GPIOC.
629 * RCC_APB2Periph_GPIOD.
630 * RCC_APB2Periph_ADC1.
631 * RCC_APB2Periph_TIM1.
632 * RCC_APB2Periph_SPI1.
633 * RCC_APB2Periph_USART1.
634 * NewState: ENABLE or DISABLE.
635 * Return : None
636 *******************************************************************************/
RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)637 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
638 {
639 if (NewState != DISABLE)
640 {
641 RCC->APB2PRSTR |= RCC_APB2Periph;
642 }
643 else
644 {
645 RCC->APB2PRSTR &= ~RCC_APB2Periph;
646 }
647 }
648
649 /*******************************************************************************
650 * Function Name : RCC_APB1PeriphResetCmd
651 * Description : Forces or releases Low Speed APB (APB1) peripheral reset.
652 * Input : RCC_APB1Periph: specifies the APB1 peripheral to reset.
653 * RCC_APB1Periph_TIM2.
654 * RCC_APB1Periph_TIM3.
655 * RCC_APB1Periph_TIM4.
656 * RCC_APB1Periph_WWDG.
657 * RCC_APB1Periph_SPI2.
658 * RCC_APB1Periph_USART2.
659 * RCC_APB1Periph_USART3.
660 * RCC_APB1Periph_I2C1.
661 * RCC_APB1Periph_I2C2.
662 * RCC_APB1Periph_USB.
663 * RCC_APB1Periph_CAN1.
664 * RCC_APB1Periph_BKP.
665 * RCC_APB1Periph_PWR.
666 * RCC_APB1Periph_DAC.
667 * NewState: ENABLE or DISABLE.
668 * Return : None
669 *******************************************************************************/
RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)670 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
671 {
672 if (NewState != DISABLE)
673 {
674 RCC->APB2PRSTR |= RCC_APB1Periph;
675 }
676 else
677 {
678 RCC->APB2PRSTR &= ~RCC_APB1Periph;
679 }
680 }
681
682 /*******************************************************************************
683 * Function Name : RCC_BackupResetCmd
684 * Description : Forces or releases the Backup domain reset.
685 * Input : NewState: ENABLE or DISABLE.
686 * Return : None
687 *******************************************************************************/
RCC_BackupResetCmd(FunctionalState NewState)688 void RCC_BackupResetCmd(FunctionalState NewState)
689 {
690 *(__IO uint32_t *) BDCTLR_BDRST_BB = (uint32_t)NewState;
691 }
692
693 /*******************************************************************************
694 * Function Name : RCC_ClockSecuritySystemCmd
695 * Description : Enables or disables the Clock Security System.
696 * Input : NewState: ENABLE or DISABLE.
697 * Return : None
698 *******************************************************************************/
RCC_ClockSecuritySystemCmd(FunctionalState NewState)699 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
700 {
701 *(__IO uint32_t *) CTLR_CSSON_BB = (uint32_t)NewState;
702 }
703
704 /*******************************************************************************
705 * Function Name : RCC_MCOConfig
706 * Description : Selects the clock source to output on MCO pin.
707 * Input : RCC_MCO: specifies the clock source to output.
708 * RCC_MCO_NoClock: No clock selected.
709 * RCC_MCO_SYSCLK: System clock selected.
710 * RCC_MCO_HSI: HSI oscillator clock selected.
711 * RCC_MCO_HSE: HSE oscillator clock selected.
712 * RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected.
713 * Return : None
714 *******************************************************************************/
RCC_MCOConfig(uint8_t RCC_MCO)715 void RCC_MCOConfig(uint8_t RCC_MCO)
716 {
717 *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO;
718 }
719
720 /*******************************************************************************
721 * Function Name : RCC_GetFlagStatus
722 * Description : Checks whether the specified RCC flag is set or not.
723 * Input : RCC_FLAG: specifies the flag to check.
724 * RCC_FLAG_HSIRDY: HSI oscillator clock ready.
725 * RCC_FLAG_HSERDY: HSE oscillator clock ready.
726 * RCC_FLAG_PLLRDY: PLL clock ready.
727 * RCC_FLAG_LSERDY: LSE oscillator clock ready.
728 * RCC_FLAG_LSIRDY: LSI oscillator clock ready.
729 * RCC_FLAG_PINRST: Pin reset.
730 * RCC_FLAG_PORRST: POR/PDR reset.
731 * RCC_FLAG_SFTRST: Software reset.
732 * RCC_FLAG_IWDGRST: Independent Watchdog reset.
733 * RCC_FLAG_WWDGRST: Window Watchdog reset.
734 * RCC_FLAG_LPWRRST: Low Power reset.
735 * Return : FlagStatus: SET or RESET.
736 *******************************************************************************/
RCC_GetFlagStatus(uint8_t RCC_FLAG)737 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
738 {
739 uint32_t tmp = 0;
740 uint32_t statusreg = 0;
741
742 FlagStatus bitstatus = RESET;
743 tmp = RCC_FLAG >> 5;
744
745 if (tmp == 1)
746 {
747 statusreg = RCC->CTLR;
748 }
749 else if (tmp == 2)
750 {
751 statusreg = RCC->BDCTLR;
752 }
753 else
754 {
755 statusreg = RCC->RSTSCKR;
756 }
757
758 tmp = RCC_FLAG & FLAG_Mask;
759
760 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
761 {
762 bitstatus = SET;
763 }
764 else
765 {
766 bitstatus = RESET;
767 }
768
769 return bitstatus;
770 }
771
772 /*******************************************************************************
773 * Function Name : RCC_ClearFlag
774 * Description : Clears the RCC reset flags.
775 * Input : None
776 * Return : None
777 *******************************************************************************/
RCC_ClearFlag(void)778 void RCC_ClearFlag(void)
779 {
780 RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
781 }
782
783 /*******************************************************************************
784 * Function Name : RCC_GetITStatus
785 * Description : Checks whether the specified RCC interrupt has occurred or not.
786 * Input : RCC_IT: specifies the RCC interrupt source to check.
787 * RCC_IT_LSIRDY: LSI ready interrupt.
788 * RCC_IT_LSERDY: LSE ready interrupt.
789 * RCC_IT_HSIRDY: HSI ready interrupt.
790 * RCC_IT_HSERDY: HSE ready interrupt.
791 * RCC_IT_PLLRDY: PLL ready interrupt.
792 * RCC_IT_CSS: Clock Security System interruptt.
793 * Return : ITStatus: SET or RESET.
794 *******************************************************************************/
RCC_GetITStatus(uint8_t RCC_IT)795 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
796 {
797 ITStatus bitstatus = RESET;
798
799 if ((RCC->INTR & RCC_IT) != (uint32_t)RESET)
800 {
801 bitstatus = SET;
802 }
803 else
804 {
805 bitstatus = RESET;
806 }
807
808 return bitstatus;
809 }
810
811 /*******************************************************************************
812 * Function Name : RCC_ClearITPendingBit
813 * Description : Clears the RCC's interrupt pending bits.
814 * Input : RCC_IT: specifies the interrupt pending bit to clear.
815 * RCC_IT_LSIRDY: LSI ready interrupt.
816 * RCC_IT_LSERDY: LSE ready interrupt.
817 * RCC_IT_HSIRDY: HSI ready interrupt.
818 * RCC_IT_HSERDY: HSE ready interrupt.
819 * RCC_IT_PLLRDY: PLL ready interrupt.
820 * RCC_IT_CSS: Clock Security System interruptt.
821 * Return : None
822 *******************************************************************************/
RCC_ClearITPendingBit(uint8_t RCC_IT)823 void RCC_ClearITPendingBit(uint8_t RCC_IT)
824 {
825 *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT;
826 }
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