1 /**
2 ******************************************************************************
3 * @file tae32f53xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL Module Driver.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© Copyright (c) 2020 Tai-Action.
11 * All rights reserved.</center></h2>
12 *
13 * This software is licensed by Tai-Action under BSD 3-Clause license,
14 * the "License"; You may not use this file except in compliance with the
15 * License. You may obtain a copy of the License at:
16 * opensource.org/licenses/BSD-3-Clause
17 *
18 ******************************************************************************
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "tae32f53xx_ll.h"
23
24
25 #define DBG_TAG "DMA LL"
26 #define DBG_LVL DBG_ERROR
27 #include "dbg/tae32f53xx_dbg.h"
28
29
30 /** @addtogroup TAE32F53xx_LL_Driver
31 * @{
32 */
33
34 /** @defgroup DMA_LL DMA LL
35 * @brief DMA LL module driver
36 * @{
37 */
38
39 #ifdef LL_DMA_MODULE_ENABLED
40
41 /* Private define ------------------------------------------------------------*/
42 /* Private typedef -----------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Types DMA LL Private Types
44 * @brief DMA LL Private Types
45 * @{
46 */
47
48 /**
49 * @brief DMA LL config type definition
50 */
51 typedef struct __DMA_LLCfgTypeDef {
52 DMA_SrcBurstLenETypeDef src_burst; /*!< source burst length */
53 DMA_DstBurstLenETypeDef dst_burst; /*!< destinationd burst length */
54 uint16_t max_burst;
55 } DMA_LLCfgTypeDef;
56
57 /**
58 * @brief DMA channel control type definition
59 */
60 typedef struct __DMA_ChCtrlTypeDef {
61 DMA_StateETypeDef state; /*!< channel state */
62 void *end_arg; /*!< argument of transfer complete callback fucntion */
63 DMA_IRQCallback end_callback; /*!< transfer complete callback fucntion */
64 void *err_arg; /*!< argument of transfer error callback fucntion */
65 DMA_IRQCallback err_callback; /*!< transfer error callback fucntion */
66 } DMA_ChCtrlTypeDef;
67
68 /**
69 * @brief DMA Private control type definition
70 */
71 typedef struct __DMA_PriCtrlTypeDef {
72 uint8_t ch_used; /*!< channel used variable */
73 DMA_ChCtrlTypeDef ch_ctrl[DMA_CHN_NB]; /*!< channel control params */
74 } DMA_PriCtrlTypeDef;
75
76 /**
77 * @}
78 */
79
80 /* Private variables ---------------------------------------------------------*/
81 /** @defgroup DMA_LL_Private_Variables DMA LL Private Variables
82 * @brief DMA LL Private Variables
83 * @{
84 */
85
86 /**
87 * @brief DMA LL config default
88 */
89 static const DMA_LLCfgTypeDef dma_ll_cfg_def = {
90 .src_burst = DMA_SRC_BURST_LEN_1, /*!< source burst default 1 */
91 .dst_burst = DMA_DST_BURST_LEN_1, /*!< destination burst default 1 */
92 .max_burst = 0x0, /*!< max burst defalut 0x0 (no limit) */
93 };
94
95
96 /**
97 * @brief DMA private control global variable
98 */
99 static DMA_PriCtrlTypeDef dma_pri_ctrl;
100
101 /**
102 * @}
103 */
104
105
106 /* Private macro -------------------------------------------------------------*/
107 /* Private function prototypes -----------------------------------------------*/
108 /* Exported functions --------------------------------------------------------*/
109 /** @defgroup DMA_LL_Exported_Functions DMA LL Exported Functions
110 * @brief DMA LL Exported Functions
111 * @{
112 */
113
114 /** @defgroup DMA_LL_Exported_Functions_Group1 DMA Init Function
115 * @brief DMA Init function
116 * @{
117 */
118
119 /**
120 * @brief DMA LL init
121 * @param Instance Specifies DMA peripheral
122 * @param ch channel to init
123 * @param user_cfg user config pointer
124 * @return Status of the Initialization
125 */
LL_DMA_Init(DMA_TypeDef * Instance,DMA_ChannelETypeDef ch,DMA_UserCfgTypeDef * user_cfg)126 LL_StatusETypeDef LL_DMA_Init(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, DMA_UserCfgTypeDef *user_cfg)
127 {
128 DMA_LLCfgTypeDef *ll_cfg = (DMA_LLCfgTypeDef *)&dma_ll_cfg_def;
129
130 //Check config params to be valid
131 if (Instance == NULL || ch >= DMA_CHANNEL_NUM || user_cfg == NULL) {
132 LOG_E("Init Params config error!\n");
133 return LL_ERROR;
134 }
135
136 //Burst config
137 __LL_DMA_SrcBurstLen_Set(Instance, ch, ll_cfg->src_burst);
138 __LL_DMA_DstBurstLen_Set(Instance, ch, ll_cfg->dst_burst);
139 __LL_DMA_BurstLenMax_Set(Instance, ch, ll_cfg->max_burst);
140
141 //User config
142 __LL_DMA_TransType_Set(Instance, ch, user_cfg->trans_type);
143 __LL_DMA_SrcAddrMode_Set(Instance, ch, user_cfg->src_addr_mode);
144 __LL_DMA_DstAddrMode_Set(Instance, ch, user_cfg->dst_addr_mode);
145 __LL_DMA_SrcTransWidth_Set(Instance, ch, user_cfg->src_data_width);
146 __LL_DMA_DstTransWidth_Set(Instance, ch, user_cfg->dst_data_width);
147
148 //Source and destination handshake mode config
149 if (user_cfg->trans_type == DMA_TRANS_TYPE_P2M || user_cfg->trans_type == DMA_TRANS_TYPE_P2P) {
150 __LL_DMA_SrcHandshakeMode_Clr(Instance, ch);
151 } else {
152 __LL_DMA_SrcHandshakeMode_Set(Instance, ch);
153 }
154
155 if (user_cfg->trans_type == DMA_TRANS_TYPE_M2P || user_cfg->trans_type == DMA_TRANS_TYPE_P2P) {
156 __LL_DMA_DstHandshakeMode_Clr(Instance, ch);
157 } else {
158 __LL_DMA_DstHandshakeMode_Set(Instance, ch);
159 }
160
161 //Channel priority config to default
162 if (ch == DMA_CHANNEL_0) {
163 __LL_DMA_ChannelPriLow_Set(Instance, ch);
164 } else if (ch == DMA_CHANNEL_1) {
165 __LL_DMA_ChannelPriHigh_Set(Instance, ch);
166 }
167
168 //Source and destination handshake interface config
169 if (user_cfg->src_hs_ifc != DMA_SRC_HANDSHAKE_IFC_MEMORY) {
170 __LL_DMA_SrcHandshakeIfc_Set(Instance, ch, user_cfg->src_hs_ifc);
171 }
172
173 if (user_cfg->dst_hs_ifc != DMA_DST_HANDSHAKE_IFC_MEMORY) {
174 __LL_DMA_DstHandshakeIfc_Set(Instance, ch, user_cfg->dst_hs_ifc);
175 }
176
177 //Peripheral enable
178 __LL_DMA_Periph_En(Instance);
179
180 //IRQ callback config
181 dma_pri_ctrl.ch_ctrl[ch].end_callback = user_cfg->end_callback;
182 dma_pri_ctrl.ch_ctrl[ch].end_arg = user_cfg->end_arg;
183 dma_pri_ctrl.ch_ctrl[ch].err_callback = user_cfg->err_callback;
184 dma_pri_ctrl.ch_ctrl[ch].err_arg = user_cfg->err_arg;
185
186 //Update channel state to Ready
187 dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_READY;
188
189 return LL_OK;
190 }
191
192 /**
193 * @brief DMA LL deinit
194 * @param Instance Specifies DMA peripheral
195 * @param ch channel to deinit
196 * @return Status of the DeInitialization
197 */
LL_DMA_DeInit(DMA_TypeDef * Instance,DMA_ChannelETypeDef ch)198 LL_StatusETypeDef LL_DMA_DeInit(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch)
199 {
200 uint8_t i;
201
202 //Check config params to be valid
203 if (Instance == NULL || ch >= DMA_CHANNEL_NUM) {
204 LOG_E("Deinit Params config error!\n");
205 return LL_ERROR;
206 }
207
208 //IRQ callback deinit
209 dma_pri_ctrl.ch_ctrl[ch].end_callback = NULL;
210 dma_pri_ctrl.ch_ctrl[ch].end_arg = NULL;
211 dma_pri_ctrl.ch_ctrl[ch].err_callback = NULL;
212 dma_pri_ctrl.ch_ctrl[ch].err_arg = NULL;
213
214 //Update channel state to Reset
215 dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_RESET;
216
217 //Peripheral disable when all channels close
218 for (i = 0; i < DMA_CHANNEL_NUM; i++) {
219 if (dma_pri_ctrl.ch_ctrl[i].state != DMA_STATE_RESET) {
220 break;
221 }
222 }
223
224 if (i == DMA_CHANNEL_NUM) {
225 __LL_DMA_Periph_Dis(Instance);
226 }
227
228 return LL_OK;
229 }
230
231 /**
232 * @}
233 */
234
235
236 /** @defgroup DMA_LL_Exported_Functions_Group2 DMA Channel Management Functions
237 * @brief DMA Channel Management Functions
238 * @{
239 */
240
241 /**
242 * @brief DMA LL channel request
243 * @param None
244 * @return DMA_ChannelETypeDef
245 */
LL_DMA_ChannelRequest(void)246 DMA_ChannelETypeDef LL_DMA_ChannelRequest(void)
247 {
248 uint8_t i;
249 DMA_ChannelETypeDef avl_ch = DMA_CHANNEL_INVALID;
250
251 //Search available channel
252 for (i = 0; i < DMA_CHANNEL_NUM; i++) {
253 if (!READ_BIT(dma_pri_ctrl.ch_used, BIT(i)) && (dma_pri_ctrl.ch_ctrl[i].state == DMA_STATE_RESET)) {
254 SET_BIT(dma_pri_ctrl.ch_used, BIT(i));
255 avl_ch = (DMA_ChannelETypeDef)i;
256 break;
257 }
258 }
259
260 return avl_ch;
261 }
262
263 /**
264 * @brief DMA LL request specific channel
265 * @param ch specific channel to request
266 * @return DMA_ChannelETypeDef
267 */
LL_DMA_ChReqSpecific(DMA_ChannelETypeDef ch)268 DMA_ChannelETypeDef LL_DMA_ChReqSpecific(DMA_ChannelETypeDef ch)
269 {
270 if (ch < DMA_CHANNEL_NUM && !READ_BIT(dma_pri_ctrl.ch_used, BIT(ch)) && (dma_pri_ctrl.ch_ctrl[ch].state == DMA_STATE_RESET)) {
271 SET_BIT(dma_pri_ctrl.ch_used, BIT(ch));
272 } else {
273 ch = DMA_CHANNEL_INVALID;
274 }
275
276 return ch;
277 }
278
279 /**
280 * @brief DMA LL channel release
281 * @param ch channel to release
282 * @return None
283 */
LL_DMA_ChannelRelease(DMA_ChannelETypeDef ch)284 void LL_DMA_ChannelRelease(DMA_ChannelETypeDef ch)
285 {
286 if (dma_pri_ctrl.ch_ctrl[ch].state == DMA_STATE_RESET) {
287 CLEAR_BIT(dma_pri_ctrl.ch_used, BIT(ch));
288 }
289 }
290 /**
291 * @}
292 */
293
294
295 /** @defgroup DMA_LL_Exported_Functions_Group3 DMA Start and Stop Functions
296 * @brief DMA Start and Stop Functions
297 * @{
298 */
299
300 /**
301 * @brief DMA LL start in CPU mode
302 * @param Instance Specifies DMA peripheral
303 * @param ch channel to start
304 * @param src_addr source address
305 * @param dst_addr destination address
306 * @param data_len transfer data length
307 * @return LL_StatusETypeDef
308 */
LL_DMA_Start_CPU(DMA_TypeDef * Instance,DMA_ChannelETypeDef ch,uint32_t src_addr,uint32_t dst_addr,uint32_t data_len)309 LL_StatusETypeDef LL_DMA_Start_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch,
310 uint32_t src_addr, uint32_t dst_addr, uint32_t data_len)
311 {
312 uint8_t src_data_width;
313 uint32_t block_size;
314
315 if (ch >= DMA_CHANNEL_NUM) {
316 LOG_E("Invalid ch-[%d]!\n", ch);
317 return LL_ERROR;
318 }
319
320 //Config block size, which is associate to data length
321 src_data_width = __LL_DMA_SrcTransWidth_Get(Instance, ch);
322
323 if (src_data_width > 2) {
324 LOG_E("Source data width config error-[%d]!\n", src_data_width);
325 return LL_ERROR;
326 }
327
328 src_data_width = BIT(src_data_width);
329 block_size = data_len / src_data_width;
330
331 if (block_size > LL_DMA_BLOCK_SIZE_MAX) {
332 LOG_E("Block size max is %d, while now is %d!\n", LL_DMA_BLOCK_SIZE_MAX, block_size);
333 return LL_ERROR;
334 }
335
336 __LL_DMA_BlockTransCnt_Set(Instance, ch, block_size);
337
338 //Check and update channel state
339 if (dma_pri_ctrl.ch_ctrl[ch].state != DMA_STATE_READY) {
340 LOG_E("Channel state-[%d] isn't in Ready!\n", dma_pri_ctrl.ch_ctrl[ch].state);
341 return LL_ERROR;
342 }
343
344 dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_BUSY;
345
346 //Config source and destination peripheral bus master 1/2
347 if (src_addr >= LL_DMA_SRMBC_ADDR_START && src_addr <= LL_DMA_SRMBC_ADDR_END) { //SRAMB & SRAMC
348 __LL_DMA_SrcPeriphBus_Set(Instance, ch, DMA_SRC_PERIPH_BUS_AHB_MST2);
349 } else { //SRAMA & Peripheral & Flash
350 __LL_DMA_SrcPeriphBus_Set(Instance, ch, DMA_SRC_PERIPH_BUS_AHB_MST1);
351 }
352
353 if (dst_addr >= LL_DMA_SRMBC_ADDR_START && dst_addr <= LL_DMA_SRMBC_ADDR_END) { //SRAMB & SRAMC
354 __LL_DMA_DstPeriphBus_Set(Instance, ch, DMA_DST_PERIPH_BUS_AHB_MST2);
355 } else { //SRAMA & Peripheral & Flash
356 __LL_DMA_DstPeriphBus_Set(Instance, ch, DMA_DST_PERIPH_BUS_AHB_MST1);
357 }
358
359 //source and destination address config
360 __LL_DMA_SrcAddr_Set(Instance, ch, src_addr);
361 __LL_DMA_DstAddr_Set(Instance, ch, dst_addr);
362
363 //Channel enable
364 if (ch == DMA_CHANNEL_0) {
365 __LL_DMA_Ch0_En(Instance);
366 } else if (ch == DMA_CHANNEL_1) {
367 __LL_DMA_Ch1_En(Instance);
368 }
369
370 return LL_OK;
371 }
372
373 /**
374 * @brief DMA LL start in interrupt mode
375 * @param Instance Specifies DMA peripheral
376 * @param ch channel to start
377 * @param src_addr source address
378 * @param dst_addr destination address
379 * @param data_len transfer data length
380 * @return LL_StatusETypeDef
381 */
LL_DMA_Start_IT(DMA_TypeDef * Instance,DMA_ChannelETypeDef ch,uint32_t src_addr,uint32_t dst_addr,uint32_t data_len)382 LL_StatusETypeDef LL_DMA_Start_IT(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch,
383 uint32_t src_addr, uint32_t dst_addr, uint32_t data_len)
384 {
385 //Channel interrupt enable
386 __LL_DMA_Channel_Int_En(Instance, ch);
387
388 //Channel transfer complete and error interrupt enable
389 if (ch == DMA_CHANNEL_0) {
390 __LL_DMA_Ch0TransCom_Int_En(Instance);
391 __LL_DMA_Ch0TransErr_Int_En(Instance);
392 } else if (ch == DMA_CHANNEL_1) {
393 __LL_DMA_Ch1TransCom_Int_En(Instance);
394 __LL_DMA_Ch1TransErr_Int_En(Instance);
395 }
396
397 return LL_DMA_Start_CPU(Instance, ch, src_addr, dst_addr, data_len);
398 }
399
400 /**
401 * @brief DMA LL Stop in CPU mode
402 * @param Instance Specifies DMA peripheral
403 * @param ch channel to stop
404 * @return LL_StatusETypeDef
405 */
LL_DMA_Stop_CPU(DMA_TypeDef * Instance,DMA_ChannelETypeDef ch)406 LL_StatusETypeDef LL_DMA_Stop_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch)
407 {
408 //Check and update channel state
409 if (dma_pri_ctrl.ch_ctrl[ch].state == DMA_STATE_RESET) {
410 LOG_E("Channel state is in RESET!\n");
411 return LL_ERROR;
412 }
413
414 dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_READY;
415
416 //Channel disable
417 if (ch == DMA_CHANNEL_0) {
418 __LL_DMA_Ch0_Dis(Instance);
419 } else if (ch == DMA_CHANNEL_1) {
420 __LL_DMA_Ch1_Dis(Instance);
421 }
422
423 return LL_OK;
424 }
425
426 /**
427 * @brief DMA LL Stop in interrupt mode
428 * @param Instance Specifies DMA peripheral
429 * @param ch channel to stop
430 * @return LL_StatusETypeDef
431 */
LL_DMA_Stop_IT(DMA_TypeDef * Instance,DMA_ChannelETypeDef ch)432 LL_StatusETypeDef LL_DMA_Stop_IT(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch)
433 {
434 LL_StatusETypeDef ret;
435
436 ret = LL_DMA_Stop_CPU(Instance, ch);
437
438 if (ret != LL_OK) {
439 return ret;
440 }
441
442 //Channel interrupt disable
443 __LL_DMA_Channel_Int_Dis(Instance, ch);
444
445 //Channel transfer complete and error interrupt disable
446 if (ch == DMA_CHANNEL_0) {
447 __LL_DMA_Ch0TransCom_Int_Dis(Instance);
448 __LL_DMA_Ch0TransErr_Int_Dis(Instance);
449 } else if (ch == DMA_CHANNEL_1) {
450 __LL_DMA_Ch1TransCom_Int_Dis(Instance);
451 __LL_DMA_Ch1TransErr_Int_Dis(Instance);
452 }
453
454 return LL_OK;
455 }
456
457 /**
458 * @brief DMA LL wait for transfer complete in CPU mode
459 * @param Instance Specifies DMA peripheral
460 * @param ch channel to wait for transfer complete
461 * @return LL_StatusETypeDef
462 */
LL_DMA_WaitComplete_CPU(DMA_TypeDef * Instance,DMA_ChannelETypeDef ch,uint32_t timeout)463 LL_StatusETypeDef LL_DMA_WaitComplete_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, uint32_t timeout)
464 {
465 uint32_t tickstart;
466 LL_StatusETypeDef ret = LL_ERROR;
467
468 //Check channel state
469 if (dma_pri_ctrl.ch_ctrl[ch].state != DMA_STATE_BUSY) {
470 LOG_E("Channel state-[%d] isn't in Busy!\n", dma_pri_ctrl.ch_ctrl[ch].state);
471 return LL_ERROR;
472 }
473
474 tickstart = LL_GetTick();
475
476 switch (ch) {
477 case DMA_CHANNEL_0:
478 while (!__LL_DMA_Ch0TransErrSta_Get(Instance)) { //transfer normal, no error
479 if (__LL_DMA_Ch0TransComSta_Get(Instance)) { //transfer complete
480 //Clear complete status
481 __LL_DMA_Ch0TransComSta_Clr(Instance);
482 ret = LL_OK;
483 break;
484 }
485
486 if ((LL_GetTick() - tickstart) > timeout) { //transfer timeout
487 ret = LL_TIMEOUT;
488 break;
489 }
490 }
491
492 //Clear error status
493 __LL_DMA_Ch0TransErrSta_Clr(Instance);
494
495 //Update channel state to Ready
496 dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_READY;
497
498 break;
499
500 case DMA_CHANNEL_1:
501 while (!__LL_DMA_Ch1TransErrSta_Get(Instance)) { //transfer normal, no error
502 if (__LL_DMA_Ch1TransComSta_Get(Instance)) { //transfer complete
503 //Clear complete status
504 __LL_DMA_Ch1TransComSta_Clr(Instance);
505 ret = LL_OK;
506 break;
507 }
508
509 if ((LL_GetTick() - tickstart) > timeout) { //transfer timeout
510 ret = LL_TIMEOUT;
511 break;
512 }
513 }
514
515 //Clear error status
516 __LL_DMA_Ch1TransErrSta_Clr(Instance);
517
518 //Update channel state to Ready
519 dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_READY;
520
521 break;
522
523 default:
524 break;;
525 }
526
527 return ret;
528 }
529
530 /**
531 * @}
532 */
533
534
535 /** @defgroup DMA_LL_Exported_Functions_Interrupt DMA Interrupt handler and call back
536 * @brief DMA Interrupt handler and call back
537 * @{
538 */
539
540 /**
541 * @brief DMA IRQ Handler
542 * @param Instance Specifies DMA peripheral
543 * @return None
544 */
LL_DMA_IRQHandler(DMA_TypeDef * Instance)545 void LL_DMA_IRQHandler(DMA_TypeDef *Instance)
546 {
547 //Transfer complete interrupt handler
548 if (__LL_DMA_Ch0TransComIntSta_Get(Instance)) { //Channel 0 transfer complete interrupt
549 //Disable interrupt in single mode
550 __LL_DMA_Ch0TransCom_Int_Dis(Instance);
551 __LL_DMA_Ch0TransErr_Int_Dis(Instance);
552
553 //Clear pending
554 __LL_DMA_Ch0TransComSta_Clr(Instance);
555
556 //Update channel state to Ready
557 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
558
559 //Interrupt callback
560 if (dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].end_callback) {
561 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].end_callback(dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].end_arg);
562 }
563
564 }
565
566 if (__LL_DMA_Ch1TransComIntSta_Get(Instance)) { //Channel 1 transfer complete interrupt
567 //Disable interrupt in single mode
568 __LL_DMA_Ch1TransCom_Int_Dis(Instance);
569 __LL_DMA_Ch1TransErr_Int_Dis(Instance);
570
571 //Clear pending
572 __LL_DMA_Ch1TransComSta_Clr(Instance);
573
574 //Update channel state to Ready
575 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
576
577 //Interrupt callback
578 if (dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].end_callback) {
579 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].end_callback(dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].end_arg);
580 }
581
582 }
583
584
585 //Transfer error interrupt handler
586 if (__LL_DMA_Ch0TransErrIntSta_Get(Instance)) { //Channel 0 transfer error interrupt
587 //Disable interrupt in single mode
588 __LL_DMA_Ch0TransCom_Int_Dis(Instance);
589 __LL_DMA_Ch0TransErr_Int_Dis(Instance);
590
591 //Clear pending
592 __LL_DMA_Ch0TransErrSta_Clr(Instance);
593
594 //Update channel state to Ready
595 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
596
597 //Interrupt callback
598 if (dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].err_callback) {
599 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].err_callback(dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].err_arg);
600 }
601
602 }
603
604 if (__LL_DMA_Ch1TransErrIntSta_Get(Instance)) { //Channel 1 transfer error interrupt
605 //Disable interrupt in single mode
606 __LL_DMA_Ch1TransCom_Int_Dis(Instance);
607 __LL_DMA_Ch1TransErr_Int_Dis(Instance);
608
609 //Clear pending
610 __LL_DMA_Ch1TransErrSta_Clr(Instance);
611
612 //Update channel state to Ready
613 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
614
615 //Interrupt callback
616 if (dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].err_callback) {
617 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].err_callback(dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].err_arg);
618 }
619
620 }
621
622
623 //Block transfer complete interrupt handler
624 if (__LL_DMA_Ch0BlockTransComIntSta_Get(Instance)) { //Channel 0 block transfer complete interrupt
625 __LL_DMA_Ch0BlockTransComSta_Clr(Instance);
626 //:TODO: according to need
627
628 //Update channel state to Ready
629 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
630 }
631
632 if (__LL_DMA_Ch1BlockTransComIntSta_Get(Instance)) { //Channel 1 block transfer complete interrupt
633 __LL_DMA_Ch1BlockTransComSta_Clr(Instance);
634 //:TODO: according to need
635
636 //Update channel state to Ready
637 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
638 }
639
640
641 //Source transfer complete interrupt handler
642 if (__LL_DMA_Ch0SrcTransComIntSta_Get(Instance)) { //Channel 0 source transfer complete interrupt
643 __LL_DMA_Ch0SrcTransComSta_Clr(Instance);
644 //:TODO: according to need
645
646 //Update channel state to Ready
647 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
648 }
649
650 if (__LL_DMA_Ch1SrcTransComIntSta_Get(Instance)) { //Channel 1 source transfer complete interrupt
651 __LL_DMA_Ch1SrcTransComSta_Clr(Instance);
652 //:TODO: according to need
653
654 //Update channel state to Ready
655 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
656 }
657
658
659 //Destination transfer complete interrupt handler
660 if (__LL_DMA_Ch0DstTransComIntSta_Get(Instance)) { //Channel 0 destination transfer complete interrupt
661 __LL_DMA_Ch0DstTransComSta_Clr(Instance);
662 //:TODO: according to need
663
664 //Update channel state to Ready
665 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
666 }
667
668 if (__LL_DMA_Ch1DstTransComIntSta_Get(Instance)) { //Channel 1 destination transfer complete interrupt
669 __LL_DMA_Ch1DstTransComSta_Clr(Instance);
670 //:TODO: according to need
671
672 //Update channel state to Ready
673 dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
674 }
675 }
676
677 /**
678 * @}
679 */
680
681 /**
682 * @}
683 */
684
685
686 /* Private functions ---------------------------------------------------------*/
687
688
689 #endif /* LL_DMA_MODULE_ENABLED */
690
691
692 /**
693 * @}
694 */
695
696 /**
697 * @}
698 */
699
700
701 /************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
702
703