1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-04-12 shelton first version 9 */ 10 11 #ifndef __DMA_CONFIG_H__ 12 #define __DMA_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* DMA1 channel1 */ 21 /* DMA1 channel2 */ 22 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) 23 #define SPI1_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler 24 #define SPI1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 25 #define SPI1_RX_DMA_CHANNEL DMA1_CHANNEL2 26 #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn 27 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_CHANNEL) 28 #define UART3_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler 29 #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 30 #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL2 31 #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn 32 #elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) 33 #define I2C3_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler 34 #define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 35 #define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL2 36 #define I2C3_TX_DMA_IRQ DMA1_Channel2_IRQn 37 #endif 38 39 /* DMA1 channel3 */ 40 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) 41 #define SPI1_TX_DMA_IRQHandler DMA1_Channel3_IRQHandler 42 #define SPI1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 43 #define SPI1_TX_DMA_CHANNEL DMA1_CHANNEL3 44 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn 45 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) 46 #define UART3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler 47 #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 48 #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL3 49 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn 50 #elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) 51 #define I2C3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler 52 #define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 53 #define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL3 54 #define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn 55 #endif 56 57 /* DMA1 channel4 */ 58 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) 59 #define SPI2_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler 60 #define SPI2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 61 #define SPI2_RX_DMA_CHANNEL DMA1_CHANNEL4 62 #define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn 63 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_CHANNEL) 64 #define UART1_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 65 #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 66 #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 67 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn 68 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) 69 #define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 70 #define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 71 #define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 72 #define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn 73 #endif 74 75 /* DMA1 channel5 */ 76 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) 77 #define SPI2_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler 78 #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 79 #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 80 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn 81 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) 82 #define UART1_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 83 #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 84 #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 85 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn 86 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) 87 #define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 88 #define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 89 #define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 90 #define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn 91 #endif 92 93 /* DMA1 channel6 */ 94 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) 95 #define UART2_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler 96 #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 97 #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 98 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn 99 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) 100 #define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler 101 #define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 102 #define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 103 #define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn 104 #endif 105 106 /* DMA1 channel7 */ 107 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_CHANNEL) 108 #define UART2_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler 109 #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 110 #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 111 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn 112 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) 113 #define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler 114 #define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 115 #define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 116 #define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn 117 #endif 118 119 /* DMA2 channel1 */ 120 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) 121 #define SPI3_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler 122 #define SPI3_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 123 #define SPI3_RX_DMA_CHANNEL DMA2_CHANNEL1 124 #define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn 125 #endif 126 127 /* DMA2 channel2 */ 128 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) 129 #define SPI3_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler 130 #define SPI3_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 131 #define SPI3_TX_DMA_CHANNEL DMA2_CHANNEL2 132 #define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn 133 #endif 134 135 /* DMA2 channel3 */ 136 #if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_CHANNEL) 137 #define SPI4_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler 138 #define SPI4_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 139 #define SPI4_RX_DMA_CHANNEL DMA2_CHANNEL3 140 #define SPI4_RX_DMA_IRQ DMA2_Channel3_IRQn 141 #elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL) 142 #define UART4_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler 143 #define UART4_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 144 #define UART4_RX_DMA_CHANNEL DMA2_CHANNEL3 145 #define UART4_RX_DMA_IRQ DMA2_Channel3_IRQn 146 #endif 147 148 /* DMA2 channel4 */ 149 /* DMA2 channel5 */ 150 #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) 151 #define SPI4_TX_DMA_IRQHandler DMA2_Channel4_5_IRQHandler 152 #define SPI4_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 153 #define SPI4_TX_DMA_CHANNEL DMA2_CHANNEL5 154 #define SPI4_TX_DMA_IRQ DMA2_Channel4_5_IRQn 155 #elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_CHANNEL) 156 #define UART4_TX_DMA_IRQHandler DMA2_Channel4_5_IRQHandler 157 #define UART4_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 158 #define UART4_TX_DMA_CHANNEL DMA2_CHANNEL5 159 #define UART4_TX_DMA_IRQ DMA2_Channel4_5_IRQn 160 #endif 161 162 #ifdef __cplusplus 163 } 164 #endif 165 166 #endif /* __DMA_CONFIG_H__ */ 167