1 /* 2 * Copyright (c) 2022 OpenLuat & AirM2M 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy of 5 * this software and associated documentation files (the "Software"), to deal in 6 * the Software without restriction, including without limitation the rights to 7 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 8 * the Software, and to permit persons to whom the Software is furnished to do so, 9 * subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in all 12 * copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 16 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 17 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 18 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22 23 #ifndef __AIR105_I2C_H 24 #define __AIR105_I2C_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "air105.h" 32 33 34 /** @defgroup I2C_mode 35 * @{ 36 */ 37 typedef enum 38 { 39 I2C_Mode_Master =((uint32_t)0x0001), 40 I2C_Mode_Slave =((uint32_t)0x0002) 41 }I2CMode_TypeDef; 42 43 #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_Master) || \ 44 ((MODE) == I2C_Mode_Slave)) 45 /** 46 * @} 47 */ 48 49 typedef struct 50 { 51 uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. */ 52 53 I2CMode_TypeDef I2C_Mode; 54 55 uint32_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. 56 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ 57 uint32_t I2C_SDASetupTime; 58 59 uint32_t I2C_SDAHoldTime; 60 61 uint32_t I2C_TargetAddress; 62 63 uint32_t I2C_TargetAddressMode; 64 65 uint32_t I2C_OwnAddress; /*!< Specifies the slave mode own address. 66 This parameter can be a 7-bit or 10-bit address. */ 67 68 uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. 69 This parameter can be a value of @ref I2C_acknowledged_address */ 70 71 uint32_t I2C_RXFIFOFullThreshold; 72 73 uint32_t I2C_TXFIFOEmptyThreshold; 74 75 FunctionalState I2C_GenerateRestartEnable; 76 }I2C_InitTypeDef; 77 78 79 typedef struct 80 { 81 uint32_t I2C_DMAReq; 82 uint32_t I2C_DMAReceiveLevel; 83 uint32_t I2C_DMATransmitLevel; 84 FunctionalState I2C_DMAEnCmd; 85 }I2C_DMAInitTypeDef; 86 87 88 #define I2C_ClockSpeed_100KHz (100000) 89 #define I2C_ClockSpeed_400KHz (400000) 90 91 92 /** @defgroup I2C_duty_cycle_in_fast_mode 93 * @{ 94 */ 95 /*Tlow/Thigh = ((I2C_DutyCycle_x_y & 0xFF00) >> 8) / (I2C_DutyCycle_x_y & 0x00FF)*/ 96 #define I2C_DutyCycle_1 ((uint16_t)0x0101) /*!< I2C standard mode Tlow/Thigh = 1 */ 97 #define I2C_DutyCycle_16_9 ((uint16_t)0x1009) /*!< I2C fast mode Tlow/Thigh = 16/9 */ 98 #define I2C_DutyCycle_2 ((uint16_t)0x0201) /*!< I2C fast mode Tlow/Thigh = 2 */ 99 #define I2C_DutyCycle_8_3 ((uint16_t)0x0803) /*!< I2C high mode Tlow/Thigh = 8/3 */ 100 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ 101 ((CYCLE) == I2C_DutyCycle_2)) 102 /** 103 * @} 104 */ 105 106 #define IS_I2C_SDA_SETUP_TIME(TIME) ((TIME) <= 0x000000FF) 107 #define IS_I2C_SDA_HOLD_TIME(TIME) ((TIME) <= 0x0000FFFF) 108 109 /** @defgroup I2C_acknowledged_address 110 * @{ 111 */ 112 #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x0001) 113 #define I2C_AcknowledgedAddress_10bit ((uint16_t)0x0002) 114 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ 115 ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) 116 /** 117 * @} 118 */ 119 120 /** @defgroup Target_Address_Bit 121 * @{ 122 */ 123 #define I2C_TargetAddressMode_7bit ((uint16_t)0x0001) 124 #define I2C_TargetAddressMode_10bit ((uint16_t)0x0002) 125 #define IS_I2C_TARGET_ADDRESS_MODE(ADDRESS) (((ADDRESS) == I2C_TargetAddressMode_7bit) || \ 126 ((ADDRESS) == I2C_TargetAddressMode_10bit)) 127 /** 128 * @} 129 */ 130 131 132 /** @defgroup SPI_RXFIFOFullThreshold 133 * @{ 134 */ 135 #define I2C_RXFIFOFullThreshold_1 ((uint32_t)0x0000) 136 #define I2C_RXFIFOFullThreshold_2 ((uint32_t)0x0001) 137 #define I2C_RXFIFOFullThreshold_3 ((uint32_t)0x0002) 138 #define I2C_RXFIFOFullThreshold_4 ((uint32_t)0x0003) 139 #define I2C_RXFIFOFullThreshold_5 ((uint32_t)0x0004) 140 #define I2C_RXFIFOFullThreshold_6 ((uint32_t)0x0005) 141 #define I2C_RXFIFOFullThreshold_7 ((uint32_t)0x0006) 142 #define I2C_RXFIFOFullThreshold_8 ((uint32_t)0x0007) 143 144 #define IS_I2C_RX_FIFO_FULL_THRESHOLD(THRESHOLD) (THRESHOLD <= I2C_RXFIFOFullThreshold_8) 145 /** 146 * @} 147 */ 148 149 /** @defgroup SPI_TXFIFOEmptyThreshold 150 * @{ 151 */ 152 #define I2C_TXFIFOEmptyThreshold_0 ((uint32_t)0x0000) 153 #define I2C_TXFIFOEmptyThreshold_1 ((uint32_t)0x0001) 154 #define I2C_TXFIFOEmptyThreshold_2 ((uint32_t)0x0002) 155 #define I2C_TXFIFOEmptyThreshold_3 ((uint32_t)0x0003) 156 #define I2C_TXFIFOEmptyThreshold_4 ((uint32_t)0x0004) 157 #define I2C_TXFIFOEmptyThreshold_5 ((uint32_t)0x0005) 158 #define I2C_TXFIFOEmptyThreshold_6 ((uint32_t)0x0006) 159 #define I2C_TXFIFOEmptyThreshold_7 ((uint32_t)0x0007) 160 #define I2C_TXFIFOEmptyThreshold_8 ((uint32_t)0x0008) 161 162 #define IS_I2C_TX_FIFO_EMPTY_THRESHOLD(THRESHOLD) (THRESHOLD <= I2C_TXFIFOEmptyThreshold_8) 163 /** 164 * @} 165 */ 166 167 168 /** @defgroup I2C_DMAReceiveLevel 169 * @{ 170 */ 171 #define I2C_DMAReceiveLevel_1 ((uint32_t)0x0000) 172 #define I2C_DMAReceiveLevel_2 ((uint32_t)0x0001) 173 #define I2C_DMAReceiveLevel_3 ((uint32_t)0x0002) 174 #define I2C_DMAReceiveLevel_4 ((uint32_t)0x0003) 175 #define I2C_DMAReceiveLevel_5 ((uint32_t)0x0004) 176 #define I2C_DMAReceiveLevel_6 ((uint32_t)0x0005) 177 #define I2C_DMAReceiveLevel_7 ((uint32_t)0x0006) 178 #define I2C_DMAReceiveLevel_8 ((uint32_t)0x0007) 179 180 #define IS_I2C_DMA_RECEIVE_LEVEL(LEVEL) (LEVEL <= I2C_DMAReceiveLevel_8) 181 /** 182 * @} 183 */ 184 185 /** @defgroup I2C_DMATransmitLevel 186 * @{ 187 */ 188 #define I2C_DMATransmitLevel_0 ((uint32_t)0x0000) 189 #define I2C_DMATransmitLevel_1 ((uint32_t)0x0001) 190 #define I2C_DMATransmitLevel_2 ((uint32_t)0x0002) 191 #define I2C_DMATransmitLevel_3 ((uint32_t)0x0003) 192 #define I2C_DMATransmitLevel_4 ((uint32_t)0x0004) 193 #define I2C_DMATransmitLevel_5 ((uint32_t)0x0005) 194 #define I2C_DMATransmitLevel_6 ((uint32_t)0x0006) 195 #define I2C_DMATransmitLevel_7 ((uint32_t)0x0007) 196 197 #define IS_I2C_DMA_TRANSMIT_LEVEL(LEVEL) (LEVEL <= I2C_DMATransmitLevel_7) 198 /** 199 * @} 200 */ 201 202 /** @defgroup I2C_DMA_transfer_requests 203 * @{ 204 */ 205 #define I2C_DMAReq_Rx ((uint32_t)0x0001) 206 #define I2C_DMAReq_Tx ((uint32_t)0x0002) 207 #define IS_I2C_DMAREQ(DMAREQ) (((DMAREQ) & I2C_DMAReq_Tx) || \ 208 ((DMAREQ) & I2C_DMAReq_Rx)) 209 /** 210 * @} 211 */ 212 213 #define I2C_IT_RXUDF ((uint32_t)0x0001) //clear by hardware 214 #define I2C_IT_RXOVF ((uint32_t)0x0002) //clear by read 215 #define I2C_IT_RXF ((uint32_t)0x0004) //clear by read 216 #define I2C_IT_TXOVF ((uint32_t)0x0008) //clear by read 217 #define I2C_IT_TXE ((uint32_t)0x0010) //clear by hardware 218 #define I2C_IT_RD_REQ ((uint32_t)0x0020) //clear by read 219 #define I2C_IT_TX_ABRT ((uint32_t)0x0040) //clear by read 220 #define I2C_IT_RX_DONE ((uint32_t)0x0080) //clear by read 221 #define I2C_IT_ACTIVITY ((uint32_t)0x0100) //clear by read 222 #define I2C_IT_STOP_DET ((uint32_t)0x0200) //clear by read 223 #define I2C_IT_START_DET ((uint32_t)0x0400) 224 #define I2C_IT_GEN_CALL ((uint32_t)0x0800) 225 #define I2C_IT_ALL ((uint32_t)0x0FFF) 226 227 #define IS_I2C_CONFIG_IT(IT) ((((IT) & (~(uint32_t)0x0FFF)) == 0x00) && ((IT) != 0x00)) 228 #define IS_I2C_CLEAR_IT(IT) ((((IT) & (~(uint32_t)0x0FFF)) == 0x00) && ((IT) != 0x00)) 229 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RXUDF) || \ 230 ((IT) == I2C_IT_RXOVF) || \ 231 ((IT) == I2C_IT_RXF) || \ 232 ((IT) == I2C_IT_TXOVF) || \ 233 ((IT) == I2C_IT_TXE) || \ 234 ((IT) == I2C_IT_RD_REQ) || \ 235 ((IT) == I2C_IT_TX_ABRT) || \ 236 ((IT) == I2C_IT_RX_DONE) || \ 237 ((IT) == I2C_IT_ACTIVITY) || \ 238 ((IT) == I2C_IT_STOP_DET) || \ 239 ((IT) == I2C_IT_START_DET) || \ 240 ((IT) == I2C_IT_GEN_CALL) || \ 241 ((IT) == I2C_IT_ALL)) 242 243 #define I2C_FLAG_ACTIVITY ((uint32_t)0x0001) 244 #define I2C_FLAG_TXNF ((uint32_t)0x0002) 245 #define I2C_FLAG_TXE ((uint32_t)0x0004) 246 #define I2C_FLAG_RXNE ((uint32_t)0x0008) 247 #define I2C_FLAG_RXF ((uint32_t)0x0010) 248 #define I2C_FLAG_MST_ACTIVITY ((uint32_t)0x0020) 249 #define I2C_FLAG_SLV_ACTIVITY ((uint32_t)0x0040) 250 #define I2C_FLAG_ALL ((uint32_t)0x007F) 251 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_ACTIVITY) || \ 252 ((FLAG) == I2C_FLAG_TXNF) || \ 253 ((FLAG) == I2C_FLAG_TXE) || \ 254 ((FLAG) == I2C_FLAG_RXNE) || \ 255 ((FLAG) == I2C_FLAG_RXF) || \ 256 ((FLAG) == I2C_FLAG_MST_ACTIVITY) || \ 257 ((FLAG) == I2C_FLAG_SLV_ACTIVITY) || \ 258 ((FLAG) == I2C_FLAG_ALL)) 259 260 #define I2C_TX_ABRT_7BIT_ADDR_NOACK ((uint32_t)0x00000001) 261 #define I2C_TX_ABRT_10BIT_ADDR1_NOACK ((uint32_t)0x00000002) 262 #define I2C_TX_ABRT_10BIT_ADDR2_NOACK ((uint32_t)0x00000004) 263 #define I2C_TX_ABRT_TXDATA_NOACK ((uint32_t)0x00000008) 264 #define I2C_TX_ABRT_GEN_CALL_NOACK ((uint32_t)0x00000010) 265 #define I2C_TX_ABRT_GEN_CALL_READ ((uint32_t)0x00000020) 266 #define I2C_TX_ABRT_HIGH_SPEED_ACKDET ((uint32_t)0x00000040) 267 #define I2C_TX_ABRT_START_BYTE_ACKDET ((uint32_t)0x00000080) 268 #define I2C_TX_ABRT_HIGH_SPEED_NORSTRT ((uint32_t)0x00000100) 269 #define I2C_TX_ABRT_START_BYTE_NORSTRT ((uint32_t)0x00000200) 270 #define I2C_TX_ABRT_10BIT_RD_NORSTRT ((uint32_t)0x00000400) 271 #define I2C_TX_ABRT_LOST_ARB ((uint32_t)0x00000800) 272 #define I2C_TX_ABRT_SLVFLUSH_TXFIFO ((uint32_t)0x00001000) 273 #define I2C_TX_ABRT_SLV_LOST_ARB ((uint32_t)0x00002000) 274 #define I2C_TX_ABRT_SLV_RD_INTX ((uint32_t)0x00004000) 275 #define I2C_TX_ABRT_MASTER_DISABLE ((uint32_t)0x00008000) 276 #define I2C_TX_ABRT_USER_ABRT ((uint32_t)0x00010000) 277 #define I2C_TX_ABRT_TX_FLUSH_CNT ((uint32_t)0x00020000) 278 #define IS_I2C_TX_ABRT(ABRT) (((ABRT) == I2C_TX_ABRT_7BIT_ADDR_NOACK) || \ 279 ((ABRT) == I2C_TX_ABRT_10BIT_ADDR1_NOACK) || \ 280 ((FLAG) == I2C_TX_ABRT_10BIT_ADDR2_NOACK) || \ 281 ((FLAG) == I2C_TX_ABRT_TXDATA_NOACK) || \ 282 ((FLAG) == I2C_TX_ABRT_GEN_CALL_NOACK) || \ 283 ((FLAG) == I2C_TX_ABRT_GEN_CALL_READ) || \ 284 ((FLAG) == I2C_TX_ABRT_HIGH_SPEED_ACKDET) || \ 285 ((FLAG) == I2C_TX_ABRT_START_BYTE_ACKDET) || \ 286 ((FLAG) == I2C_TX_ABRT_HIGH_SPEED_NORSTRT) || \ 287 ((FLAG) == I2C_TX_ABRT_START_BYTE_NORSTRT) || \ 288 ((FLAG) == I2C_TX_ABRT_10BIT_RD_NORSTRT) || \ 289 ((FLAG) == I2C_TX_ABRT_LOST_ARB) || \ 290 ((FLAG) == I2C_TX_ABRT_SLVFLUSH_TXFIFO) || \ 291 ((FLAG) == I2C_TX_ABRT_SLV_LOST_ARB) || \ 292 ((FLAG) == I2C_TX_ABRT_SLV_RD_INTX) || \ 293 ((FLAG) == I2C_TX_ABRT_MASTER_DISABLE) || \ 294 ((FLAG) == I2C_TX_ABRT_USER_ABRT) || \ 295 ((FLAG) == I2C_TX_ABRT_TX_FLUSH_CNT)) 296 297 typedef enum 298 { 299 I2C_DataCMD_Write = (uint32_t)0x01, 300 I2C_DataCMD_Read = (uint32_t)0x02 301 }I2CDataCMD_TypeDef; 302 #define IS_I2C_DATA_CMD(CMD) (((CMD) == I2C_DataCMD_Write) || \ 303 ((CMD) == I2C_DataCMD_Read)) 304 305 typedef enum 306 { 307 I2C_DataEndCondition_None = (uint32_t)0x01, 308 I2C_DataEndCondition_Stop = (uint32_t)0x02, 309 I2C_DataEndCondition_Restart = (uint32_t)0x03 310 }I2CDataEndCondition_TypeDef; 311 #define IS_I2C_DATA_END_CONDITION(CONDITION) (((CONDITION) == I2C_DataEndCondition_None) || \ 312 ((CONDITION) == I2C_DataEndCondition_Stop) || \ 313 ((CONDITION) == I2C_DataEndCondition_Restart)) 314 315 316 void I2C_DeInit(I2C_TypeDef* I2Cx); 317 void I2C_Init(I2C_TypeDef* I2Cx,I2C_InitTypeDef* I2C_InitStruct); 318 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); 319 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 320 void I2C_SetTargetAddress(I2C_TypeDef* I2Cx, uint32_t TargetAddress, uint32_t TargetAddressMode); 321 void I2C_DMAInit(I2C_TypeDef* I2Cx, I2C_DMAInitTypeDef* I2C_DMAInitStruct); 322 void I2C_DMAStructInit(I2C_DMAInitTypeDef* I2C_DMAInitStruct); 323 void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); 324 void I2C_SetSDASetupTime(I2C_TypeDef* I2Cx,uint32_t PCLKCycles); 325 void I2C_SetSDAHoldTime(I2C_TypeDef* I2Cx,uint32_t PCLKCycles); 326 327 void I2C_ITConfig(I2C_TypeDef* I2Cx,uint32_t I2C_IT, FunctionalState NewState); 328 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx,uint32_t I2C_IT); 329 ITStatus I2C_GetRawITStatus(I2C_TypeDef* I2Cx,uint32_t I2C_IT); 330 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx,uint32_t I2C_IT); 331 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx,uint32_t I2C_FLAG); 332 uint32_t I2C_GetFlagStatusReg(I2C_TypeDef* I2Cx); 333 FlagStatus I2C_GetTXAbortSource(I2C_TypeDef* I2Cx,uint32_t I2C_TX_ABRT); 334 uint32_t I2C_GetTXAbortSourceReg(I2C_TypeDef* I2Cx); 335 I2CMode_TypeDef I2C_GetI2CMode(I2C_TypeDef* I2Cx); 336 337 void I2C_MasterGenerateReceiveSCL(I2C_TypeDef* I2Cx, I2CDataEndCondition_TypeDef DataCondition); 338 uint16_t I2C_ExtendData(uint8_t Data, I2CDataCMD_TypeDef DataCMD, I2CDataEndCondition_TypeDef DataCondition); 339 void I2C_WriteDataToDR(I2C_TypeDef* I2Cx, uint16_t ExtendData); 340 uint8_t I2C_ReadDataFromDR(I2C_TypeDef* I2Cx); 341 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data, I2CDataEndCondition_TypeDef DataCondition); 342 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx, I2CDataEndCondition_TypeDef DataCondition); 343 void I2C_SendBytes(I2C_TypeDef* I2Cx, uint8_t* Data, uint32_t DataLen, I2CDataEndCondition_TypeDef DataCondition); 344 void I2C_ReceiveBytes(I2C_TypeDef* I2Cx, uint8_t* Data, uint32_t DataLen, I2CDataEndCondition_TypeDef DataCondition); 345 346 void I2C_SlaveGeneralNACKOnlyCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 347 348 FlagStatus I2C_IsEnable(I2C_TypeDef* I2Cx); 349 350 351 #ifdef __cplusplus 352 } 353 #endif 354 355 #endif 356 357 /************************** (C) COPYRIGHT Megahunt *****END OF FILE****/ 358