1 /* Define to prevent recursive inclusion -------------------------------------*/ 2 #ifndef __AIR32F10x_I2C_H 3 #define __AIR32F10x_I2C_H 4 5 #ifdef __cplusplus 6 extern "C" { 7 #endif 8 9 /* Includes ------------------------------------------------------------------*/ 10 #include "air32f10x.h" 11 12 /** @addtogroup air32f10x_StdPeriph_Driver 13 * @{ 14 */ 15 16 /** @addtogroup I2C 17 * @{ 18 */ 19 20 /** @defgroup I2C_Exported_Types 21 * @{ 22 */ 23 24 /** 25 * @brief I2C Init structure definition 26 */ 27 28 typedef struct 29 { 30 uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. 31 This parameter must be set to a value lower than 400kHz */ 32 33 uint16_t I2C_Mode; /*!< Specifies the I2C mode. 34 This parameter can be a value of @ref I2C_mode */ 35 36 uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. 37 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ 38 39 uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. 40 This parameter can be a 7-bit or 10-bit address. */ 41 42 uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. 43 This parameter can be a value of @ref I2C_acknowledgement */ 44 45 uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. 46 This parameter can be a value of @ref I2C_acknowledged_address */ 47 }I2C_InitTypeDef; 48 49 /** 50 * @} 51 */ 52 53 54 /** @defgroup I2C_Exported_Constants 55 * @{ 56 */ 57 58 #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ 59 ((PERIPH) == I2C2)) 60 /** @defgroup I2C_mode 61 * @{ 62 */ 63 64 #define I2C_Mode_I2C ((uint16_t)0x0000) 65 #define I2C_Mode_SMBusDevice ((uint16_t)0x0002) 66 #define I2C_Mode_SMBusHost ((uint16_t)0x000A) 67 #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ 68 ((MODE) == I2C_Mode_SMBusDevice) || \ 69 ((MODE) == I2C_Mode_SMBusHost)) 70 /** 71 * @} 72 */ 73 74 /** @defgroup I2C_duty_cycle_in_fast_mode 75 * @{ 76 */ 77 78 #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ 79 #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ 80 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ 81 ((CYCLE) == I2C_DutyCycle_2)) 82 /** 83 * @} 84 */ 85 86 /** @defgroup I2C_acknowledgement 87 * @{ 88 */ 89 90 #define I2C_Ack_Enable ((uint16_t)0x0400) 91 #define I2C_Ack_Disable ((uint16_t)0x0000) 92 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ 93 ((STATE) == I2C_Ack_Disable)) 94 /** 95 * @} 96 */ 97 98 /** @defgroup I2C_transfer_direction 99 * @{ 100 */ 101 102 #define I2C_Direction_Transmitter ((uint8_t)0x00) 103 #define I2C_Direction_Receiver ((uint8_t)0x01) 104 #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ 105 ((DIRECTION) == I2C_Direction_Receiver)) 106 /** 107 * @} 108 */ 109 110 /** @defgroup I2C_acknowledged_address 111 * @{ 112 */ 113 114 #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) 115 #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) 116 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ 117 ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) 118 /** 119 * @} 120 */ 121 122 /** @defgroup I2C_registers 123 * @{ 124 */ 125 126 #define I2C_Register_CR1 ((uint8_t)0x00) 127 #define I2C_Register_CR2 ((uint8_t)0x04) 128 #define I2C_Register_OAR1 ((uint8_t)0x08) 129 #define I2C_Register_OAR2 ((uint8_t)0x0C) 130 #define I2C_Register_DR ((uint8_t)0x10) 131 #define I2C_Register_SR1 ((uint8_t)0x14) 132 #define I2C_Register_SR2 ((uint8_t)0x18) 133 #define I2C_Register_CCR ((uint8_t)0x1C) 134 #define I2C_Register_TRISE ((uint8_t)0x20) 135 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ 136 ((REGISTER) == I2C_Register_CR2) || \ 137 ((REGISTER) == I2C_Register_OAR1) || \ 138 ((REGISTER) == I2C_Register_OAR2) || \ 139 ((REGISTER) == I2C_Register_DR) || \ 140 ((REGISTER) == I2C_Register_SR1) || \ 141 ((REGISTER) == I2C_Register_SR2) || \ 142 ((REGISTER) == I2C_Register_CCR) || \ 143 ((REGISTER) == I2C_Register_TRISE)) 144 /** 145 * @} 146 */ 147 148 /** @defgroup I2C_SMBus_alert_pin_level 149 * @{ 150 */ 151 152 #define I2C_SMBusAlert_Low ((uint16_t)0x2000) 153 #define I2C_SMBusAlert_High ((uint16_t)0xDFFF) 154 #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ 155 ((ALERT) == I2C_SMBusAlert_High)) 156 /** 157 * @} 158 */ 159 160 /** @defgroup I2C_PEC_position 161 * @{ 162 */ 163 164 #define I2C_PECPosition_Next ((uint16_t)0x0800) 165 #define I2C_PECPosition_Current ((uint16_t)0xF7FF) 166 #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ 167 ((POSITION) == I2C_PECPosition_Current)) 168 /** 169 * @} 170 */ 171 172 /** @defgroup I2C_NCAK_position 173 * @{ 174 */ 175 176 #define I2C_NACKPosition_Next ((uint16_t)0x0800) 177 #define I2C_NACKPosition_Current ((uint16_t)0xF7FF) 178 #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ 179 ((POSITION) == I2C_NACKPosition_Current)) 180 /** 181 * @} 182 */ 183 184 /** @defgroup I2C_interrupts_definition 185 * @{ 186 */ 187 188 #define I2C_IT_BUF ((uint16_t)0x0400) 189 #define I2C_IT_EVT ((uint16_t)0x0200) 190 #define I2C_IT_ERR ((uint16_t)0x0100) 191 #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) 192 /** 193 * @} 194 */ 195 196 /** @defgroup I2C_interrupts_definition 197 * @{ 198 */ 199 200 #define I2C_IT_SMBALERT ((uint32_t)0x01008000) 201 #define I2C_IT_TIMEOUT ((uint32_t)0x01004000) 202 #define I2C_IT_PECERR ((uint32_t)0x01001000) 203 #define I2C_IT_OVR ((uint32_t)0x01000800) 204 #define I2C_IT_AF ((uint32_t)0x01000400) 205 #define I2C_IT_ARLO ((uint32_t)0x01000200) 206 #define I2C_IT_BERR ((uint32_t)0x01000100) 207 #define I2C_IT_TXE ((uint32_t)0x06000080) 208 #define I2C_IT_RXNE ((uint32_t)0x06000040) 209 #define I2C_IT_STOPF ((uint32_t)0x02000010) 210 #define I2C_IT_ADD10 ((uint32_t)0x02000008) 211 #define I2C_IT_BTF ((uint32_t)0x02000004) 212 #define I2C_IT_ADDR ((uint32_t)0x02000002) 213 #define I2C_IT_SB ((uint32_t)0x02000001) 214 215 #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) 216 217 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ 218 ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ 219 ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ 220 ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ 221 ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ 222 ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ 223 ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) 224 /** 225 * @} 226 */ 227 228 /** @defgroup I2C_flags_definition 229 * @{ 230 */ 231 232 /** 233 * @brief SR2 register flags 234 */ 235 236 #define I2C_FLAG_DUALF ((uint32_t)0x00800000) 237 #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) 238 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) 239 #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) 240 #define I2C_FLAG_TRA ((uint32_t)0x00040000) 241 #define I2C_FLAG_BUSY ((uint32_t)0x00020000) 242 #define I2C_FLAG_MSL ((uint32_t)0x00010000) 243 244 /** 245 * @brief SR1 register flags 246 */ 247 248 #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) 249 #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) 250 #define I2C_FLAG_PECERR ((uint32_t)0x10001000) 251 #define I2C_FLAG_OVR ((uint32_t)0x10000800) 252 #define I2C_FLAG_AF ((uint32_t)0x10000400) 253 #define I2C_FLAG_ARLO ((uint32_t)0x10000200) 254 #define I2C_FLAG_BERR ((uint32_t)0x10000100) 255 #define I2C_FLAG_TXE ((uint32_t)0x10000080) 256 #define I2C_FLAG_RXNE ((uint32_t)0x10000040) 257 #define I2C_FLAG_STOPF ((uint32_t)0x10000010) 258 #define I2C_FLAG_ADD10 ((uint32_t)0x10000008) 259 #define I2C_FLAG_BTF ((uint32_t)0x10000004) 260 #define I2C_FLAG_ADDR ((uint32_t)0x10000002) 261 #define I2C_FLAG_SB ((uint32_t)0x10000001) 262 263 #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) 264 265 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ 266 ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ 267 ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ 268 ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ 269 ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ 270 ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ 271 ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ 272 ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ 273 ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ 274 ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ 275 ((FLAG) == I2C_FLAG_SB)) 276 /** 277 * @} 278 */ 279 280 /** @defgroup I2C_Events 281 * @{ 282 */ 283 284 /*======================================== 285 286 I2C Master Events (Events grouped in order of communication) 287 ==========================================*/ 288 /** 289 * @brief Communication start 290 * 291 * After sending the START condition (I2C_GenerateSTART() function) the master 292 * has to wait for this event. It means that the Start condition has been correctly 293 * released on the I2C bus (the bus is free, no other devices is communicating). 294 * 295 */ 296 /* --EV5 */ 297 #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ 298 299 /** 300 * @brief Address Acknowledge 301 * 302 * After checking on EV5 (start condition correctly released on the bus), the 303 * master sends the address of the slave(s) with which it will communicate 304 * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 305 * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 306 * his address. If an acknowledge is sent on the bus, one of the following events will 307 * be set: 308 * 309 * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 310 * event is set. 311 * 312 * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 313 * is set 314 * 315 * 3) In case of 10-Bit addressing mode, the master (just after generating the START 316 * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 317 * function). Then master should wait on EV9. It means that the 10-bit addressing 318 * header has been correctly sent on the bus. Then master should send the second part of 319 * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 320 * should wait for event EV6. 321 * 322 */ 323 324 /* --EV6 */ 325 #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ 326 #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ 327 /* --EV9 */ 328 #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ 329 330 /** 331 * @brief Communication events 332 * 333 * If a communication is established (START condition generated and slave address 334 * acknowledged) then the master has to check on one of the following events for 335 * communication procedures: 336 * 337 * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 338 * the data received from the slave (I2C_ReceiveData() function). 339 * 340 * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 341 * function) then to wait on event EV8 or EV8_2. 342 * These two events are similar: 343 * - EV8 means that the data has been written in the data register and is 344 * being shifted out. 345 * - EV8_2 means that the data has been physically shifted out and output 346 * on the bus. 347 * In most cases, using EV8 is sufficient for the application. 348 * Using EV8_2 leads to a slower communication but ensure more reliable test. 349 * EV8_2 is also more suitable than EV8 for testing on the last data transmission 350 * (before Stop condition generation). 351 * 352 * @note In case the user software does not guarantee that this event EV7 is 353 * managed before the current byte end of transfer, then user may check on EV7 354 * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). 355 * In this case the communication may be slower. 356 * 357 */ 358 359 /* Master RECEIVER mode -----------------------------*/ 360 /* --EV7 */ 361 #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ 362 363 /* Master TRANSMITTER mode --------------------------*/ 364 /* --EV8 */ 365 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ 366 /* --EV8_2 */ 367 #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ 368 369 370 /*======================================== 371 372 I2C Slave Events (Events grouped in order of communication) 373 ==========================================*/ 374 375 /** 376 * @brief Communication start events 377 * 378 * Wait on one of these events at the start of the communication. It means that 379 * the I2C peripheral detected a Start condition on the bus (generated by master 380 * device) followed by the peripheral address. The peripheral generates an ACK 381 * condition on the bus (if the acknowledge feature is enabled through function 382 * I2C_AcknowledgeConfig()) and the events listed above are set : 383 * 384 * 1) In normal case (only one address managed by the slave), when the address 385 * sent by the master matches the own address of the peripheral (configured by 386 * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 387 * (where XXX could be TRANSMITTER or RECEIVER). 388 * 389 * 2) In case the address sent by the master matches the second address of the 390 * peripheral (configured by the function I2C_OwnAddress2Config() and enabled 391 * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 392 * (where XXX could be TRANSMITTER or RECEIVER) are set. 393 * 394 * 3) In case the address sent by the master is General Call (address 0x00) and 395 * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 396 * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. 397 * 398 */ 399 400 /* --EV1 (all the events below are variants of EV1) */ 401 /* 1) Case of One Single Address managed by the slave */ 402 #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ 403 #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ 404 405 /* 2) Case of Dual address managed by the slave */ 406 #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ 407 #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ 408 409 /* 3) Case of General Call enabled for the slave */ 410 #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ 411 412 /** 413 * @brief Communication events 414 * 415 * Wait on one of these events when EV1 has already been checked and: 416 * 417 * - Slave RECEIVER mode: 418 * - EV2: When the application is expecting a data byte to be received. 419 * - EV4: When the application is expecting the end of the communication: master 420 * sends a stop condition and data transmission is stopped. 421 * 422 * - Slave Transmitter mode: 423 * - EV3: When a byte has been transmitted by the slave and the application is expecting 424 * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and 425 * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 426 * used when the user software doesn't guarantee the EV3 is managed before the 427 * current byte end of transfer. 428 * - EV3_2: When the master sends a NACK in order to tell slave that data transmission 429 * shall end (before sending the STOP condition). In this case slave has to stop sending 430 * data bytes and expect a Stop condition on the bus. 431 * 432 * @note In case the user software does not guarantee that the event EV2 is 433 * managed before the current byte end of transfer, then user may check on EV2 434 * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). 435 * In this case the communication may be slower. 436 * 437 */ 438 439 /* Slave RECEIVER mode --------------------------*/ 440 /* --EV2 */ 441 #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ 442 /* --EV4 */ 443 #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ 444 445 /* Slave TRANSMITTER mode -----------------------*/ 446 /* --EV3 */ 447 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ 448 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ 449 /* --EV3_2 */ 450 #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ 451 452 /*=========================== End of Events Description ==========================================*/ 453 454 #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ 455 ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ 456 ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ 457 ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ 458 ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ 459 ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ 460 ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ 461 ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ 462 ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ 463 ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ 464 ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ 465 ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ 466 ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ 467 ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ 468 ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ 469 ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ 470 ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ 471 ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ 472 ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ 473 ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) 474 /** 475 * @} 476 */ 477 478 /** @defgroup I2C_own_address1 479 * @{ 480 */ 481 482 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) 483 /** 484 * @} 485 */ 486 487 /** @defgroup I2C_clock_speed 488 * @{ 489 */ 490 491 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) 492 /** 493 * @} 494 */ 495 496 /** 497 * @} 498 */ 499 500 /** @defgroup I2C_Exported_Macros 501 * @{ 502 */ 503 504 /** 505 * @} 506 */ 507 508 /** @defgroup I2C_Exported_Functions 509 * @{ 510 */ 511 512 void I2C_DeInit(I2C_TypeDef* I2Cx); 513 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); 514 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); 515 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 516 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 517 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 518 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); 519 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); 520 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); 521 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); 522 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 523 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 524 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); 525 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); 526 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); 527 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); 528 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); 529 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 530 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); 531 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); 532 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); 533 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); 534 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); 535 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); 536 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 537 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 538 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); 539 540 /** 541 * @brief 542 **************************************************************************************** 543 * 544 * I2C State Monitoring Functions 545 * 546 **************************************************************************************** 547 * This I2C driver provides three different ways for I2C state monitoring 548 * depending on the application requirements and constraints: 549 * 550 * 551 * 1) Basic state monitoring: 552 * Using I2C_CheckEvent() function: 553 * It compares the status registers (SR1 and SR2) content to a given event 554 * (can be the combination of one or more flags). 555 * It returns SUCCESS if the current status includes the given flags 556 * and returns ERROR if one or more flags are missing in the current status. 557 * - When to use: 558 * - This function is suitable for most applications as well as for startup 559 * activity since the events are fully described in the product reference manual 560 * (RM0008). 561 * - It is also suitable for users who need to define their own events. 562 * - Limitations: 563 * - If an error occurs (ie. error flags are set besides to the monitored flags), 564 * the I2C_CheckEvent() function may return SUCCESS despite the communication 565 * hold or corrupted real state. 566 * In this case, it is advised to use error interrupts to monitor the error 567 * events and handle them in the interrupt IRQ handler. 568 * 569 * @note 570 * For error management, it is advised to use the following functions: 571 * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). 572 * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. 573 * Where x is the peripheral instance (I2C1, I2C2 ...) 574 * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() 575 * in order to determine which error occurred. 576 * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 577 * and/or I2C_GenerateStop() in order to clear the error flag and source, 578 * and return to correct communication status. 579 * 580 * 581 * 2) Advanced state monitoring: 582 * Using the function I2C_GetLastEvent() which returns the image of both status 583 * registers in a single word (uint32_t) (Status Register 2 value is shifted left 584 * by 16 bits and concatenated to Status Register 1). 585 * - When to use: 586 * - This function is suitable for the same applications above but it allows to 587 * overcome the limitations of I2C_GetFlagStatus() function (see below). 588 * The returned value could be compared to events already defined in the 589 * library (air32f10x_i2c.h) or to custom values defined by user. 590 * - This function is suitable when multiple flags are monitored at the same time. 591 * - At the opposite of I2C_CheckEvent() function, this function allows user to 592 * choose when an event is accepted (when all events flags are set and no 593 * other flags are set or just when the needed flags are set like 594 * I2C_CheckEvent() function). 595 * - Limitations: 596 * - User may need to define his own events. 597 * - Same remark concerning the error management is applicable for this 598 * function if user decides to check only regular communication flags (and 599 * ignores error flags). 600 * 601 * 602 * 3) Flag-based state monitoring: 603 * Using the function I2C_GetFlagStatus() which simply returns the status of 604 * one single flag (ie. I2C_FLAG_RXNE ...). 605 * - When to use: 606 * - This function could be used for specific applications or in debug phase. 607 * - It is suitable when only one flag checking is needed (most I2C events 608 * are monitored through multiple flags). 609 * - Limitations: 610 * - When calling this function, the Status register is accessed. Some flags are 611 * cleared when the status register is accessed. So checking the status 612 * of one Flag, may clear other ones. 613 * - Function may need to be called twice or more in order to monitor one 614 * single event. 615 * 616 */ 617 618 /** 619 * 620 * 1) Basic state monitoring 621 ******************************************************************************* 622 */ 623 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); 624 /** 625 * 626 * 2) Advanced state monitoring 627 ******************************************************************************* 628 */ 629 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); 630 /** 631 * 632 * 3) Flag-based state monitoring 633 ******************************************************************************* 634 */ 635 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); 636 /** 637 * 638 ******************************************************************************* 639 */ 640 641 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); 642 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); 643 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); 644 645 #ifdef __cplusplus 646 } 647 #endif 648 649 #endif /*__AIR32F10x_I2C_H */ 650 /** 651 * @} 652 */ 653 654 /** 655 * @} 656 */ 657 658 /** 659 * @} 660 */ 661 662