1 /* Define to prevent recursive inclusion -------------------------------------*/ 2 #ifndef __AIR32F10x_RCC_H 3 #define __AIR32F10x_RCC_H 4 5 #ifdef __cplusplus 6 extern "C" { 7 #endif 8 9 /* Includes ------------------------------------------------------------------*/ 10 #include "air32f10x.h" 11 12 /** @addtogroup air32f10x_StdPeriph_Driver 13 * @{ 14 */ 15 16 /** @addtogroup RCC 17 * @{ 18 */ 19 20 /** @defgroup RCC_Exported_Types 21 * @{ 22 */ 23 24 typedef struct 25 { 26 uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ 27 uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ 28 uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ 29 uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ 30 uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ 31 }RCC_ClocksTypeDef; 32 33 /** 34 * @} 35 */ 36 37 /** @defgroup RCC_Exported_Constants 38 * @{ 39 */ 40 41 /** @defgroup HSE_configuration 42 * @{ 43 */ 44 45 #define RCC_HSE_OFF ((uint32_t)0x00000000) 46 #define RCC_HSE_ON ((uint32_t)0x00010000) 47 #define RCC_HSE_Bypass ((uint32_t)0x00040000) 48 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 49 ((HSE) == RCC_HSE_Bypass)) 50 51 /** 52 * @} 53 */ 54 55 /** @defgroup PLL_entry_clock_source 56 * @{ 57 */ 58 59 #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) 60 61 62 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) 63 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) 64 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 65 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ 66 ((SOURCE) == RCC_PLLSource_HSE_Div2)) 67 /** 68 * @} 69 */ 70 71 /** @defgroup PLL_multiplication_factor 72 * @{ 73 */ 74 #define RCC_PLLMul_2 ((uint32_t)0x00000000) 75 #define RCC_PLLMul_3 ((uint32_t)0x00040000) 76 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 77 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 78 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 79 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 80 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 81 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 82 #define RCC_PLLMul_10 ((uint32_t)0x00200000) 83 #define RCC_PLLMul_11 ((uint32_t)0x00240000) 84 #define RCC_PLLMul_12 ((uint32_t)0x00280000) 85 #define RCC_PLLMul_13 ((uint32_t)0x002C0000) 86 #define RCC_PLLMul_14 ((uint32_t)0x00300000) 87 #define RCC_PLLMul_15 ((uint32_t)0x00340000) 88 #define RCC_PLLMul_16 ((uint32_t)0x00380000) 89 #define RCC_PLLMul_17 ((uint32_t)0x10000000) 90 #define RCC_PLLMul_18 ((uint32_t)0x10040000) 91 #define RCC_PLLMul_19 ((uint32_t)0x10080000) 92 #define RCC_PLLMul_20 ((uint32_t)0x100C0000) 93 #define RCC_PLLMul_21 ((uint32_t)0x10100000) 94 #define RCC_PLLMul_22 ((uint32_t)0x10140000) 95 #define RCC_PLLMul_23 ((uint32_t)0x10180000) 96 #define RCC_PLLMul_24 ((uint32_t)0x101C0000) 97 #define RCC_PLLMul_25 ((uint32_t)0x10200000) 98 #define RCC_PLLMul_26 ((uint32_t)0x10240000) 99 #define RCC_PLLMul_27 ((uint32_t)0x10280000) 100 #define RCC_PLLMul_28 ((uint32_t)0x102C0000) 101 #define RCC_PLLMul_29 ((uint32_t)0x10300000) 102 #define RCC_PLLMul_30 ((uint32_t)0x10340000) 103 #define RCC_PLLMul_31 ((uint32_t)0x10380000) 104 #define RCC_PLLMul_32 ((uint32_t)0x103C0000) 105 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 106 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 107 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 108 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 109 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 110 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 111 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 112 ((MUL) == RCC_PLLMul_16) || \ 113 ((MUL) == RCC_PLLMul_17) || ((MUL) == RCC_PLLMul_18) || \ 114 ((MUL) == RCC_PLLMul_19) || ((MUL) == RCC_PLLMul_20) || \ 115 ((MUL) == RCC_PLLMul_21) || ((MUL) == RCC_PLLMul_22) || \ 116 ((MUL) == RCC_PLLMul_23) || ((MUL) == RCC_PLLMul_24) || \ 117 ((MUL) == RCC_PLLMul_25) || ((MUL) == RCC_PLLMul_26) || \ 118 ((MUL) == RCC_PLLMul_27) || ((MUL) == RCC_PLLMul_28) || \ 119 ((MUL) == RCC_PLLMul_29) || ((MUL) == RCC_PLLMul_30) || \ 120 ((MUL) == RCC_PLLMul_31) || ((MUL) == RCC_PLLMul_32)\ 121 ) 122 123 124 125 /** @defgroup System_clock_source 126 * @{ 127 */ 128 129 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 130 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 131 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 132 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 133 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 134 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 135 /** 136 * @} 137 */ 138 139 /** @defgroup AHB_clock_source 140 * @{ 141 */ 142 143 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 144 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 145 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 146 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 147 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 148 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 149 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 150 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 151 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 152 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 153 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 154 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 155 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 156 ((HCLK) == RCC_SYSCLK_Div512)) 157 /** 158 * @} 159 */ 160 161 /** @defgroup APB1_APB2_clock_source 162 * @{ 163 */ 164 165 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 166 #define RCC_HCLK_Div2 ((uint32_t)0x00000400) 167 #define RCC_HCLK_Div4 ((uint32_t)0x00000500) 168 #define RCC_HCLK_Div8 ((uint32_t)0x00000600) 169 #define RCC_HCLK_Div16 ((uint32_t)0x00000700) 170 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 171 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 172 ((PCLK) == RCC_HCLK_Div16)) 173 /** 174 * @} 175 */ 176 177 /** @defgroup RCC_Interrupt_source 178 * @{ 179 */ 180 181 #define RCC_IT_LSIRDY ((uint8_t)0x01) 182 #define RCC_IT_LSERDY ((uint8_t)0x02) 183 #define RCC_IT_HSIRDY ((uint8_t)0x04) 184 #define RCC_IT_HSERDY ((uint8_t)0x08) 185 #define RCC_IT_PLLRDY ((uint8_t)0x10) 186 #define RCC_IT_CSS ((uint8_t)0x80) 187 188 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) 189 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 190 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 191 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) 192 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) 193 194 195 196 /** 197 * @} 198 */ 199 200 /** @defgroup USB_Device_clock_source 201 * @{ 202 */ 203 #define RCC_USBCLKSource_PLLCLK_Div4 ((uint32_t)0x80C00000) 204 #define RCC_USBCLKSource_PLLCLK_4Div5 ((uint32_t)0x80800000) 205 #define RCC_USBCLKSource_PLLCLK_Div3 ((uint32_t)0x80400000) 206 #define RCC_USBCLKSource_PLLCLK_3Div5 ((uint32_t)0x80000000) 207 #define RCC_USBCLKSource_PLLCLK_Div2 ((uint32_t)0x00C00000) 208 #define RCC_USBCLKSource_PLLCLK_2Div5 ((uint32_t)0x00800000) 209 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint32_t)0x00400000) 210 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint32_t)0x00000000) 211 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1) || \ 212 ((SOURCE) == RCC_USBCLKSource_PLLCLK_2Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2) || \ 213 ((SOURCE) == RCC_USBCLKSource_PLLCLK_3Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div3) || \ 214 ((SOURCE) == RCC_USBCLKSource_PLLCLK_4Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div4)) 215 216 /** @defgroup ADC_clock_source 217 * @{ 218 */ 219 220 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) 221 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) 222 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) 223 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) 224 #define RCC_PCLK2_Div16 ((uint32_t)0x20000000) 225 #define RCC_PCLK2_Div32 ((uint32_t)0x20004000) 226 #define RCC_PCLK2_Div36 ((uint32_t)0x20008000) 227 #define RCC_PCLK2_Div48 ((uint32_t)0x2000C000) 228 #define RCC_PCLK2_Div64 ((uint32_t)0x40000000) 229 #define RCC_PCLK2_Div72 ((uint32_t)0x40004000) 230 #define RCC_PCLK2_Div96 ((uint32_t)0x40008000) 231 #define RCC_PCLK2_Div120 ((uint32_t)0x4000C000) 232 #define RCC_PCLK2_Div144 ((uint32_t)0x60000000) 233 #define RCC_PCLK2_Div168 ((uint32_t)0x60004000) 234 #define RCC_PCLK2_Div192 ((uint32_t)0x60008000) 235 #define RCC_PCLK2_Div216 ((uint32_t)0x6000C000) 236 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ 237 ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8) || \ 238 ((ADCCLK) == RCC_PCLK2_Div16) || ((ADCCLK) == RCC_PCLK2_Div32) || \ 239 ((ADCCLK) == RCC_PCLK2_Div36) || ((ADCCLK) == RCC_PCLK2_Div48) || \ 240 ((ADCCLK) == RCC_PCLK2_Div64) || ((ADCCLK) == RCC_PCLK2_Div72) || \ 241 ((ADCCLK) == RCC_PCLK2_Div96) || ((ADCCLK) == RCC_PCLK2_Div120) || \ 242 ((ADCCLK) == RCC_PCLK2_Div144) || ((ADCCLK) == RCC_PCLK2_Div168) || \ 243 ((ADCCLK) == RCC_PCLK2_Div192) || ((ADCCLK) == RCC_PCLK2_Div216)) 244 /** 245 * @} 246 */ 247 248 /** @defgroup LSE_configuration 249 * @{ 250 */ 251 252 #define RCC_LSE_OFF ((uint8_t)0x00) 253 #define RCC_LSE_ON ((uint8_t)0x01) 254 #define RCC_LSE_Bypass ((uint8_t)0x04) 255 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 256 ((LSE) == RCC_LSE_Bypass)) 257 /** 258 * @} 259 */ 260 261 /** @defgroup RTC_clock_source 262 * @{ 263 */ 264 265 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 266 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 267 #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) 268 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 269 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 270 ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) 271 /** 272 * @} 273 */ 274 275 /** @defgroup AHB_peripheral 276 * @{ 277 */ 278 279 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) 280 #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) 281 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) 282 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) 283 #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) 284 285 #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) 286 #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) 287 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) 288 289 /** 290 * @} 291 */ 292 293 /** @defgroup APB2_peripheral 294 * @{ 295 */ 296 297 #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) 298 #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) 299 #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) 300 #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) 301 #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) 302 #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) 303 #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) 304 #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) 305 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) 306 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) 307 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) 308 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 309 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) 310 #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) 311 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) 312 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) 313 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) 314 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) 315 316 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) 317 /** 318 * @} 319 */ 320 321 /** @defgroup APB1_peripheral 322 * @{ 323 */ 324 325 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 326 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 327 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 328 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 329 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 330 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 331 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) 332 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) 333 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) 334 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 335 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 336 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 337 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 338 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 339 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 340 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 341 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 342 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 343 #define RCC_APB1Periph_USB ((uint32_t)0x00800000) 344 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 345 #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) 346 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 347 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 348 #define RCC_APB1Periph_CEC ((uint32_t)0x40000000) 349 350 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) 351 352 /** 353 * @} 354 */ 355 356 /** @defgroup Clock_source_to_output_on_MCO_pin 357 * @{ 358 */ 359 enum 360 { 361 RCC_MCO_NoClock = 0x00, 362 RCC_MCO_SYSCLK = 0x04, 363 RCC_MCO_HSI, 364 RCC_MCO_HSE, 365 RCC_MCO_PLLCLK_Div2, 366 RCC_MCO_PLLCLK_Div3, 367 RCC_MCO_PLLCLK_Div4, 368 RCC_MCO_PLLCLK_Div5, 369 RCC_MCO_PLLCLK_Div6, 370 RCC_MCO_PLLCLK_Div7, 371 RCC_MCO_PLLCLK_Div8, 372 RCC_MCO_PLLCLK_Div9, 373 RCC_MCO_PLLCLK_Div10, 374 RCC_MCO_PLLCLK_Div11, 375 RCC_MCO_PLLCLK_Div12, 376 RCC_MCO_PLLCLK_Div13, 377 RCC_MCO_PLLCLK_Div14, 378 RCC_MCO_PLLCLK_Div15, 379 RCC_MCO_PLLCLK_Div16, 380 }; 381 382 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 383 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 384 ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLLCLK_Div3) || \ 385 ((MCO) == RCC_MCO_PLLCLK_Div4) || ((MCO) == RCC_MCO_PLLCLK_Div5) || \ 386 ((MCO) == RCC_MCO_PLLCLK_Div6) || ((MCO) == RCC_MCO_PLLCLK_Div7) || \ 387 ((MCO) == RCC_MCO_PLLCLK_Div8) || ((MCO) == RCC_MCO_PLLCLK_Div9) || \ 388 ((MCO) == RCC_MCO_PLLCLK_Div10) || ((MCO) == RCC_MCO_PLLCLK_Div11)|| \ 389 ((MCO) == RCC_MCO_PLLCLK_Div12) || ((MCO) == RCC_MCO_PLLCLK_Div13 || \ 390 ((MCO) == RCC_MCO_PLLCLK_Div14) || ((MCO) == RCC_MCO_PLLCLK_Div15) || \ 391 ((MCO) == RCC_MCO_PLLCLK_Div16) )) 392 393 /** 394 * @} 395 */ 396 397 /** @defgroup RCC_Flag 398 * @{ 399 */ 400 401 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 402 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 403 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 404 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 405 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 406 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 407 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 408 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 409 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 410 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 411 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 412 413 414 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 415 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 416 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 417 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 418 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 419 ((FLAG) == RCC_FLAG_LPWRRST)) 420 421 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 422 /** 423 * @} 424 */ 425 426 /** 427 * @} 428 */ 429 430 /** @defgroup RCC_Exported_Macros 431 * @{ 432 */ 433 434 /** 435 * @} 436 */ 437 438 /** @defgroup RCC_Exported_Functions 439 * @{ 440 */ 441 442 void RCC_DeInit(void); 443 void RCC_HSEConfig(uint32_t RCC_HSE); 444 ErrorStatus RCC_WaitForHSEStartUp(void); 445 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 446 void RCC_HSICmd(FunctionalState NewState); 447 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 448 void RCC_PLLCmd(FunctionalState NewState); 449 450 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 451 uint8_t RCC_GetSYSCLKSource(void); 452 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 453 void RCC_PCLK1Config(uint32_t RCC_HCLK); 454 void RCC_PCLK2Config(uint32_t RCC_HCLK); 455 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 456 457 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); 458 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); 459 460 void RCC_LSEConfig(uint8_t RCC_LSE); 461 void RCC_LSICmd(FunctionalState NewState); 462 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 463 void RCC_RTCCLKCmd(FunctionalState NewState); 464 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 465 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 466 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 467 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 468 469 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 470 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 471 void RCC_BackupResetCmd(FunctionalState NewState); 472 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 473 void RCC_MCOConfig(uint8_t RCC_MCO); 474 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 475 void RCC_ClearFlag(void); 476 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 477 void RCC_ClearITPendingBit(uint8_t RCC_IT); 478 479 void RCC_PLLConfigUser(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 480 481 #ifdef __cplusplus 482 } 483 #endif 484 485 #endif /* __AIR32F10x_RCC_H */ 486 /** 487 * @} 488 */ 489 490 /** 491 * @} 492 */ 493 494 /** 495 * @} 496 */ 497 498