1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 */ 9 #ifndef __AM33XX_H__ 10 #define __AM33XX_H__ 11 12 #define REG32(x) (*((volatile unsigned int *)(x))) 13 #define REG16(x) (*((volatile unsigned short *)(x))) 14 15 /** Cache Line size in ARM Cortex-A8. */ 16 #define AM33XX_CACHELINE_SIZE (64) 17 18 /** @brief Base address of AINTC memory mapped registers */ 19 #define AM33XX_AINTC_REGS (0x48200000) 20 21 22 /** @brief Base addresses of control module registers */ 23 #define AM33XX_CTLM_REGS (0x44e10000) 24 25 /** @brief Base addresses of USB memory mapped registers */ 26 #define AM33XX_USB_0_BASE (0x47401400) 27 #define AM33XX_USB_1_BASE (0x47401C00) 28 /** @brief Base addresses of SPI memory mapped registers */ 29 #define AM33XX_SPI_0_REGS (0x48030000) 30 #define AM33XX_SPI_1_REGS (0x481A0000) 31 32 /** @brief Base addresses of GPIO memory mapped registers */ 33 #define AM33XX_GPIO_0_REGS (0x44E07000) 34 #define AM33XX_GPIO_1_REGS (0x4804C000) 35 #define AM33XX_GPIO_2_REGS (0x481AC000) 36 #define AM33XX_GPIO_3_REGS (0x481AE000) 37 38 /** @brief Base addresses of DMTIMER memory mapped registers */ 39 #define AM33XX_DMTIMER_0_REGS (0x44E05000) 40 #define AM33XX_DMTIMER_1_REGS (0x44E31000) 41 #define AM33XX_DMTIMER_2_REGS (0x48040000) 42 #define AM33XX_DMTIMER_3_REGS (0x48042000) 43 #define AM33XX_DMTIMER_4_REGS (0x48044000) 44 #define AM33XX_DMTIMER_5_REGS (0x48046000) 45 #define AM33XX_DMTIMER_6_REGS (0x48048000) 46 #define AM33XX_DMTIMER_7_REGS (0x4804A000) 47 48 /** @brief Base address of MMC memory mapped registers */ 49 #define AM33XX_MMCHS_0_REGS (0x48060000) 50 #define AM33XX_MMCHS_1_REGS (0x481D8000) 51 #define AM33XX_MMCHS_2_REGS (0x47810000) 52 53 /** @brief Base address of GPMC memory mapped registers */ 54 #define AM33XX_GPMC_0_REGS (0x50000000) 55 56 /** @brief Base address of GPMC memory mapped registers */ 57 #define AM33XX_ELM_0_REGS (0x48080000) 58 59 /** @brief Base address of I2C memory mapped registers */ 60 #define AM33XX_I2C_0_REGS (0x44E0B000) 61 #define AM33XX_I2C_1_REGS (0x4802A000) 62 #define AM33XX_I2C_2_REGS (0x4819C000) 63 64 /** @brief Base address of WDT memory mapped registers */ 65 #define AM33XX_WDT_0_REGS (0x44E33000) 66 #define AM33XX_WDT_1_REGS (0x44E35000) 67 68 /** @brief Base address of WDT memory mapped registers */ 69 #define AM33XX_CPSW_SS_REGS (0x4A100000) 70 #define AM33XX_CPSW_MDIO_REGS (0x4A101000) 71 #define AM33XX_CPSW_WR_REGS (0x4A101200) 72 #define AM33XX_CPSW_CPDMA_REGS (0x4A100800) 73 #define AM33XX_CPSW_ALE_REGS (0x4A100D00) 74 #define AM33XX_CPSW_STAT_REGS (0x4A100900) 75 #define AM33XX_CPSW_PORT_0_REGS (0x4A100100) 76 #define AM33XX_CPSW_PORT_1_REGS (0x4A100200) 77 #define AM33XX_CPSW_SLIVER_1_REGS (0x4A100D80) 78 #define AM33XX_CPSW_PORT_2_REGS (0x4A100300) 79 #define AM33XX_CPSW_SLIVER_2_REGS (0x4A100DC0) 80 #define AM33XX_CPSW_CPPI_RAM_REGS (0x4A102000) 81 82 /** @brief Base address of McASP memory mapped registers */ 83 #define AM33XX_MCASP_1_CTRL_REGS (0x4803C000) 84 #define AM33XX_MCASP_1_FIFO_REGS (AM33XX_MCASP_1_CTRL_REGS + 0x1000) 85 #define AM33XX_MCASP_1_DATA_REGS (0x46400000) 86 87 /** @brief Base address of EMIF memory mapped registers */ 88 #define AM33XX_EMIF_0_REGS (0x4C000000) 89 90 /** @brief Base addresses of RTC memory mapped registers */ 91 #define AM33XX_RTC_0_REGS (0x44E3E000) 92 93 #define CM_PER(base) ((base) + 0) 94 #define CM_PER_L4LS_CLKSTCTRL(base) (CM_PER(base) + 0) 95 #define CM_PER_UART1_CLKCTRL(base) (CM_PER(base) + 0x6C) 96 #define CM_PER_UART2_CLKCTRL(base) (CM_PER(base) + 0x70) 97 #define CM_PER_UART3_CLKCTRL(base) (CM_PER(base) + 0x74) 98 #define CM_PER_UART4_CLKCTRL(base) (CM_PER(base) + 0x78) 99 #define CM_PER_UART5_CLKCTRL(base) (CM_PER(base) + 0x38) 100 #define CM_WKUP(base) ((base) + 0x400) 101 #define CM_WKUP_CLKSTCTRL(base) (CM_WKUP(base) + 0) 102 #define CM_WKUP_UART0_CLKCTRL(base) (CM_WKUP(base) + 0xB4) 103 #define CM_DPLL(base) ((base) + 0x500) 104 #define CM_MPU(base) ((base) + 0x600) 105 #define CM_DEVICE(base) ((base) + 0x700) 106 #define CM_RTC(base) ((base) + 0x800) 107 #define CM_GFX(base) ((base) + 0x900) 108 #define CM_CEFUSE(base) ((base) + 0xA00) 109 #define OCP_AM33XXKET_RAM(base) ((base) + 0xB00) 110 #define PRM_PER(base) ((base) + 0xC00) 111 #define PRM_PER_PWRSTST(base) (PRM_PER(base) + 0x008) 112 #define PRM_PER_PWRSTCTRL(base) (PRM_PER(base) + 0x00C) 113 #define PRM_WKUP(base) ((base) + 0xD00) 114 #define PRM_MPU(base) ((base) + 0xE00) 115 #define PRM_DEVICE(base) ((base) + 0xF00) 116 #define PRM_RTC(base) ((base) + 0x1000) 117 #define PRM_GFX(base) ((base) + 0x1100) 118 #define PRM_CEFUSE(base) ((base) + 0x1200) 119 120 /** @brief Base addresses of PRCM memory mapped registers */ 121 #define AM33XX_PRCM_REGS (0x44E00000) 122 #define AM33XX_CM_PER_REGS CM_PER(AM33XX_PRCM_REGS) 123 #define AM33XX_CM_WKUP_REGS CM_WKUP(AM33XX_PRCM_REGS) 124 #define AM33XX_CM_DPLL_REGS CM_DPLL(AM33XX_PRCM_REGS) 125 #define AM33XX_CM_MPU_REGS CM_MPU(AM33XX_PRCM_REGS) 126 #define AM33XX_CM_DEVICE_REGS CM_DEVICE(AM33XX_PRCM_REGS) 127 #define AM33XX_CM_RTC_REGS CM_RTC(AM33XX_PRCM_REGS) 128 #define AM33XX_CM_GFX_REGS CM_GFX(AM33XX_PRCM_REGS) 129 #define AM33XX_CM_CEFUSE_REGS CM_CEFUSE(AM33XX_PRCM_REGS) 130 #define AM33XX_OCP_AM33XXKET_RAM_REGS OCP_AM33XXKET_RAM(AM33XX_PRCM_REGS) 131 #define AM33XX_PRM_PER_REGS PRM_PER(AM33XX_PRCM_REGS) 132 #define AM33XX_PRM_WKUP_REGS PRM_WKUP(AM33XX_PRCM_REGS) 133 #define AM33XX_PRM_MPU_REGS PRM_MPU(AM33XX_PRCM_REGS) 134 #define AM33XX_PRM_DEVICE_REGS PRM_DEVICE(AM33XX_PRCM_REGS) 135 #define AM33XX_PRM_RTC_REGS PRM_RTC(AM33XX_PRCM_REGS) 136 #define AM33XX_PRM_GFX_REGS PRM_GFX(AM33XX_PRCM_REGS) 137 #define AM33XX_PRM_CEFUSE_REGS PRM_CEFUSE(AM33XX_PRCM_REGS) 138 139 /** @brief Base address of control module memory mapped registers */ 140 #define AM33XX_CONTROL_REGS (0x44E10000) 141 142 143 /** @brief Base address of Channel controller memory mapped registers */ 144 #define AM33XX_EDMA30CC_0_REGS (0x49000000) 145 146 /** @brief Base address of DCAN module memory mapped registers */ 147 #define AM33XX_DCAN_0_REGS (0x481CC000) 148 #define AM33XX_DCAN_1_REGS (0x481D0000) 149 150 /******************************************************************************\ 151 * Parameterizable Configuration:- These are fed directly from the RTL 152 * parameters for the given AM33XX 153 \******************************************************************************/ 154 #define TPCC_MUX(n) 0xF90 + ((n) * 4) 155 156 157 #define AM33XX_LCDC_0_REGS 0x4830E000 158 159 #define AM33XX_ADC_TSC_0_REGS 0x44E0D000 160 161 /** @brief Base addresses of PWMSS memory mapped registers. */ 162 163 #define AM33XX_PWMSS0_REGS (0x48300000) 164 #define AM33XX_PWMSS1_REGS (0x48302000) 165 #define AM33XX_PWMSS2_REGS (0x48304000) 166 167 #define AM33XX_ECAP_REGS (0x00000100) 168 #define AM33XX_EQEP_REGS (0x00000180) 169 #define AM33XX_EPWM_REGS (0x00000200) 170 171 #define AM33XX_ECAP_0_REGS (AM33XX_PWMSS0_REGS + AM33XX_ECAP_REGS) 172 #define AM33XX_ECAP_1_REGS (AM33XX_PWMSS1_REGS + AM33XX_ECAP_REGS) 173 #define AM33XX_ECAP_2_REGS (AM33XX_PWMSS2_REGS + AM33XX_ECAP_REGS) 174 175 #define AM33XX_EQEP_0_REGS (AM33XX_PWMSS0_REGS + AM33XX_EQEP_REGS) 176 #define AM33XX_EQEP_1_REGS (AM33XX_PWMSS1_REGS + AM33XX_EQEP_REGS) 177 #define AM33XX_EQEP_2_REGS (AM33XX_PWMSS2_REGS + AM33XX_EQEP_REGS) 178 179 #define AM33XX_EPWM_0_REGS (AM33XX_PWMSS0_REGS + AM33XX_EPWM_REGS) 180 #define AM33XX_EPWM_1_REGS (AM33XX_PWMSS1_REGS + AM33XX_EPWM_REGS) 181 #define AM33XX_EPWM_2_REGS (AM33XX_PWMSS2_REGS + AM33XX_EPWM_REGS) 182 183 #define AM33XX_EPWM_MODULE_FREQ 100 184 185 /* PRCM registers */ 186 #define CM_PER_L4LS_CLKSTCTRL_REG(base) REG32((base) + 0x0) 187 #define CM_PER_UART1_CLKCTRL_REG(base) REG32(CM_PER_UART1_CLKCTRL(base)) 188 #define CM_PER_UART2_CLKCTRL_REG(base) REG32(CM_PER_UART2_CLKCTRL(base)) 189 #define CM_PER_UART3_CLKCTRL_REG(base) REG32(CM_PER_UART3_CLKCTRL(base)) 190 #define CM_PER_UART4_CLKCTRL_REG(base) REG32(CM_PER_UART4_CLKCTRL(base)) 191 #define CM_PER_UART5_CLKCTRL_REG(base) REG32(CM_PER_UART5_CLKCTRL(base)) 192 193 #define CM_PER_TIMER7_CLKCTRL(base) REG32((base) + 0x7C) 194 #define CM_PER_TIMER2_CLKCTRL(base) REG32((base) + 0x80) 195 196 #define PRM_PER_PWRSTST_REG(base) REG32(PRM_PER_PWRSTST(base)) 197 #define PRM_PER_PWRSTCTRL_REG(base) REG32(PRM_PER_PWRSTCTRL(base)) 198 199 #define CM_WKUP_CLKSTCTRL_REG(base) REG32(CM_WKUP_CLKSTCTRL(base)) 200 #define CM_WKUP_UART0_CLKCTRL_REG(base) REG32(CM_WKUP_UART0_CLKCTRL(base)) 201 202 #define CM_DPLL_CLKSEL_TIMER7_CLK(base) REG32(CM_DPLL(base) + 0x4) 203 #define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8) 204 205 /* timer registers */ 206 #define DMTIMER_TIDR(base) REG32(base + 0x0) 207 #define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) 208 #define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) 209 #define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) 210 #define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) 211 #define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) 212 #define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) 213 #define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) 214 #define DMTIMER_TCLR(base) REG32(base + 0x38) 215 #define DMTIMER_TCRR(base) REG32(base + 0x3C) 216 #define DMTIMER_TLDR(base) REG32(base + 0x40) 217 #define DMTIMER_TTGR(base) REG32(base + 0x44) 218 #define DMTIMER_TWPS(base) REG32(base + 0x48) 219 #define DMTIMER_TMAR(base) REG32(base + 0x4C) 220 #define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) 221 #define DMTIMER_TSICR(base) REG32(base + 0x54) 222 223 #define EMU_INT 0 224 #define COMMTX_INT 1 225 #define COMMRX_INT 2 226 #define BENCH_INT 3 227 #define ELM_IRQ_INT 4 228 #define NMI_INT 7 229 #define L3DEBUG_INT 9 230 #define L3APP_INT 10 231 #define PRCM_INT 11 232 #define EDMACOMP_INT 12 233 #define EDMAMPERR_INT 13 234 #define EDMAERR_INT 14 235 #define ADC_TSC_GEN_INT 16 236 #define USBSS_INT 17 237 #define USB_INT0 18 238 #define USB_INT1 19 239 #define PRU_ICSS_EVTOUT0_INT 20 240 #define PRU_ICSS_EVTOUT1_INT 21 241 #define PRU_ICSS_EVTOUT2_INT 22 242 #define PRU_ICSS_EVTOUT3_INT 23 243 #define PRU_ICSS_EVTOUT4_INT 24 244 #define PRU_ICSS_EVTOUT5_INT 25 245 #define PRU_ICSS_EVTOUT6_INT 26 246 #define PRU_ICSS_EVTOUT7_INT 27 247 #define MMCSD1_INT 28 248 #define MMCSD2_INT 29 249 #define I2C2_INT 30 250 #define ECAP0_INT 31 251 #define GPIO_INT2A 32 252 #define GPIO_INT2B 33 253 #define USBWAKEUP_INT 34 254 #define LCDC_INT 36 255 #define GFX_INT 37 256 #define EPWM2_INT 39 257 #define CPSW_RXTHR0_INT 40 258 #define CPSW_RX_INT0 41 259 #define CPSW_TX_INT0 42 260 #define CPSW_MISC0_INT 43 261 #define UART3_INT 44 262 #define UART4_INT 45 263 #define UART5_INT 46 264 #define ECAP1_INT 47 265 #define DCAN0_INT0 52 266 #define DCAN0_INT1 53 267 #define DCAN0_PARITY 54 268 #define DCAN1_INT0 55 269 #define DCAN1_INT1 56 270 #define DCAN1_PARITY 57 271 #define EPWM0_TZINT 58 272 #define EPWM1_TZINT 59 273 #define EPWM2_TZINT 60 274 #define ECAP2_INT 61 275 #define GPIO_INT3A 62 276 #define GPIO_INT3B 63 277 #define MMCSD0_INT 64 278 #define MCSPI0_INT 65 279 #define TINT0 66 280 #define TINT1_1MS 67 281 #define TINT2 68 282 #define TINT3 69 283 #define I2C0_INT 70 284 #define I2C1_INT 71 285 #define UART0_INT 72 286 #define UART1_INT 73 287 #define UART2_INT 74 288 #define RTC_INT 75 289 #define RTC_ALARM_INT 76 290 #define MB_INT0 77 291 #define M3_TXEV 78 292 #define EQEP0_INT 79 293 #define MACTX_INT0 80 294 #define MCARX_INT0 81 295 #define MCATX_INT1 82 296 #define MCARX_INT1 83 297 #define EPWM0_INT 86 298 #define EPWM1_INT 87 299 #define EQEP1_INT 88 300 #define EQEP2_INT 89 301 #define DMA_INTR_PIN2 90 302 #define WDT1_INT 91 303 #define TINT4 92 304 #define TINT5 93 305 #define TINT6 94 306 #define TINT7 95 307 #define GPIO_INT0A 96 308 #define GPIO_INT0B 97 309 #define GPIO_INT1A 98 310 #define GPIO_INT1B 99 311 #define GPMC_INT 100 312 #define DDRERR0 101 313 #define TCERR_INT0 112 314 #define TCERR_INT1 113 315 #define TCERR_INT2 114 316 #define ADC_TSC_PEN_INT 115 317 #define SMRFLX_MPU 120 318 #define SMRFLX_CORE 121 319 #define DMA_INTR_PIN0 123 320 #define DMA_INTR_PIN1 124 321 #define MCSPI1_INT 125 322 323 struct rt_hw_register 324 { 325 unsigned long r0; 326 unsigned long r1; 327 unsigned long r2; 328 unsigned long r3; 329 unsigned long r4; 330 unsigned long r5; 331 unsigned long r6; 332 unsigned long r7; 333 unsigned long r8; 334 unsigned long r9; 335 unsigned long r10; 336 unsigned long fp; 337 unsigned long ip; 338 unsigned long sp; 339 unsigned long lr; 340 unsigned long pc; 341 unsigned long cpsr; 342 unsigned long ORIG_r0; 343 }; 344 345 #define USERMODE 0x10 346 #define FIQMODE 0x11 347 #define IRQMODE 0x12 348 #define SVCMODE 0x13 349 #define ABORTMODE 0x17 350 #define UNDEFMODE 0x1b 351 #define MODEMASK 0x1f 352 #define NOINT 0xc0 353 354 #endif 355