1 /*!
2  * @file       apm32e10x_dma.h
3  *
4  * @brief      This file contains all the functions prototypes for the DMA firmware library
5  *
6  * @version     V1.0.2
7  *
8  * @date        2022-12-31
9  *
10  * @attention
11  *
12  *  Copyright (C) 2021-2023 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 /* Define to prevent recursive inclusion */
27 #ifndef __APM32E10X_DMA_H
28 #define __APM32E10X_DMA_H
29 
30 /* Includes */
31 #include "apm32e10x.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 /** @addtogroup APM32E10x_StdPeriphDriver
38   @{
39 */
40 
41 /** @addtogroup DMA_Driver
42   @{
43 */
44 
45 /** @defgroup DMA_Enumerations Enumerations
46   @{
47 */
48 
49 /**
50  * @brief   DMA Transmission direction
51  */
52 typedef enum
53 {
54     DMA_DIR_PERIPHERAL_SRC,
55     DMA_DIR_PERIPHERAL_DST
56 } DMA_DIR_T;
57 
58 /**
59  * @brief   DMA Peripheral address increment
60  */
61 typedef enum
62 {
63     DMA_PERIPHERAL_INC_DISABLE,
64     DMA_PERIPHERAL_INC_ENABLE
65 } DMA_PERIPHERAL_INC_T;
66 
67 /**
68  * @brief   DMA Memory address increment
69  */
70 typedef enum
71 {
72     DMA_MEMORY_INC_DISABLE,
73     DMA_MEMORY_INC_ENABLE
74 } DMA_MEMORY_INC_T;
75 
76 /**
77  * @brief   DMA Peripheral Data Size
78  */
79 typedef enum
80 {
81     DMA_PERIPHERAL_DATA_SIZE_BYTE,
82     DMA_PERIPHERAL_DATA_SIZE_HALFWORD,
83     DMA_PERIPHERAL_DATA_SIZE_WOED
84 } DMA_PERIPHERAL_DATA_SIZE_T;
85 
86 /**
87  * @brief   DMA Memory Data Size
88  */
89 typedef enum
90 {
91     DMA_MEMORY_DATA_SIZE_BYTE,
92     DMA_MEMORY_DATA_SIZE_HALFWORD,
93     DMA_MEMORY_DATA_SIZE_WOED
94 } DMA_MEMORY_DATA_SIZE_T;
95 
96 /**
97  * @brief   DMA Mode
98  */
99 typedef enum
100 {
101     DMA_MODE_NORMAL,
102     DMA_MODE_CIRCULAR
103 } DMA_LOOP_MODE_T;
104 
105 /**
106  * @brief   DMA priority level
107  */
108 typedef enum
109 {
110     DMA_PRIORITY_LOW,
111     DMA_PRIORITY_MEDIUM,
112     DMA_PRIORITY_HIGH,
113     DMA_PRIORITY_VERYHIGH
114 } DMA_PRIORITY_T;
115 
116 /**
117  * @brief   DMA Memory to Memory
118  */
119 typedef enum
120 {
121     DMA_M2MEN_DISABLE,
122     DMA_M2MEN_ENABLE
123 } DMA_M2MEN_T;
124 
125 /**
126  * @brief   DMA interrupt
127  */
128 typedef enum
129 {
130     DMA_INT_TC   = 0x00000002,
131     DMA_INT_HT   = 0x00000004,
132     DMA_INT_TERR = 0x00000008
133 } DMA_INT_T;
134 
135 /**
136  * @brief   DMA Flag
137  */
138 typedef enum
139 {
140     DMA1_FLAG_GINT1 = 0x00000001,
141     DMA1_FLAG_TC1   = 0x00000002,
142     DMA1_FLAG_HT1   = 0x00000004,
143     DMA1_FLAG_TERR1 = 0x00000008,
144     DMA1_FLAG_GINT2 = 0x00000010,
145     DMA1_FLAG_TC2   = 0x00000020,
146     DMA1_FLAG_HT2   = 0x00000040,
147     DMA1_FLAG_TERR2 = 0x00000080,
148     DMA1_FLAG_GINT3 = 0x00000100,
149     DMA1_FLAG_TC3   = 0x00000200,
150     DMA1_FLAG_HT3   = 0x00000400,
151     DMA1_FLAG_TERR3 = 0x00000800,
152     DMA1_FLAG_GINT4 = 0x00001000,
153     DMA1_FLAG_TC4   = 0x00002000,
154     DMA1_FLAG_HT4   = 0x00004000,
155     DMA1_FLAG_TERR4 = 0x00008000,
156     DMA1_FLAG_GINT5 = 0x00010000,
157     DMA1_FLAG_TC5   = 0x00020000,
158     DMA1_FLAG_HT5   = 0x00040000,
159     DMA1_FLAG_TERR5 = 0x00080000,
160     DMA1_FLAG_GINT6 = 0x00100000,
161     DMA1_FLAG_TC6   = 0x00200000,
162     DMA1_FLAG_HT6   = 0x00400000,
163     DMA1_FLAG_TERR6 = 0x00800000,
164     DMA1_FLAG_GINT7 = 0x01000000,
165     DMA1_FLAG_TC7   = 0x02000000,
166     DMA1_FLAG_HT7   = 0x04000000,
167     DMA1_FLAG_TERR7 = 0x08000000,
168 
169     DMA2_FLAG_GINT1 = 0x10000001,
170     DMA2_FLAG_TC1   = 0x10000002,
171     DMA2_FLAG_HT1   = 0x10000004,
172     DMA2_FLAG_TERR1 = 0x10000008,
173     DMA2_FLAG_GINT2 = 0x10000010,
174     DMA2_FLAG_TC2   = 0x10000020,
175     DMA2_FLAG_HT2   = 0x10000040,
176     DMA2_FLAG_TERR2 = 0x10000080,
177     DMA2_FLAG_GINT3 = 0x10000100,
178     DMA2_FLAG_TC3   = 0x10000200,
179     DMA2_FLAG_HT3   = 0x10000400,
180     DMA2_FLAG_TERR3 = 0x10000800,
181     DMA2_FLAG_GINT4 = 0x10001000,
182     DMA2_FLAG_TC4   = 0x10002000,
183     DMA2_FLAG_HT4   = 0x10004000,
184     DMA2_FLAG_TERR4 = 0x10008000,
185     DMA2_FLAG_GINT5 = 0x10010000,
186     DMA2_FLAG_TC5   = 0x10020000,
187     DMA2_FLAG_HT5   = 0x10040000,
188     DMA2_FLAG_TERR5 = 0x10080000
189 } DMA_FLAG_T;
190 
191 /**
192  * @brief DMA Interrupt Flag
193  */
194 typedef enum
195 {
196     DMA1_INT_FLAG_GINT1   = 0x00000001,
197     DMA1_INT_FLAG_TC1     = 0x00000002,
198     DMA1_INT_FLAG_HT1     = 0x00000004,
199     DMA1_INT_FLAG_TERR1   = 0x00000008,
200     DMA1_INT_FLAG_GINT2   = 0x00000010,
201     DMA1_INT_FLAG_TC2     = 0x00000020,
202     DMA1_INT_FLAG_HT2     = 0x00000040,
203     DMA1_INT_FLAG_TERR2   = 0x00000080,
204     DMA1_INT_FLAG_GINT3   = 0x00000100,
205     DMA1_INT_FLAG_TC3     = 0x00000200,
206     DMA1_INT_FLAG_HT3     = 0x00000400,
207     DMA1_INT_FLAG_TERR3   = 0x00000800,
208     DMA1_INT_FLAG_GINT4   = 0x00001000,
209     DMA1_INT_FLAG_TC4     = 0x00002000,
210     DMA1_INT_FLAG_HT4     = 0x00004000,
211     DMA1_INT_FLAG_TERR4   = 0x00008000,
212     DMA1_INT_FLAG_GINT5   = 0x00010000,
213     DMA1_INT_FLAG_TC5     = 0x00020000,
214     DMA1_INT_FLAG_HT5     = 0x00040000,
215     DMA1_INT_FLAG_TERR5   = 0x00080000,
216     DMA1_INT_FLAG_GINT6   = 0x00100000,
217     DMA1_INT_FLAG_TC6     = 0x00200000,
218     DMA1_INT_FLAG_HT6     = 0x00400000,
219     DMA1_INT_FLAG_TERR6   = 0x00800000,
220     DMA1_INT_FLAG_GINT7   = 0x01000000,
221     DMA1_INT_FLAG_TC7     = 0x02000000,
222     DMA1_INT_FLAG_HT7     = 0x04000000,
223     DMA1_INT_FLAG_TERR7   = 0x08000000,
224 
225     DMA2_INT_FLAG_GINT1   = 0x10000001,
226     DMA2_INT_FLAG_TC1     = 0x10000002,
227     DMA2_INT_FLAG_HT1     = 0x10000004,
228     DMA2_INT_FLAG_TERR1   = 0x10000008,
229     DMA2_INT_FLAG_GINT2   = 0x10000010,
230     DMA2_INT_FLAG_TC2     = 0x10000020,
231     DMA2_INT_FLAG_HT2     = 0x10000040,
232     DMA2_INT_FLAG_TERR2   = 0x10000080,
233     DMA2_INT_FLAG_GINT3   = 0x10000100,
234     DMA2_INT_FLAG_TC3     = 0x10000200,
235     DMA2_INT_FLAG_HT3     = 0x10000400,
236     DMA2_INT_FLAG_TERR3   = 0x10000800,
237     DMA2_INT_FLAG_GINT4   = 0x10001000,
238     DMA2_INT_FLAG_TC4     = 0x10002000,
239     DMA2_INT_FLAG_HT4     = 0x10004000,
240     DMA2_INT_FLAG_TERR4   = 0x10008000,
241     DMA2_INT_FLAG_GINT5   = 0x10010000,
242     DMA2_INT_FLAG_TC5     = 0x10020000,
243     DMA2_INT_FLAG_HT5     = 0x10040000,
244     DMA2_INT_FLAG_TERR5   = 0x10080000
245 } DMA_INT_FLAG_T;
246 
247 /**@} end of group DMA_Enumerations */
248 
249 
250 /** @defgroup DMA_Structures Structures
251   @{
252 */
253 
254 /**
255  * @brief    DMA Config struct definition
256  */
257 typedef struct
258 {
259     uint32_t                   peripheralBaseAddr;
260     uint32_t                   memoryBaseAddr;
261     DMA_DIR_T                  dir;
262     uint32_t                   bufferSize;
263     DMA_PERIPHERAL_INC_T       peripheralInc;
264     DMA_MEMORY_INC_T           memoryInc;
265     DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize;
266     DMA_MEMORY_DATA_SIZE_T     memoryDataSize;
267     DMA_LOOP_MODE_T            loopMode;
268     DMA_PRIORITY_T             priority;
269     DMA_M2MEN_T                M2M;
270 } DMA_Config_T;
271 
272 /**@} end of group DMA_Structures */
273 
274 
275 /** @defgroup DMA_Functions Functions
276   @{
277 */
278 
279 /** Reset and configuration */
280 void DMA_Reset(DMA_Channel_T *channel);
281 void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
282 void DMA_ConfigStructInit( DMA_Config_T* dmaConfig);
283 void DMA_Enable(DMA_Channel_T *channel);
284 void DMA_Disable(DMA_Channel_T *channel);
285 
286 /** Data number */
287 void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber);
288 uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel);
289 
290 /** Interrupt and flag */
291 void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
292 void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
293 uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag);
294 void DMA_ClearStatusFlag(uint32_t flag);
295 uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
296 void DMA_ClearIntFlag(uint32_t flag);
297 
298 /**@} end of group DMA_Functions */
299 /**@} end of group DMA_Driver */
300 /**@} end of group APM32E10x_StdPeriphDriver */
301 
302 #ifdef __cplusplus
303 }
304 #endif
305 
306 #endif /* __APM32E10X_DMA_H */
307