1 /*! 2 * @file apm32e10x_i2c.h 3 * 4 * @brief This file contains all the functions prototypes for the I2C firmware library 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-12-31 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2023 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32E10X_I2C_H 28 #define __APM32E10X_I2C_H 29 30 /* Includes */ 31 #include "apm32e10x.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /** @addtogroup APM32E10x_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup I2C_Driver 42 @{ 43 */ 44 45 /** @defgroup I2C_Enumerations Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief I2C Mode 51 */ 52 typedef enum 53 { 54 I2C_MODE_I2C = 0x0000, 55 I2C_MODE_SMBUUSDEVICE = 0x0002, 56 I2C_MODE_SMBUSHOST = 0x000A 57 } I2C_MODE_T; 58 59 /** 60 * @brief I2C duty cycle in fast mode 61 */ 62 typedef enum 63 { 64 I2C_DUTYCYCLE_16_9 = 0x4000, 65 I2C_DUTYCYCLE_2 = 0xBFFF 66 } I2C_DUTYCYCLE_T; 67 68 /** 69 * @brief I2C acknowledgement 70 */ 71 typedef enum 72 { 73 I2C_ACK_DISABLE, 74 I2C_ACK_ENABLE 75 } I2C_ACK_T; 76 77 /** 78 * @brief I2C acknowledged address 79 */ 80 typedef enum 81 { 82 I2C_ACK_ADDRESS_7BIT = 0x4000, 83 I2C_ACK_ADDRESS_10BIT = 0xC000 84 } I2C_ACK_ADDRESS_T; 85 86 /** 87 * @brief I2C interrupts definition 88 */ 89 typedef enum 90 { 91 I2C_INT_BUF = 0x0400, 92 I2C_INT_EVT = 0x0200, 93 I2C_INT_ERR = 0x0100 94 } I2C_INT_T; 95 96 /** 97 * @brief I2C transfer direction 98 */ 99 100 typedef enum 101 { 102 I2C_DIRECTION_TX, 103 I2C_DIRECTION_RX 104 } I2C_DIRECTION_T; 105 106 /** 107 * @brief I2C Register 108 */ 109 typedef enum 110 { 111 I2C_REGISTER_CTRL1, 112 I2C_REGISTER_CTRL2, 113 I2C_REGISTER_SADDR1, 114 I2C_REGISTER_SADDR2, 115 I2C_REGISTER_DATA, 116 I2C_REGISTER_STS1, 117 I2C_REGISTER_STS2, 118 I2C_REGISTER_CLKCTRL, 119 I2C_REGISTER_RISETMAX, 120 I2C_REGISTER_SWITCH 121 } I2C_REGISTER_T; 122 123 /** 124 * @brief I2C NCAK position 125 */ 126 typedef enum 127 { 128 I2C_NACK_POSITION_NEXT, 129 I2C_NACK_POSITION_CURRENT 130 } I2C_NACK_POSITION_T; 131 132 /** 133 * @brief I2C SMBus alert pin level 134 */ 135 typedef enum 136 { 137 I2C_SMBUSALER_LOW, 138 I2C_SMBUSALER_HIGH 139 } I2C_SMBUSALER_T; 140 141 /** 142 * @brief I2C PEC position 143 */ 144 typedef enum 145 { 146 I2C_PEC_POSITION_NEXT, 147 I2C_PEC_POSITION_CURRENT 148 } I2C_PEC_POSITION_T; 149 150 /** 151 * @brief I2C Events 152 */ 153 typedef enum 154 { 155 /* I2C Master Events */ 156 /* Event 5: Communication start event */ 157 I2C_EVENT_MASTER_MODE_SELECT = 0x00030001, /*!< BUSBSYFLG, MSFLG and STARTFLG flag */ 158 159 /* 160 Event 6: 7-bit Address Acknowledge 161 in case of master receiver 162 */ 163 I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = 0x00070082, /*!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */ 164 I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = 0x00030002, /*!< BUSBSYFLG, MSFLG and ADDRFLG flags */ 165 /** 166 Event 9: Master has sent the first byte 167 in 10-bit address mode 168 */ 169 I2C_EVENT_MASTER_MODE_ADDRESS10 = 0x00030008, /*!< BUSBSYFLG, MSFLG and ADDR10FLG flags */ 170 171 /* Master RECEIVER mode */ 172 /* Event 7 */ 173 I2C_EVENT_MASTER_BYTE_RECEIVED = 0x00030040, /*!< BUSBSYFLG, MSFLG and RXBNEFLG flags */ 174 175 /* Master TRANSMITTER mode */ 176 /* Event 8 */ 177 I2C_EVENT_MASTER_BYTE_TRANSMITTING = 0x00070080, /*!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */ 178 /* Event 8_2 */ 179 I2C_EVENT_MASTER_BYTE_TRANSMITTED = 0x00070084, /*!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */ 180 181 182 /* EV1 (all the events below are variants of EV1) */ 183 /* 1, Case of One Single Address managed by the slave */ 184 I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = 0x00020002, /*!< BUSBSYFLG and ADDRFLG flags */ 185 I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = 0x00060082, /*!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */ 186 187 /* 2, Case of Dual address managed by the slave */ 188 I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = 0x00820000, /*!< DUALF and BUSBSYFLG flags */ 189 I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = 0x00860080, /*!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */ 190 191 /* 3, Case of General Call enabled for the slave */ 192 I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = 0x00120000, /*!< GENCALL and BUSBSYFLG flags */ 193 194 195 /* Slave RECEIVER mode */ 196 /* EV2 */ 197 I2C_EVENT_SLAVE_BYTE_RECEIVED = 0x00020040, /*!< BUSBSYFLG and RXBNEFLG flags */ 198 /* EV4 */ 199 I2C_EVENT_SLAVE_STOP_DETECTED = 0x00000010, /*!< STOPFLG flag */ 200 201 /* Slave TRANSMITTER mode */ 202 /* EV3 */ 203 I2C_EVENT_SLAVE_BYTE_TRANSMITTED = 0x00060084, /*!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */ 204 I2C_EVENT_SLAVE_BYTE_TRANSMITTING = 0x00060080, /*!< TRFLG, BUSBSYFLG and TXBEFLG flags */ 205 /* EV3_2 */ 206 I2C_EVENT_SLAVE_ACK_FAILURE = 0x00000400, /*!< AEFLG flag */ 207 } I2C_EVENT_T; 208 209 /** 210 * @brief I2C flags 211 */ 212 typedef enum 213 { 214 /* STS2 register flags */ 215 I2C_FLAG_DUALADDR, 216 I2C_FLAG_SMMHADDR, 217 I2C_FLAG_SMBDADDR, 218 I2C_FLAG_GENCALL, 219 I2C_FLAG_TR, 220 I2C_FLAG_BUSBSY, 221 I2C_FLAG_MS, 222 223 /* STS1 register flags */ 224 I2C_FLAG_SMBALT, 225 I2C_FLAG_TTE, 226 I2C_FLAG_PECE, 227 I2C_FLAG_OVRUR, 228 I2C_FLAG_AE, 229 I2C_FLAG_AL, 230 I2C_FLAG_BERR, 231 I2C_FLAG_TXBE, 232 I2C_FLAG_RXBNE, 233 I2C_FLAG_STOP, 234 I2C_FLAG_ADDR10, 235 I2C_FLAG_BTC, 236 I2C_FLAG_ADDR, 237 I2C_FLAG_START, 238 } I2C_FLAG_T; 239 240 /** 241 * @brief I2C interrupt 242 */ 243 typedef enum 244 { 245 I2C_INT_FLAG_SMBALT = 0x01008000, 246 I2C_INT_FLAG_TTE = 0x01004000, 247 I2C_INT_FLAG_PECE = 0x01001000, 248 I2C_INT_FLAG_OVRUR = 0x01000800, 249 I2C_INT_FLAG_AE = 0x01000400, 250 I2C_INT_FLAG_AL = 0x01000200, 251 I2C_INT_FLAG_BERR = 0x01000100, 252 I2C_INT_FLAG_TXBE = 0x06000080, 253 I2C_INT_FLAG_RXBNE = 0x06000040, 254 I2C_INT_FLAG_STOP = 0x02000010, 255 I2C_INT_FLAG_ADDR10 = 0x02000008, 256 I2C_INT_FLAG_BTC = 0x02000004, 257 I2C_INT_FLAG_ADDR = 0x02000002, 258 I2C_INT_FLAG_START = 0x02000001, 259 } I2C_INT_FLAG_T; 260 261 /**@} end of group I2C_Enumerations */ 262 263 /** @defgroup I2C_Structures Structures 264 @{ 265 */ 266 267 /** 268 * @brief I2C Config structure definition 269 */ 270 typedef struct 271 { 272 uint32_t clockSpeed; 273 I2C_MODE_T mode; 274 I2C_DUTYCYCLE_T dutyCycle; 275 uint16_t ownAddress1; 276 I2C_ACK_T ack; 277 I2C_ACK_ADDRESS_T ackAddress; 278 } I2C_Config_T; 279 280 /**@} end of group I2C_Structures */ 281 282 283 /** @defgroup I2C_Functions Functions 284 @{ 285 */ 286 287 /* I2C reset and configuration */ 288 void I2C_Reset(I2C_T* i2c); 289 void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig); 290 void I2C_ConfigStructInit(I2C_Config_T* i2cConfig); 291 void I2C_Enable(I2C_T* i2c); 292 void I2C_Disable(I2C_T* i2c); 293 void I2C_EnableGenerateStart(I2C_T* i2c); 294 void I2C_DisableGenerateStart(I2C_T* i2c); 295 void I2C_EnableGenerateStop(I2C_T* i2c); 296 void I2C_DisableGenerateStop(I2C_T* i2c); 297 void I2C_EnableAcknowledge(I2C_T* i2c); 298 void I2C_DisableAcknowledge(I2C_T* i2c); 299 void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address); 300 void I2C_EnableDualAddress(I2C_T* i2c); 301 void I2C_DisableDualAddress(I2C_T* i2c); 302 void I2C_EnableGeneralCall(I2C_T* i2c); 303 void I2C_DisableGeneralCall(I2C_T* i2c); 304 305 /* Transmit Configuration */ 306 void I2C_TxData(I2C_T* i2c, uint8_t data); 307 uint8_t I2C_RxData(I2C_T* i2c); 308 void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction); 309 uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister); 310 void I2C_EnableSoftwareReset(I2C_T* i2c); 311 void I2C_DisableSoftwareReset(I2C_T* i2c); 312 void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition); 313 void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState); 314 void I2C_EnablePECTransmit(I2C_T* i2c); 315 void I2C_DisablePECTransmit(I2C_T* i2c); 316 void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition); 317 void I2C_EnablePEC(I2C_T* i2c); 318 void I2C_DisablePEC(I2C_T* i2c); 319 uint8_t I2C_ReadPEC(I2C_T* i2c); 320 void I2C_EnableARP(I2C_T* i2c); 321 void I2C_DisableARP(I2C_T* i2c); 322 void I2C_EnableStretchClock(I2C_T* i2c); 323 void I2C_DisableStretchClock(I2C_T* i2c); 324 void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle); 325 326 /* DMA */ 327 void I2C_EnableDMA(I2C_T* i2c); 328 void I2C_DisableDMA(I2C_T* i2c); 329 void I2C_EnableDMALastTransfer(I2C_T* i2c); 330 void I2C_DisableDMALastTransfer(I2C_T* i2c); 331 332 /* Interrupts and flags */ 333 void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt); 334 void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt); 335 uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent); 336 uint32_t I2C_ReadLastEvent(I2C_T* i2c); 337 uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); 338 void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); 339 uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag); 340 void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag); 341 342 /**@} end of group I2C_Functions*/ 343 /**@} end of group I2C_Driver*/ 344 /**@} end of group APM32E10x_StdPeriphDriver*/ 345 346 #ifdef __cplusplus 347 } 348 #endif 349 350 #endif /* __APM32E10X_I2C_H */ 351