1 /*! 2 * @file apm32e10x_sdio.c 3 * 4 * @brief This file provides all the SDIO firmware functions 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-12-31 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2023 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 #include "apm32e10x_sdio.h" 27 #include "apm32e10x_rcm.h" 28 29 /** @addtogroup APM32E10x_StdPeriphDriver 30 @{ 31 */ 32 33 /** @addtogroup SDIO_Driver 34 * @brief SDIO driver modules 35 @{ 36 */ 37 38 /** @defgroup SDIO_Functions Functions 39 @{ 40 */ 41 42 /*! 43 * @brief Reset sdio peripheral registers to their default reset values 44 * 45 * @param None 46 * 47 * @retval None 48 */ SDIO_Reset(void)49void SDIO_Reset(void) 50 { 51 SDIO->PWRCTRL = 0x00000000; 52 SDIO->CLKCTRL = 0x00000000; 53 SDIO->ARG = 0x00000000; 54 SDIO->CMD = 0x00000000; 55 SDIO->DATATIME = 0x00000000; 56 SDIO->DATALEN = 0x00000000; 57 SDIO->DCTRL = 0x00000000; 58 SDIO->ICF = 0x00C007FF; 59 SDIO->MASK = 0x00000000; 60 } 61 62 /*! 63 * @brief Config the SDIO peripheral according to the specified parameters in the sdioConfig 64 * 65 * @param sdioConfig: pointer to a SDIO_Config_T structure 66 * 67 * @retval None 68 */ SDIO_Config(SDIO_Config_T * sdioConfig)69void SDIO_Config(SDIO_Config_T* sdioConfig) 70 { 71 uint32_t tmp = 0; 72 73 tmp = SDIO->CLKCTRL; 74 tmp &= 0xFFFF8100; 75 76 tmp |= (sdioConfig->clockDiv | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide | 77 sdioConfig->clockEdge | sdioConfig->hardwareFlowControl); 78 79 SDIO->CLKCTRL = tmp; 80 } 81 82 /*! 83 * @brief Fills each SDIO_Config_T member with its default value 84 * 85 * @param sdioConfig: pointer to a SDIO_Config_T structure 86 * 87 * @retval None 88 */ SDIO_ConfigStructInit(SDIO_Config_T * sdioConfig)89void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig) 90 { 91 sdioConfig->clockDiv = 0x00; 92 sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING; 93 sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE; 94 sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; 95 sdioConfig->busWide = SDIO_BUSWIDE_1B; 96 sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; 97 } 98 99 /*! 100 * @brief Enables the SDIO clock 101 * 102 * @param None 103 * 104 * @retval None 105 */ SDIO_EnableClock(void)106void SDIO_EnableClock(void) 107 { 108 *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)SET; 109 } 110 111 /*! 112 * @brief Disables the SDIO clock 113 * 114 * @param None 115 * 116 * @retval None 117 */ SDIO_DisableClock(void)118void SDIO_DisableClock(void) 119 { 120 *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)RESET; 121 } 122 123 /*! 124 * @brief Sets the power status of the controller 125 * 126 * @param powerState: new state of the Power state 127 * The parameter can be one of following values: 128 * @arg SDIO_POWER_STATE_OFF 129 * @arg SDIO_POWER_STATE_ON 130 * @retval None 131 */ SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState)132void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState) 133 { 134 SDIO->PWRCTRL &= 0xFFFFFFFC; 135 SDIO->PWRCTRL |= powerState; 136 } 137 138 /*! 139 * @brief Reads the SDIO power state 140 * 141 * @param None 142 * 143 * @retval The new state SDIO power 144 * 145 * @note 0x00:Power OFF, 0x02:Power UP, 0x03:Power ON 146 */ SDIO_ReadPowerState(void)147uint32_t SDIO_ReadPowerState(void) 148 { 149 return (SDIO->PWRCTRL & (~0xFFFFFFFC)); 150 } 151 152 /*! 153 * @brief Enables the SDIO DMA request 154 * 155 * @param None 156 * 157 * @retval None 158 */ SDIO_EnableDMA(void)159void SDIO_EnableDMA(void) 160 { 161 *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)SET; 162 } 163 164 /*! 165 * @brief Disables the SDIO DMA request 166 * 167 * @param None 168 * 169 * @retval None 170 */ SDIO_DisableDMA(void)171void SDIO_DisableDMA(void) 172 { 173 *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)RESET; 174 } 175 176 /*! 177 * @brief Configs the SDIO Command and send the command 178 * 179 * @param cmdConfig: pointer to a SDIO_CMDConfig_T structure 180 * 181 * @retval None 182 * 183 * @note 184 */ SDIO_TxCommand(SDIO_CMDConfig_T * cmdConfig)185void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig) 186 { 187 uint32_t tmpreg = 0; 188 189 SDIO->ARG = cmdConfig->argument; 190 tmpreg = SDIO->CMD; 191 tmpreg &= 0xFFFFF800; 192 tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response 193 | cmdConfig->wait | cmdConfig->CPSM; 194 SDIO->CMD = tmpreg; 195 } 196 197 /*! 198 * @brief Fills each SDIO_CMD_ConfigStruct_T member with its default value 199 * 200 * @param cmdConfig: pointer to a SDIO_CMDConfig_T structure 201 * 202 * @retval None 203 * 204 * @note 205 */ SDIO_TxCommandStructInit(SDIO_CMDConfig_T * cmdConfig)206void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdConfig) 207 { 208 cmdConfig->argument = 0x00; 209 cmdConfig->cmdIndex = 0x00; 210 cmdConfig->response = SDIO_RESPONSE_NO; 211 cmdConfig->wait = SDIO_WAIT_NO; 212 cmdConfig->CPSM = SDIO_CPSM_DISABLE; 213 } 214 215 /*! 216 * @brief Reads the SDIO command response 217 * 218 * @param None 219 * 220 * @retval The command index of the last command response received 221 * 222 * @note 223 */ SDIO_ReadCommandResponse(void)224uint8_t SDIO_ReadCommandResponse(void) 225 { 226 return (uint8_t)(SDIO->CMDRES); 227 } 228 229 /*! 230 * @brief Reads the SDIO response 231 * 232 * @param res: Specifies the SDIO response register 233 * The parameter can be one of following values: 234 * @arg SDIO_RES1: Response Register 1 235 * @arg SDIO_RES2: Response Register 2 236 * @arg SDIO_RES3: Response Register 3 237 * @arg SDIO_RES4: Response Register 4 238 * 239 * @retval The Corresponding response register value 240 */ SDIO_ReadResponse(SDIO_RES_T res)241uint32_t SDIO_ReadResponse(SDIO_RES_T res) 242 { 243 __IO uint32_t tmp = 0; 244 245 tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res; 246 247 return (*(__IO uint32_t *) tmp); 248 } 249 250 /*! 251 * @brief Configs the SDIO Dataaccording to the specified parameters in the dataConfig 252 * 253 * @param dataConfig: pointer to a SDIO_DataConfig_T structure 254 * 255 * @retval None 256 */ SDIO_ConfigData(SDIO_DataConfig_T * dataConfig)257void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig) 258 { 259 uint32_t tmpreg = 0; 260 261 SDIO->DATATIME = dataConfig->dataTimeOut; 262 263 SDIO->DATALEN = dataConfig->dataLength; 264 265 tmpreg = SDIO->DCTRL; 266 267 tmpreg &= 0xFFFFFF08; 268 269 tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir 270 | dataConfig->transferMode | dataConfig->DPSM; 271 272 SDIO->DCTRL = tmpreg; 273 } 274 275 /*! 276 * @brief Fills each SDIO_DataConfig_T member with its default value 277 * 278 * @param dataConfig: pointer to a SDIO_DataConfig_T structure 279 * 280 * @retval None 281 */ SDIO_ConfigDataStructInit(SDIO_DataConfig_T * dataConfig)282void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig) 283 { 284 dataConfig->dataTimeOut = 0xFFFFFFFF; 285 dataConfig->dataLength = 0x00; 286 dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B; 287 dataConfig->transferDir = SDIO_TRANSFER_DIR_TOCARD; 288 dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK; 289 dataConfig->DPSM = SDIO_DPSM_DISABLE; 290 } 291 292 /*! 293 * @brief Reads the SDIO Data counter 294 * 295 * @param None 296 * 297 * @retval The SDIO Data counter value 298 */ SDIO_ReadDataCounter(void)299uint32_t SDIO_ReadDataCounter(void) 300 { 301 return SDIO->DCNT; 302 } 303 304 /*! 305 * @brief Write the SDIO Data 306 * 307 * @param Data: Write 32-bit data 308 * 309 * @retval None 310 */ SDIO_WriteData(uint32_t data)311void SDIO_WriteData(uint32_t data) 312 { 313 SDIO->FIFODATA = data; 314 } 315 316 /*! 317 * @brief Reads the SDIO Data 318 * 319 * @param None 320 * 321 * @retval The SDIO FIFO Data value 322 */ SDIO_ReadData(void)323uint32_t SDIO_ReadData(void) 324 { 325 return SDIO->FIFODATA; 326 } 327 328 /*! 329 * @brief Reads the SDIO FIFO count value 330 * 331 * @param None 332 * 333 * @retval The SDIO FIFO count value 334 */ SDIO_ReadFIFOCount(void)335uint32_t SDIO_ReadFIFOCount(void) 336 { 337 return SDIO->FIFOCNT; 338 } 339 340 /*! 341 * @brief Enables SDIO start read wait 342 * 343 * @param None 344 * 345 * @retval None 346 */ SDIO_EnableStartReadWait(void)347void SDIO_EnableStartReadWait(void) 348 { 349 *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) SET; 350 } 351 352 /*! 353 * @brief Disables SDIO start read wait 354 * 355 * @param None 356 * 357 * @retval None 358 */ SDIO_DisableStopReadWait(void)359void SDIO_DisableStopReadWait(void) 360 { 361 *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) RESET; 362 } 363 364 /*! 365 * @brief Enables SDIO stop read wait 366 * 367 * @param None 368 * 369 * @retval None 370 */ SDIO_EnableStopReadWait(void)371void SDIO_EnableStopReadWait(void) 372 { 373 *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) SET; 374 } 375 376 /*! 377 * @brief Disables SDIO stop read wait 378 * 379 * @param None 380 * 381 * @retval None 382 */ SDIO_DisableStartReadWait(void)383void SDIO_DisableStartReadWait(void) 384 { 385 *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) RESET; 386 } 387 388 /*! 389 * @brief Sets the read wait interval 390 * 391 * @param readWaitMode: SDIO read Wait Mode 392 * The parameter can be one of following values: 393 * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK 394 * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 395 * 396 * @retval None 397 * 398 * @note 399 */ SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)400void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode) 401 { 402 *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode; 403 } 404 /*! 405 * @brief Enables SDIO SD I/O Mode Operation 406 * 407 * @param None 408 * 409 * @retval None 410 */ SDIO_EnableSDIO(void)411void SDIO_EnableSDIO(void) 412 { 413 *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET; 414 } 415 416 /*! 417 * @brief Disables SDIO SD I/O Mode Operation 418 * 419 * @param None 420 * 421 * @retval None 422 */ SDIO_DisableSDIO(void)423void SDIO_DisableSDIO(void) 424 { 425 *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET; 426 } 427 428 /*! 429 * @brief Ensables SDIO SD I/O Mode suspend command sending 430 * 431 * @param None 432 * 433 * @retval None 434 */ SDIO_EnableTxSDIOSuspend(void)435void SDIO_EnableTxSDIOSuspend(void) 436 { 437 *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)SET; 438 } 439 440 /*! 441 * @brief Disables SDIO SD I/O Mode suspend command sending 442 * 443 * @param None 444 * 445 * @retval None 446 */ SDIO_DisableTxSDIOSuspend(void)447void SDIO_DisableTxSDIOSuspend(void) 448 { 449 *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)RESET; 450 } 451 452 /*! 453 * @brief Enables the command completion signal 454 * 455 * @param None 456 * 457 * @retval None 458 */ SDIO_EnableCommandCompletion(void)459void SDIO_EnableCommandCompletion(void) 460 { 461 *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)SET; 462 } 463 464 /*! 465 * @brief Disables the command completion signal 466 * 467 * @param None 468 * 469 * @retval None 470 */ SDIO_DisableCommandCompletion(void)471void SDIO_DisableCommandCompletion(void) 472 { 473 *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)RESET; 474 } 475 476 /*! 477 * @brief Enables the CE-ATA interrupt 478 * 479 * @param None 480 * 481 * @retval None 482 */ SDIO_EnableCEATAInterrupt(void)483void SDIO_EnableCEATAInterrupt(void) 484 { 485 *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1)); 486 } 487 488 /*! 489 * @brief Disables the CE-ATA interrupt 490 * 491 * @param None 492 * 493 * @retval None 494 */ SDIO_DisableCEATAInterrupt(void)495void SDIO_DisableCEATAInterrupt(void) 496 { 497 *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1)); 498 } 499 500 /*! 501 * @brief Ensables Sends CE-ATA command 502 * 503 * @param None 504 * 505 * @retval None 506 */ SDIO_EnableTxCEATA(void)507void SDIO_EnableTxCEATA(void) 508 { 509 *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)SET; 510 } 511 512 /*! 513 * @brief Disables Sends CE-ATA command 514 * 515 * @param None 516 * 517 * @retval None 518 */ SDIO_DisableTxCEATA(void)519void SDIO_DisableTxCEATA(void) 520 { 521 *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)RESET; 522 } 523 524 /*! 525 * @brief Enables the specified SDIO interrupt 526 * 527 * @param interrupt: Select the SDIO interrupt source 528 * The parameter can be any combination of following values: 529 * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt 530 * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt 531 * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt 532 * @arg SDIO_INT_DATATO: Data timeout interrupt 533 * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt 534 * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt 535 * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt 536 * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt 537 * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt 538 * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt 539 * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt 540 * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt 541 * @arg SDIO_INT_TXACT: Data transmit in progress interrupt 542 * @arg SDIO_INT_RXACT: Data receive in progress interrupt 543 * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt 544 * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt 545 * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt 546 * @arg SDIO_INT_RXFF: Receive FIFO full interrupt 547 * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt 548 * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt 549 * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt 550 * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt 551 * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt 552 * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt 553 * @retval None 554 */ SDIO_EnableInterrupt(uint32_t interrupt)555void SDIO_EnableInterrupt(uint32_t interrupt) 556 { 557 SDIO->MASK |= interrupt; 558 } 559 560 /*! 561 * @brief Disables the specified SDIO interrupt 562 * 563 * @param interrupt: Select the SDIO interrupt source 564 * The parameter can be any combination of following values: 565 * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt 566 * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt 567 * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt 568 * @arg SDIO_INT_DATATO: Data timeout interrupt 569 * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt 570 * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt 571 * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt 572 * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt 573 * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt 574 * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt 575 * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt 576 * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt 577 * @arg SDIO_INT_TXACT: Data transmit in progress interrupt 578 * @arg SDIO_INT_RXACT: Data receive in progress interrupt 579 * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt 580 * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt 581 * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt 582 * @arg SDIO_INT_RXFF: Receive FIFO full interrupt 583 * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt 584 * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt 585 * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt 586 * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt 587 * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt 588 * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt 589 * @retval None 590 */ SDIO_DisableInterrupt(uint32_t interrupt)591void SDIO_DisableInterrupt(uint32_t interrupt) 592 { 593 SDIO->MASK &= ~interrupt; 594 } 595 596 /*! 597 * @brief Reads the specified SDIO flag 598 * 599 * @param flag: Select the flag to read 600 * The parameter can be one of following values: 601 * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag 602 * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag 603 * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag 604 * @arg SDIO_FLAG_DATATO: Data timeout flag 605 * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag 606 * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag 607 * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag 608 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag 609 * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag 610 * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag 611 * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag 612 * @arg SDIO_FLAG_CMDACT: Command transfer in progress flag 613 * @arg SDIO_FLAG_TXACT: Data transmit in progress flag 614 * @arg SDIO_FLAG_RXACT: Data receive in progress flag 615 * @arg SDIO_FLAG_TXFHF: Transmit FIFO Half Empty flag 616 * @arg SDIO_FLAG_RXFHF: Receive FIFO Half Full flag 617 * @arg SDIO_FLAG_TXFF: Transmit FIFO full flag 618 * @arg SDIO_FLAG_RXFF: Receive FIFO full flag 619 * @arg SDIO_FLAG_TXFE: Transmit FIFO empty flag 620 * @arg SDIO_FLAG_RXFE: Receive FIFO empty flag 621 * @arg SDIO_FLAG_TXDA: Data available in transmit FIFO flag 622 * @arg SDIO_FLAG_RXDA: Data available in receive FIFO flag 623 * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag 624 * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag 625 * 626 * @retval SET or RESET 627 */ SDIO_ReadStatusFlag(SDIO_FLAG_T flag)628uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag) 629 { 630 uint8_t bitstatus = RESET; 631 632 if ((SDIO->STS & flag) != (uint32_t)RESET) 633 { 634 bitstatus = SET; 635 } 636 else 637 { 638 bitstatus = RESET; 639 } 640 return bitstatus; 641 } 642 643 /*! 644 * @brief Clears the specified SDIO flag 645 * 646 * @param flag: Select the flag to clear 647 * The parameter can be any combination of following values: 648 * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag 649 * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag 650 * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag 651 * @arg SDIO_FLAG_DATATO: Data timeout flag 652 * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag 653 * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag 654 * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag 655 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag 656 * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag 657 * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag 658 * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag 659 * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag 660 * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag 661 * 662 * @retval None 663 */ SDIO_ClearStatusFlag(uint32_t flag)664void SDIO_ClearStatusFlag(uint32_t flag) 665 { 666 SDIO->ICF = flag; 667 } 668 669 /*! 670 * @brief Reads the specified SDIO Interrupt flag 671 * 672 * @param flag: Select the SDIO interrupt source 673 * The parameter can be one of following values: 674 * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt 675 * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt 676 * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt 677 * @arg SDIO_INT_DATATO: Data timeout interrupt 678 * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt 679 * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt 680 * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt 681 * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt 682 * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt 683 * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt 684 * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt 685 * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt 686 * @arg SDIO_INT_TXACT: Data transmit in progress interrupt 687 * @arg SDIO_INT_RXACT: Data receive in progress interrupt 688 * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt 689 * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt 690 * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt 691 * @arg SDIO_INT_RXFF: Receive FIFO full interrupt 692 * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt 693 * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt 694 * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt 695 * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt 696 * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt 697 * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt 698 * 699 * @retval SET or RESET 700 */ SDIO_ReadIntFlag(SDIO_INT_T flag)701uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag) 702 { 703 uint32_t intEnable; 704 uint32_t intStatus; 705 706 intEnable = (uint32_t)(SDIO->MASK & flag); 707 intStatus = (uint32_t)(SDIO->STS & flag); 708 709 if (intEnable && intStatus) 710 { 711 return SET; 712 } 713 714 return RESET; 715 } 716 717 /*! 718 * @brief Clears the specified SDIO Interrupt pending bits 719 * 720 * @param flag: Select the SDIO interrupt source 721 * The parameter can be any combination of following values: 722 * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt 723 * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt 724 * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt 725 * @arg SDIO_INT_DATATO: Data timeout interrupt 726 * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt 727 * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt 728 * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt 729 * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt 730 * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt 731 * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt 732 * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt 733 * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt 734 * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt 735 * 736 * @retval None 737 */ SDIO_ClearIntFlag(uint32_t flag)738void SDIO_ClearIntFlag(uint32_t flag) 739 { 740 SDIO->ICF = flag; 741 } 742 743 /**@} end of group SDIO_Functions */ 744 /**@} end of group SDIO_Driver */ 745 /**@} end of group APM32E10x_StdPeriphDriver */ 746